TWI458231B - To avoid the sleep mode output below the cut-off voltage of the power output stage circuit - Google Patents

Description

Avoid the sleep mode output lower than the cutoff voltage of the power output stage circuit

The present invention relates to a power supply, and more particularly to a power supply output stage circuit of a power supply.

At present, in order to achieve environmental protection and power saving, computer, server or computer peripheral products, such as printers, etc., have built-in sleep mode, which means that when these electrical products are in a low-power state, they will control them. The power supply circuit pulls down its output voltage to achieve energy savings.

Please refer to FIG. 9 , which is a power output stage circuit 50 of a power supply with a sleep mode, comprising: a power output circuit comprising a DC output unit R1 , R2 , LED , and a high potential output terminal Vo and a grounding terminal GND; a discharge unit 60 is connected between the DC output unit R1, R2, LED, the high potential output terminal Vo and the grounding terminal GND of the power output circuit; wherein the discharge unit includes a point The voltage regulator R4, R5 and an RC negative feedback circuit comprise an operational amplifier 61 and an RC circuit, and the RC circuit R3, C1 and the lower resistor R5 of the voltage divider are connected to the operational amplifier An inverting input terminal (-) of 61, a forward input terminal (+) of the operational amplifier is connected to a reference voltage source Vref; a sleep triggering unit 70 is connected between the discharge unit 60 and the ground GND, and The sleep triggering unit 70 is connected to an external sleep signal source. The sleep trigger unit 70 includes an NPN transistor Q and a parallel resistor R6. The parallel resistor R6 is connected in series with the NPN transistor Q1 and then connected in parallel to the discharge unit. The resistor R5 under the voltage divider of 60.

When the power output stage circuit 50 is in the normal operation mode, the sleep trigger unit 70 receives the high potential signal outputted by the external sleep signal source, as shown in FIG. 10A, at which time the NPN transistor Q is turned on to the ground to make the parallel connection. The resistor R6 is connected in parallel with the resistor R5 under the voltage divider of the discharge unit 60. Since the resistor is reduced in parallel with the parallel resistor R6, the discharge unit 60 compares the voltage of the reference voltage source Vref (about 2.5V). And the lower resistor R5 voltage drop V3, since the voltage of the reference voltage source Vref is set higher than the lower resistor R5 voltage drop V3, the output potential of the operational amplifier 61 is high voltage, so the RC circuit R3, C1 is not connected to the ground. The terminal GND is discharged while maintaining the high potential output of the discharge cell 60 at a high voltage section (e.g., +32V).

Referring to FIG. 10B again, when the sleep trigger unit 70 of the power output stage circuit 50 receives the low potential signal (sleep signal) output by the external sleep signal source, the NPN transistor Q will not be turned on, and the parallel connection. The resistor R6 is no longer connected in parallel with the lower resistor R5 to float the NC, so that the voltage drop of the lower resistor R5 is increased and exceeds the voltage of the reference voltage source Vref, so that the output potential of the operational amplifier 61 is low, that is, the operational amplifier 61 The output equivalent circuit is connected to the ground, so that the high-potential output terminal Vo is discharged to the ground GND through the upper resistor R4 and the RC circuit R3, C1, and the high-voltage section is quickly pulled to a low-voltage section (such as +12V). ), and achieve the purpose of reducing DC power.

However, please refer to FIG. 11 , which is a voltage waveform diagram of each node during the period from the high voltage section to the low voltage section when the power output stage circuit 50 enters the sleep mode; as shown in the figure, when the NPN transistor Q is When the conduction to the non-conduction moment (between T1 and T2), the voltage drop of the lower resistor R5 rises (>2.5V), and the original operational amplifier 61 is connected to the high-potential output terminal Vo through the resistor R1 of the DC output unit. The output voltage voltage V1 (about 30V) will be steeply reduced to the clamp potential (about 2.5V) inside the output of the operational amplifier 61, and the high-potential output current I _Vo will be extracted to make the high-voltage section (+32V) Beginning to reduce to the low voltage section (+12V), at the same time, the capacitance C1 of the RC circuit R3, C1 is also steeped down to the clamp potential (about 2.5V) inside the output of the operational amplifier due to the output of the operational amplifier 61. Fast discharge.

Ideally, the high-potential output terminal Vo should be maintained after reaching the low-voltage section, but the high-potential output terminal Vo should be close to the low-voltage section, the potential of the output terminal of the operational amplifier 61 has risen, and the capacitance C1 of the RC circuit will be Therefore, charging is started, and the charging current causes the voltage drop of the lower resistor R5 to rise slightly, and the voltage lowering speed thereof becomes slow, and the state in which the high-potential output terminal Vo has reached the low-voltage section cannot be immediately reacted to the operational amplifier 61; As shown in FIG. 11, during the charging process, the voltage drop of the lower resistor R5 is still higher than the voltage (2.5V) of the reference voltage source Vref, so that the potential of the output terminal of the operational amplifier 61 is pulled low again, and the high potential is continuously drawn. The current I _Vo at the output terminal makes the potential of the high potential output terminal Vo lower than the low voltage section; after a period of T3, the voltage drop V3 of the lower resistor R5 is lower than the voltage of the reference voltage source (2.5V), so that the operational amplifier The output of 61 exhibits a high potential, so that the capacitance C1 of the RC circuit R3, C1 is stably charged, and the potential of the high potential output terminal Vo also returns to the low voltage section. However, during the T3 time, the high-potential output voltage is lower than the low-voltage section, and the electrical product enters the shutdown mode or the restart mode from the sleep mode.

Therefore, if the power output stage circuit of the power supply with the sleep mode causes the shutdown or restart mode of the electrical product due to energy saving, affecting the normal operation, it will not be acceptable to the user, and further improvement is necessary.

In view of the technical defect that the power supply output stage circuit of the power supply device enters the sleep mode and the output voltage is lower than the system cutoff voltage, and the system is restarted, the main purpose of the present invention is to provide a power output that avoids the sleep mode output being lower than the cutoff voltage. Stage circuit.

The main technical means used to achieve the above purpose is that the power output stage circuit includes: a power output circuit comprising a DC output unit, a high potential output terminal and a ground terminal; a discharge unit is connected to Between the DC output unit of the power output circuit, the high potential output terminal and the ground terminal; wherein the discharge unit includes a voltage divider and an RC negative feedback circuit, the RC negative feedback circuit includes an operational amplifier and An RC circuit, the first end of the RC circuit and the lower resistor of the voltage divider are connected to the inverting input of the operational amplifier, and the forward input of the operational amplifier is connected to a reference voltage source, and the operational amplifier is The output is connected to the second end of the RC circuit; a sleep trigger unit is connected between the discharge unit and the ground, and is connected to an external sleep signal source; wherein the sleep trigger unit includes an electronic switch and a parallel resistor, the parallel circuit is connected in series with the electronic switch and then connected in parallel to the resistor under the voltage divider of the discharge unit; and a voltage follower circuit is connected to The second end of the RC circuit adjusts the voltage of the second terminal of the RC circuit to decrease in a step-down ratio during the discharge of the RC circuit.

The above invention mainly adds a voltage follower circuit to the second of the capacitor After the discharge unit enters the sleep mode, when the voltage of the second end of the capacitor is lower than the first end and begins to discharge, the voltage of the second terminal is controlled by the voltage follower circuit to decrease with the step-down ratio of the high potential output terminal. Maintaining the discharge of the RC circuit; thus, when the high-potential output terminal of the power output circuit is lowered from the high-voltage section to the low-voltage section, the capacitor does not increase the potential of the output terminal of the operational amplifier, so that the voltage of the second terminal is higher than the voltage of the first terminal. The charging current is generated, so the lower resistance is not affected by the charging current, and the simple reaction high-potential output terminal is lowered from the high-voltage section to the low-voltage section, so that the potential of the output terminal of the operational amplifier rises back to a high potential, so that the RC circuit is no longer discharged. Therefore, the power output stage circuit of the invention ensures that after receiving the sleep signal, the minimum voltage of the output DC power source is not lower than the preset low voltage section, and has the functions of energy saving and no load shutdown or restart.

Referring to FIG. 1 , a circuit diagram of a first preferred embodiment of the power output stage circuit 10 of the present invention includes: a power output circuit including a DC output unit R1, R2, LED, and a high a potential output terminal Vo and a ground terminal GND; a discharge unit 20 is connected between the DC output unit R1, R2, LED, the high potential output terminal Vo and the ground terminal GND of the power output circuit; wherein the discharge unit 20 The system includes a voltage divider R4, R6 and an RC negative feedback circuit, the RC negative feedback circuit includes an operational amplifier 21 and an RC circuit R3, C1, the first end of the RC circuit R3, C1 and the voltage divider The lower resistor R5 of the device is connected to the inverting input terminal (-) of the operational amplifier 21, and the forward input terminal (+) of the operational amplifier 21 is connected to a reference voltage. The source Vref, the output of the operational amplifier 21 is connected to the second end of the RC circuit R3, C1; a sleep trigger unit 30 is connected between the discharge unit 20 and the ground GND, and provides an external sleep The signal source is connected; wherein the sleep trigger unit 30 includes an electronic switch Q and a parallel resistor R6. The parallel resistor R6 is connected in series with the electronic switch Q and then connected in parallel to the resistor R5 under the voltage divider of the discharge unit 20; The electronic switch Q is a transistor, in the present embodiment, an NPN transistor is used; and a voltage follower circuit is connected to the second end of the RC circuit R3, C1, and is adjusted during the discharge of the RC circuit R3, C1. The voltage of the second terminal of the RC circuit R3 and C1 is decreased according to the step-down ratio of the high potential output terminal; in the embodiment, the voltage follower circuit is a Zener diode ZD.

Referring to FIG. 2A, when the power output stage circuit 10 of the present invention is in a normal operation mode, the electronic switch Q receives the high-potential signal outputted by the sleep signal source system. At this time, the NPN transistor Q is turned on. The parallel resistor R6 is connected in parallel with the lower resistor R5, and the voltage drop of the lower resistor R5 is pulled lower than the reference voltage source voltage Vref, so that the output terminal of the operational amplifier 21 is at a high potential, and the output diode ZD is not The crash is turned on, and the RC circuits R3 and C1 are not discharged, and the high-potential output terminal Vo voltage is maintained at the high voltage section.

Referring to FIG. 2B, when the electronic switch Q of the power output stage circuit 10 of the present invention receives the low potential signal outputted by the sleep signal source system, the NPN transistor Q is not turned on and enters the sleep mode. R6 is no longer connected in parallel with the lower resistor to float the NC, so that the voltage drop of the lower resistor R5 is raised and higher than the voltage of the reference voltage source Vref. At this time, the equivalent circuit of the output terminal of the operational amplifier 21 is turned on to the ground GND. And maintain a clamp Bit (depending on the impedance of the op amp, taking 2.5V as an example). Since the potential of the output of the operational amplifier is dropped (from 30V to 2.5V), the anode potential of the Zener diode ZD is lowered, and the breakdown maintains a certain voltage drop, so the capacitance C1 of the RC circuit R3, C1 The voltage at the second end is the voltage of the high potential output terminal Vo minus the breakdown voltage of the Zener diode ZD. Since the voltage at the second terminal is lower than the voltage at the first terminal, the RC circuits R3 and C1 start to discharge, and the capacitor C1 is second. The terminal voltage begins to decrease as the voltage of the high-potential output terminal Vo decreases. As shown in FIG. 3, the voltage V2 at the second terminal of the capacitor C1, that is, the voltage drop rate following the high-potential output terminal Vo decreases, and the waveform decreases almost in parallel. . When the voltage of the high potential output terminal Vo reaches the preset low voltage section, the voltage of the first terminal of the capacitor C1 will be close to the voltage of the second terminal, but will not be lower than the voltage of the second terminal, so the capacitor C1 will not generate a charging current. Flowing through the lower resistor R5; thus, the lower resistor R5 can simply react the voltage of the high-potential output terminal Vo to the inverting input terminal (-) without being affected by the RC circuits R3 and C1, so the operational amplifier 21, when the voltage of the high potential output terminal Vo has reached a preset low voltage section, the output terminal potential is pulled high to a high potential, so that the RC circuits R3 and C1 are no longer discharged and the voltage of the high potential output terminal Vo is pulled down. The high-potential output terminal Vo is maintained at a low pressure section and not lower than a low pressure section.

Referring to FIG. 4, it is a second preferred embodiment of the power output stage circuit 10b of the present invention, which is substantially the same as the first preferred embodiment, except that the voltage follower circuit is a current limiting resistor R1. The current resistor R1 is connected between the RC circuit R3, C1 and the output terminal of the operational amplifier 21, that is, the resistor R3 of the RC circuit is connected to the second end of the capacitor C1; preferably, the DC output unit can be The first resistor R1 serves as the current limiting resistor R1 of the voltage follower circuit of the present embodiment, and can have both electronic component cost saving benefits.

When the sleep mode is entered in the embodiment, the current limiting resistor R1 is connected in series to the discharge path of the RC circuit R3 and C1. Therefore, as shown in FIG. 5A and FIG. 5B, the capacitor C1 has a second terminal voltage V2 and a current limiting resistor and an RC. The circuit connection node voltage V1 synchronously follows the voltage drop ratio of the high potential output terminal Vo, and the waveform decreases almost in parallel, as shown in FIG. 6. When the voltage of the high potential output terminal Vo reaches the preset low voltage section, the voltage of the first terminal of the capacitor C1 will be close to the voltage of the second terminal, but will not be lower than the voltage of the second terminal, so the capacitor C1 will not generate a charging current. Flowing through the lower resistor R5; thus, the lower resistor R5 can simply react the voltage of the high-potential output terminal to a predetermined low-voltage stage to the inverting input terminal (-) of the operational amplifier 21, without being affected by the RC circuit R3, The influence of C1, the operational amplifier 21 can pull the output potential to a high potential when the voltage of the high-potential output terminal Vo has reached a preset low-voltage stage, so that the RC circuits R3 and C1 are no longer discharged and are pulled low. The voltage of the high potential output terminal Vo maintains the high potential output terminal Vo at the low pressure section and not lower than the low pressure section.

In addition, as shown in FIG. 7, it is an internal circuit of a three-terminal adjustable shunt reference source (TL431) with good thermal stability, and includes an operational amplifier 21, a transistor 22, and a diode connected in parallel therewith. The body 23, as shown in FIG. 8A and FIG. 8B, can replace the above-mentioned operational amplifier to realize the circuit of the discharge unit, that is, the anode (+) is connected to the ground GND, and the cathode (-) is connected to the RC circuit R3. The second end of C1, and the reference terminal Vref is connected to the reference voltage source.

In summary, the present invention mainly adds a voltage follower circuit to the second end of the capacitor, so that after the discharge cell enters the sleep mode, when the voltage of the second terminal of the capacitor is lower than the first end and begins to discharge, the voltage follows the circuit. Controlling the voltage of the second terminal to decrease with the step-down ratio of the high-potential output terminal, maintaining the RC circuit Discharge; thus, when the high-potential output terminal of the power output circuit is lowered from the high-voltage section to the low-voltage section, the capacitor does not generate a charging current because the potential of the output terminal of the operational amplifier is increased and the voltage of the second terminal is higher than the voltage of the first terminal. Therefore, the lower resistance is not affected by the charging current, and the simple reaction high-potential output terminal is lowered from the high-voltage section to the low-voltage section, so that the potential of the output terminal of the operational amplifier rises back to a high potential, so that the RC circuit is no longer discharged; The power output stage circuit of the invention ensures that after receiving the sleep signal, the minimum voltage of the output DC power source is not lower than the preset low voltage section, and has the functions of energy saving and no load shutdown or restart.

10‧‧‧Power output circuit

20‧‧‧discharge unit

21‧‧‧Operational Amplifier

22‧‧‧Optoelectronics

23‧‧‧ diode

30‧‧‧Sleep trigger unit

50‧‧‧Power output circuit

60‧‧‧discharge unit

61‧‧‧Operational Amplifier

70‧‧‧Sleep trigger unit

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a circuit diagram showing a first preferred embodiment of the power supply output stage circuit of the present invention.

Figure 2A is an equivalent circuit diagram of Figure 1 in a normal mode of operation.

Figure 2B is an equivalent circuit diagram of Figure 1 in sleep mode.

Figure 3: Figure 1 shows the voltage waveforms of each node in sleep mode.

Figure 4 is a circuit diagram showing a first preferred embodiment of the power supply output stage circuit of the present invention.

Figure 5A is an equivalent circuit diagram of Figure 4 in a normal mode of operation.

Figure 5B is an equivalent circuit diagram of Figure 4 in sleep mode.

Figure 6 is a waveform diagram of the voltages of the nodes in Figure 4 in sleep mode.

Figure 7: A circuit diagram of a three-terminal adjustable shunt reference.

Figure 8A is a circuit diagram showing a third preferred embodiment of the power supply output stage circuit of the present invention.

8B is a circuit diagram showing a fourth preferred embodiment of the power output stage circuit of the present invention Figure.

Figure 9: Circuit diagram of an existing power supply output stage circuit.

Figure 10A is an equivalent circuit diagram of Figure 9 in a normal mode of operation.

Figure 10A is an equivalent circuit diagram of Figure 9 in sleep mode.

Figure 11 is a voltage waveform diagram of each node in Figure 9 in sleep mode.

10‧‧‧Power output circuit

20‧‧‧discharge unit

21‧‧‧Operational Amplifier

30‧‧‧Sleep trigger unit

Claims (10)

A power output stage circuit for preventing a sleep mode output from being lower than a cutoff voltage, comprising: a power output circuit comprising a DC output unit, a high potential output terminal and a ground terminal; a discharge unit connected to the power source The DC output unit of the output circuit, the high potential output end and the ground end; wherein the discharge unit includes a voltage divider and an RC negative feedback circuit, the RC negative feedback circuit includes an operational amplifier and an RC circuit The first end of the RC circuit and the lower resistor of the voltage divider are connected to the inverting input terminal of the operational amplifier, the positive input terminal of the operational amplifier is connected to a reference voltage source, and the output end of the operational amplifier is Connected to the second end of the RC circuit; a sleep trigger unit is connected between the discharge unit and the ground, and is connected to an external sleep signal source; wherein the sleep trigger unit includes an electronic switch and a parallel resistor The parallel circuit is connected in series with the electronic switch and then connected in parallel to the resistor under the voltage divider of the discharge unit; and a voltage follower circuit is connected to the RC The second end of the path, the RC circuit during discharging, the second end of the RC circuit adjusting the voltage drop by the high-potential output terminal of the step-down ratio. The power output stage circuit of claim 1 is characterized in that the voltage follower circuit comprises a register diode, the cathode of which is connected to the high potential output, and the anode is connected to the second end of the capacitor. The power output stage circuit of claim 2, wherein the DC output unit comprises a light-emitting diode of an optical coupler and a first resistor connected to the high-potential output terminal, and a parallel connection of the light-emitting diode And the first electricity The second resistance of the resistor. The power supply output stage circuit of claim 1, wherein the voltage follower circuit comprises a current limiting resistor connected between the second end of the RC circuit and the output of the operational amplifier. The power output stage circuit of claim 4, wherein the DC output unit comprises a light emitting diode of an optical coupler and a resistor connected in parallel therewith. The power output stage circuit of any one of claims 1 to 5, wherein the operational amplifier is a three-terminal adjustable shunt reference source comprising an anode, a cathode and a reference end; wherein the anode is connected to The ground terminal is connected to the second end of the RC circuit, and the reference terminal is connected to the reference voltage source. The power output stage circuit of any one of claims 1 to 5, wherein the electronic open relationship is a transistor. The power output stage circuit of claim 6, wherein the electronic open relationship is a transistor. The power output stage circuit of claim 7, wherein the electronic open relationship is an NPN transistor. The power output stage circuit of claim 8, wherein the electronic open relationship is an NPN transistor.