TWI424674B - Method of forming a buck-boost mode power supply controller and structure therefor - Google Patents

Description

Method and structure for forming a down-boost mode power supply controller

The present invention relates generally to the field of electronics, and more particularly to methods of forming semiconductor devices and structures.

In the past, the semiconductor industry has used various methods and structures to implement switching power supply controllers, such as pulse width modulation (PWM) power supply controllers. Systems that use such switched power supply controllers are typically configured as a boost system or a buck system. Some systems are implemented as a system with both buck and boost, or a drop-boost system. One example of such a drop-boost system is disclosed in U.S. Patent No. 6,166,527, issued to Dwelley et al. One of the problems with such a down-boost system is that the efficiency in the down-boost mode is usually not as high as it is. In addition, the circuitry used to implement the drop-boost system is often very complex, resulting in extremely high cost.

Accordingly, the present invention contemplates a switched power supply controller that can operate in a down-boost mode of operation with extremely high efficiency, a simpler implementation, and very low cost.

FIG. 1 schematically illustrates a schematic diagram of a particular embodiment of a portion of a power supply system 10 having an exemplary version of a power supply controller 25. Controller 25 receives a signal having multiple signal levels to represent multiple functional states.

The power supply system 10 typically receives power from a step-down between a power input terminal 11 and a power return terminal 12 and forms an output voltage between an output node 13 and the terminal 12. Load 15 can be connected for receiving the output voltage and a load current from output node 13 and terminal 12. The buck applied between terminals 11 and 12 can be a dc voltage that will be rectified, such as a half-wave rectified sine wave. System 10 typically includes an inductor 14 controlled by controller 25 for forming the output voltage. System 10 also typically includes a feedback network as shown by series coupled resistors 18 and 19 for providing a sensed signal (e.g., feedback (FB) signal) for representing output node 13 and terminal The value of the output voltage between 12. The sensing signal is formed at a sensing node 20. Such feedback (FB) networks and feedback (FB) signals are well known to those skilled in the art.

The exemplary version of controller 25 shown in FIG. 1 typically receives power from a step-down between a voltage input 26 and a voltage return terminal 27. Input 26 will typically be connected to terminal 11, and return terminal 27 will typically be connected to terminal 12. Inductor 14 will be coupled to inductor inputs 28 and 29 of controller 25. The controller 25 typically includes: a switching control section 49; a PWM control section 53; an error amplifier 55; a reference generator or reference device 56; an internal regulator or regulator 58; and a plurality of power switches, such as The first power transistor 35, the second power transistor 36, the third power transistor 37, and the fourth power transistor 38. Regulator 58 is typically coupled between input 26 and return terminal 27 for receiving an input voltage from input 26. Regulator 58 will form an internal operating voltage on an output 59 for operating other components of controller 25, including switching control section 49, PWM control section 53, reference means 56, and error amplifier 55. The error amplifier 55 receives the sensing signal (such as a feedback (FB) signal) on a sensing input 32, and forms an error signal on the output of the amplifier 55 to represent the value of the output voltage and the output voltage. The difference between the Greek values. The PWM control section 53 receives the error signal from amplifier 55 and forms a PWM control (PCS) signal for operating transistors 35 through 38 to adjust the value of the output voltage. The PWM control section 53 may have various modes of implementation that are well known to those skilled in the art. One of the examples of a suitable PWM control section is disclosed in U.S. Patent No. 5,859,768, issued toJ.S. In the preferred embodiment, the PWM control section 53 is a fixed frequency current mode PWM controller. Thus, the PCS signal has a fixed frequency and the duty cycle is known to those skilled in the art. Depends on the value of the output voltage.

As will be further seen below, the controller 25 is configured to operate the operating system 10 in a buck mode, a boost mode, or a down-boost mode. The switching control section 49 is configured to set the mode of operation of the controller 25 and to use the PCS signal to control the function of the selected mode of operation. The switching control section 49 is configured to operate the system 10 in the boost mode by actuating the transistor 35, canceling the transistor 36, and switching the transistors 37 and 38 using the PCS signal in response to the value of the output voltage. . The switching control section 49 is configured to operate the system 10 in the buck mode by actuating the transistor 37, canceling the transistor 38, and switching the transistors 35 and 36 using the PCS signal in response to the value of the output voltage. . In the down-boost mode, the switching control section 49 is configured to form one cycle of the down-boost mode into three portions. During a portion of the down-boost mode cycle, the switching control section 49 is configured to couple the inductor 14 to receive power from the input 26. During the second portion of the down-boost mode cycle, the switching control section 49 is configured to couple the inductor 14 to supply power to the output node 13 and the load 15; and in the down-boost mode During the third portion of the cycle, the switching control section 49 is configured to couple the inductor 14 to receive the input voltage from the input 26 and to couple the power to the output node 13 and the load 15. During one of the three aforementioned portions of the down-boost mode operation cycle, one of the transistors 35-38 is actuated for a fixed portion of the down-boost mode cycle. The other two parts of the down-boost mode operation cycle use the PCS signal to control transistors 35 through 38. The fixed portion will be selected as a fixed percentage of the period of the cycle. For example, a fixed amount of time or a fixed percentage of the period of the cycle. If the fixed time amount is too short or the fixed percentage is too low, it may be difficult to accurately adjust the value of the output voltage.

An exemplary embodiment of the switching control section 49 shown in FIG. 1 includes a mode detection circuit or mode detector 40, a pulse generator 50, and a logic/driver or logic/driver block 60. The pulse generator 50 receives the PCS signal from the PWM control section 53 and forms two pulse signals to help form the aforementioned three portions of the down-boost cycle. The generator 50 receives the PCS signal and forms a TO pulse signal on an output 51 and a TE pulse signal on an output 52. The mode detector 40 receives the input voltage and the output voltage and forms a control signal for setting the operating mode of the controller 25. A buck control (BU) signal will be asserted to indicate that controller 25 should operate in the buck mode of operation, and a boost control (BO) signal will be asserted to indicate that controller 25 should operate Among the boost mode of operation. The detector 40 negates the BU signal and the BO signal to indicate that the controller 25 should operate in the down-boost mode. In the exemplary embodiment shown in FIG. 1, the detector 40 includes a boost comparator 45, a boost current source 46, a boost resistor 47, a buck reference comparator 41, and a step-down current. Source 42 and a buck resistor 43. If the value of the input voltage minus the value of the output voltage is greater than the first threshold established by the current source 42 and the resistor 43, then the output of the comparator 41 will be at a high level for determining the buck control (BU). )signal. If the value of the input voltage minus the value of the output voltage is less than the second threshold established by the current source 46 and the resistor 47, then the output of the comparator 45 will be at a high level to force the boost control (BO) signal. It is a high level and is used to determine the boost control (BO) signal. If the value of the input voltage minus the output voltage is less than the first threshold but greater than the second threshold, then the outputs of the comparators 41 and 45 are both at a low level, thereby forcing both the BU signal and the BO signal. It is at a low level to indicate that the controller 25 should operate in the down-boost mode to determine the down-boost mode. The range between the first threshold and the second threshold is chosen to be very narrow enough to provide the greatest advantage of the down-boost mode of operation described herein, but must be wide enough to be sufficient for each A PWM cycle provides sufficient time. In the preferred embodiment, the difference between the first threshold and the second threshold is about 1.3 volts. However, the range can also be large or small enough.

FIG. 2 schematically illustrates an exemplary embodiment of logic within block 60. Block 60 receives the BU signal and the BO signal and uses the states of the BU and BO signals to set the operational state of controller 25 and to control the operation of transistors 35-38. Block 60 also receives the PCS signal from PWM control section 53 and the pulse control signals TO and TE from generator 50. The outputs 86, 87, 88, and 89 of block 60 are located thereon, and block 60 forms individual drive signals A, B, C, and D for driving individual transistors 35, 36, 37, and 38. . Exemplary embodiments of block 60 shown in FIG. 2 include AND gates 65, 68, 69, 70, 79, 80, and 85; NAND gates 72 and 83; inverters 63, 64, 66, 75 And 76; OR gates 67, 77, and 84; and NOR gates 62, 71, and 82. Please refer to Figure 1 and Figure 2 for this description.

In operation, if the value of the input voltage minus the output voltage is greater than the first threshold, the controller 25 operates in the buck mode. The detector 40 determines the BU signal and rejects the BO signal. Block 60 receives the BO and BU signals. A high level BU signal forces the output of gate 62 to a low level, thereby forcing the down-boost (BB) signal to become a low level. The low level signal from gate 62 forces the output of gate 72 to a high level to actuate gates 69 and 70 while forcing the outputs of gates 83 and 84 to a high level to actuate an input of gate 85. . This high level BU signal forces the output of gate 77 to a high level to actuate an input of gate 79. This high level BU signal also forces the outputs of inverters 66 and 76 to go low. The low level signal from inverter 76 forces the output of gate 80 to a low level, causing the C drive signal to also become a low level to cancel transistor 36. The low level signal from the C drive signal is delayed by a delay element or delay 73 and received by the gate 67 to actuate an input of the gate 67. The low level signal from inverter 66 forces the output of gate 68 to a low level, which also forces the output of gate 70 to a low level, causing the D drive signal on output 89 to go low to actuate the transistor. . Actuating the transistor 37 couples the input 29 to the output 31 of the controller 25, thereby coupling a terminal of the inductor 14 to the output 31 of the controller 25, which in turn is coupled to the output node 13. The low level signal from the D drive signal is delayed by a delay element or delay 78 and is received by an input of gate 77 without any effect on gate 77. The low level BO signal forces the output of the inverter 63 to a high level to actuate an input of the gate 65 and simultaneously actuate an input of the gates 80 and 82. When the PWM control section 53 forces the PCS signal to a high level to initiate a cycle of the boost mode, the high level PCS signal forces the output of the gate 67 to a high level. The high level signal from gate 67 forces the output of gate 71 to a low level, thereby forcing the output of gate 69 to a low level, thus causing the B drive signal on output 87 to go low. The low level B drive signal is received by a delay 74 which delays the B drive signal before the B drive signal is received by the inverter 75. The low level signal from delay 74 forces the output of inverter 75 received by gate 79 to a high level. Since the PCS signal is also at a high level, the high level signal from the inverter 75 forces the output of the gate 79 to a high level. The high level signal from gate 79 forces the output of gate 82 to a low level, thereby forcing the output of gate 85 to a low level, thus causing output 86 and A drive signals to become low. The low level A drive signal will actuate the transistor 35. The low level A drive signal is also received by delay 61, which delays the low level signal before inverter 64 receives the low level signal, thereby forcing the output of inverter 64 to go high. Since the other input of the gate 65 is already at a high level, the high level signal from the inverter 64 forces the output of the gate 65 to a high level, which does not have any effect on the gate 67 because The input is already at a high level. Thus, it can be seen that the positive PCS signal will force the A drive signal to a low level, thereby actuating the transistor 35. The actuation transistor 35 will couple the input 28 such that the inductor 14 will be coupled to receive power from the input 26. Because the transistors 35 and 37 are actuated, current flows from the input 26 through the transistor 35, through the input 28, to the inductor 14, through the input 29 and the transistor 37, to the output 31 and the output node. 13, in order to supply current to the load 15.

The transistor 35 will remain activated until the sense signal on input 32 forces the PWM control section 53 to negate the PCS signal. The falling edge of the PCS signal is received by generator 50, which produces an output pulse having a fixed width on the TO output. The fixed pulse width can be achieved by various well known pulse generating circuits, such as a click circuit or other equivalent circuit. For example, the pulse width can be formed as a fixed percentage of the duration of each cycle formed by controller 53, such as by a counter driven by an oscillator used to form the cycle. The TO signal that is positively advanced will be received by the gate 84, which does not produce any effect because the other input of the gate 84 is already at a high level. When the fixed pulse width from the TO signal becomes a low level, the generator 50 forces the TE signal to a high level in the remainder of the PCS cycle until the PCS signal again becomes a high level. The TE signal can be generated from the TO signals and the PCS signals using simple logic circuits such as a NOR gate. The TE signal going to the high level will be received by the gate 72, which does not produce any effect because the other input of the gate 72 is already at a low level. The PCS signal going to the lower level will also be received by block 60. This low level PCS signal forces the output of gate 79 to a low level, which forces the output of gate 82 to a high level. The high level signal from gate 82 is received by gate 85 and forces the output to go high because the other input of gate 85 is already at a high level. The high level signal from gate 85 forces the A drive signal to a high level to cancel transistor 35. The high level signal on output 86 is received by delay 61, which delays the high level signal before inverter 64 receives it. The high level signal from the delay 61 forces the output of the inverter 64 to a low level, thereby forcing the output of the gate 65 to become a low level. Since the PCS signal has forced the other input of the gate 67 to a low level, the low level signal from the gate 65 forces the output of the gate 67 to a low level, thereby forcing the output of the gate 71 to become a high level. . Since the other input of the gate 69 is at a high level, the high level signal from the gate 71 forces the output of the gate 69 to a high level, thereby forcing the B drive signal on the output 87 to become a high level, thereby actuating the power. Crystal 36. Actuating transistor 36 couples input 28 to return terminal 27, thereby coupling a terminal of inductor 14 to return terminal 27 to begin discharging inductor 14. The high level B drive signal is received by delay 74, which delays the high level B drive signal before it is received by inverter 75. This high level signal forces the output of inverter 75 to a low level, which does not have any effect on gate 79 because the PCS signal is already at a low level. Therefore, the low level portion of the PCS signal negates the A drive signal and determines the B drive signal, thereby canceling the transistor 35 and actuating the transistor 36. As can be seen in the boost mode of operation, the high level BU signal forces the C drive signal and the D drive signal to a low level to actuate the transistor 37 and cancel the transistor 38, and switch back to the PCS signal. Crystals 35 and 36. Since the PCS signal will switch back to the value of the output voltage, the controller 25 will switch the transistors 35 and 36 in response to the value of the output voltage.

If the value of the input voltage minus the value of the output voltage is less than the second threshold, then the controller 25 will operate in the boost mode. The detector 40 determines the boost (BO) signal and rejects the buck (BU) signal. A high level BO signal forces the output of gate 62 to a low level, thereby forcing the down-boost (BB) signal to become a low level. The low level signal from the forcing gate 62 forces the output of the gate 72 to a high level to actuate the gates 69 and 70 while forcing the outputs of the gates 83 and 84 to a high level to actuate one of the gates 86. Input. This low level BU signal forces the output of inverter 66 to a high level to actuate an input of gate 68. The low level BU signal also activates an input of the gate 77 and forces the output of the inverter 76 to a high level. A high level signal from inverter 76 will actuate an input to gate 80. The high level BO signal forces the output of the inverter 63 to a low level, thereby forcing the output of the gate 65 to a low level to actuate an input of the gate 67. This high level BO signal forces the output of gate 82 to a low level, thereby forcing the output of gate 85 to a low level, thus causing the A drive signal on output 86 to go low. The low level A drive signal actuates the transistor 35 for coupling the input 28 to couple a terminal of the inductor 14 to receive power from the input 26. The low level A drive signal is also received by delay 61, which delays the low level signal before it is supplied to the input of inverter 64. The low level signal from delay 61 forces the output of inverter 64 to a high level, which does not have any effect on gate 65 because the other input is already at a low level. This high level BO signal also forces the output of gate 71 to a low level, thereby forcing the output of gate 69 to become a low level, thus causing the B drive signal on output 87 to go low to cancel transistor 36. The low level B drive signal is also received by delay 74, which delays the low level signal before it is supplied to the input of inverter 75. The low level signal from delay 74 forces the output of inverter 75 to a high level, which is received by an input of gate 79 to actuate the other input of gate 79.

When the PWM control section 53 forces the PCS signal to a high level, the high level signal forces the output of the gate 67 to a high level. The high level signal from gate 67 is received by gate 68, which forces the output to go high because the other input of gate 68 is already at a high level. The high level signal from gate 68 forces the output of gate 70 to a high level because the other input is already at a high level. The high level signal from gate 70 forces the D drive signal on output 89 to go high, thereby canceling transistor 37. The high level D drive signal is received by delay 78, which delays the high level signal before it is supplied to the input of gate 77. This high level signal will force the output of gate 77 to a high level, which will be received by gate 79. Since the PCS signal is already at a high level, the high level signal from gate 77 forces the output of gate 79 to a high level. The high level signal from gate 79 forces the output of gate 80 to a high level because the other input of gate 80 is already at a high level. The high level signal from gate 80 forces the C drive signal on output 88 to go high, thereby actuating transistor 38. Actuating transistor 38 couples input 29 to return terminal 27, thereby coupling a terminal of inductor 14 to return terminal 27 to charge inductor 14. The high level C drive signal is received by delay 73, which delays the high level signal before it is supplied to the input of gate 67, which does not have any effect on gate 67. Because an input is already at a high level.

The transistor 38 will remain activated until the sense signal on the input 32 forces the PWM control section 53 to negate the PCS signal. The falling edge of the PCS signal is received by the generator 50, which determines the fixed pulse width TO signal, which is followed by the TE signal. This TO signal does not have any effect on the gate 84 because the other input is already at a high level. The TE signal going to the high level will be received by the gate 72, which does not produce any effect because the other input of the gate 72 is already at a low level. The low level PCS signal forces the output of the gate 79 to a low level, thereby forcing the output of the gate 80 and the C drive signal to a low level, thereby canceling the transistor 38. The low level C drive signal is also received by delay 73, which delays the low level signal before it is sent to the input of gate 67. Since the PCS signal is also low level, the low level signal from the delay 73 forces the output of the gate 67 to a low level, thereby forcing the output of the gate 68 to become a low level. The low level signal from gate 68 forces the output of gate 70 to a low level, thereby forcing the D drive signal to become a low level and actuating transistor 37 for coupling output 31 to input 29 and to inductor 14. a terminal. The low level D drive signal is also received by delay 78, which delays the low level signal before it is supplied to an input of gate 77. Since the other input of the gate 77 is already at a low level, the low level signal from the delay 78 forces the output of the gate 77 to a low level, which does not have any effect on the gate 79 because of the PCS. The signal is already at a low level. Therefore, it can be seen in the boost mode that the determined boost signal and the negative buck signal actuate the transistor 35, cancel the transistor 36, and respond to the PCS signal, thereby responding to the output voltage. The values are used to switch between transistors 37 and 38.

If the value of the input voltage is less than the second threshold but less than the first threshold, then the boost (BO) signal and the buck (BU) signal are both at a low level, and the controller 25 will operate in the down-boost mode.

Figure 3 illustrates a diagram of a portion of the signal during operation of system 10 in a portion of the down-boost mode. The abscissa is time, and the ordinate is the incremental value of the signal of the signal being described. Curve 91 is the A drive signal on output 86 of block 60. Curve 92 is the B drive signal on output 87 of block 60. Curve 93 is the C drive signal on output 88 of block 60. Curve 94 is the D drive signal on output 89 of block 60. Curve 95 is the PCS signal from PWM control section 53. Curve 96 is the TO signal on output 51 of generator 50, and curve 97 is the TE signal on output 52 of generator 50. Please refer to Figure 1, Figure 2, and Figure 3 for this description.

In the down-boost mode, the controller 25 forms a cycle of the PCS control signal into three portions of a cycle, one of which has a fixed duration. The duration of one part is controlled according to the value of the output voltage, the duration of the other part is fixed, and the duration of the third part is the remainder of the cycle of the PWM controller, therefore The duration of the third part also returns the value of the output voltage. Forming a portion of the cycle to have a fixed duration improves operational efficiency. This three-phase operation also makes it easier to implement the previous down-boost mode of operation and reduces the cost of the controller 25. As shown in Figure 3, the portion of the loop between time T0 and T1 will respond to the value of the output voltage. The portion of the loop between times T1 and T2 is fixed, and the portion of the loop between times T2 and T3 is the remainder of the period of the PWM control section 53.

As can be seen from Figure 2, the low level BO and BU signals will force the BB signal on the output of gate 62 to become a high level. A high level signal from gate 62 activates one of the inputs of each of gates 72 and 83. This low level BU signal forces the output of inverter 66 to a high level to actuate an input of gate 68. The low level BU signal also activates an input of the gate 77 and forces the output of the inverter 76 to a high level to actuate an input of the gate 80. The low level BO signal activates an input of the gate 82 and an input of the gate 71. The low level BO signal also forces the output of inverter 63 to a high level to actuate an input of gate 65. When the controller 53 forces the PCS signal to a high level, the output of the gate 67 is forced to a high level, thereby forcing the outputs of the gates 68 and 70 to a high level, thereby forcing the D drive signal to a high level to cancel the transistor. 37. The high level signal from the D drive signal is received by the delay 78, which delays the high level signal before it is supplied to the input of the gate 77 and forces the output of the gate 77 to a high level. . A high level signal from gate 77 will actuate one of the inputs of gate 79. The high level signal from gate 67 also forces the output of gates 71 and 69 to a low level, thereby forcing the B drive signal to a low level and canceling transistor 36. The low level signal from the B drive signal is delayed by the delay 74 before the output of the forced inverter 75 becomes a high level signal. The high level signal from inverter 75 forces the output of gate 79 to a high level. The high level signal from gate 79 forces the outputs of gates 82 and 80 to a low level, thereby forcing the A drive signal to a low level, thereby actuating transistor 35. The low level A drive signal is delayed by the delay 61 before the output of the forced inverter 64 and the gate 65 becomes a high level signal to actuate an input of the gate 67. The high level signal from gate 79 forces the output of gate 80 to a high level, causing the C drive signal to also go high to actuate transistor 38. The high level C drive signal is first delayed by the delay 73 and then received by the gate 67, which does not produce any effect because the output of the gate 67 is already at a high level.

The transistors 35 and 38 will remain activated until the sense signal on the input 32 forces the PWM control section 53 to negate the PCS signal. The falling edge of the PCS signal is received by generator 50, which produces a fixed width output pulse of the T0 output signal. The TO signal that is positively advanced will be received by the gate 84 and the output of the gate 84 will be forced to a high level to actuate an input of the gate 85. The TE signal is still at a low level to force the output of the gate 72 to a high level. The low level PCS signal is received by an input of the gate 67, which does not produce any effect since the other inputs are already at a high level. The low level PCS signal also forces the output of gate 79 to a low level, thereby forcing the output of gate 80 and the C drive signal to a low level and canceling transistor 38. The low level C drive signal is delayed by the delay 73 prior to actuating the other input of the gate 67. The low level signal from gate 79 also forces the outputs of gates 82 and 85 to a high level, thereby forcing the A drive signal to a high level and actuating transistor 35. The A drive signal going to the high level is delayed by the delay 61 and forces the output of the inverter 64 and the gate 65 to a low level. The low level signal from gate 65 forces the output of gate 67 to a low level because the other inputs are already at a low level. The low level signal from gate 67 forces the output of gates 68 and 70 to a low level, thereby forcing the D drive signal to a low level to actuate transistor 37. The low level D drive signal is delayed by the delay 78 before the output of the forced gate 77 becomes low, which does not produce any effect because the output of the gate 79 is already at a low level. The low level signal from gate 67 also forces the output of gates 71 and 69 to a high level, thereby forcing the B drive signal to a high level to actuate transistor 36. The high level signal on output 87 is delayed by delay 74 before being received by gate 79. This low level signal does not have any effect on the gate 79 because the other inputs are already at a low level.

When the fixed time period of the TO signal expires, the generator 50 drives the TE signal to a high level and drives the TO signal to a low level. This high level TE signal also forces the outputs of gates 72 and 69 to a low level. A low level signal from gate 69 drives the B drive signal to a low level and cancels transistor 36. The low level B drive signal is delayed by the delay 74 before the output of the forced inverter 75 becomes high, which does not produce any effect. This low level TE signal forces the outputs of gates 84 and 85 to a low level, thereby forcing the A drive signal to a low level to actuate transistor 35.

When the PWM control section 53 drives the PCS signal to a high level to initiate another cycle of the controller 25, the generator 50 forces the TO and TE signals to a high level, and the driver 60 will rely on the PCS signal, BO. The signal, and the BU signal, form drive signals A through D. As can be seen from the foregoing, the retarders will ensure that the A to D drive signals do not overlap, thereby preventing transconductance from passing through the transistors 35 to 38.

As can be seen from the foregoing, the controller 25 is configured to couple the inductor 14 to receive the input voltage during the first portion of each of the down-boost modes for coupling the inductor 14 to Supplying power to the load 15 during a second portion of each cycle of the down-boost mode, and coupling the inductor 14 to receive the third portion of each cycle of the down-boost mode The voltage is input and power is supplied to the load 15.

To perform this function of controller 25, an input to detector 40 is coupled to input 26 and to a source of transistor 35. A first terminal of resistor 43 is coupled to the input of detector 40 and to an inverting input of comparator 41. A second terminal of resistor 43 is commonly coupled to an inverting input of comparator 41 and a first terminal of current source 42. A second terminal of current source 42 is coupled to a first terminal of current source 46 and to return terminal 27. A second terminal of current source 46 is coupled to a non-inverting input of comparator 45 and a first terminal of resistor 47. A second terminal of resistor 47 is coupled to a non-inverting input of comparator 41 and to output 31. An output of comparator 41 is coupled to the BU input of driver 60 and an output of comparator 45 is coupled to the BO input of driver 60. A drain of transistor 35 is commonly connected to a drain of transistor 36 and is coupled to input 28. Input 29 will be coupled to a source of transistor 37 and a drain of transistor 38. A drain of transistor 37 is connected to output 31. A source of transistor 38 is commonly coupled to a source of transistor 36 and to return terminal 27. Outputs 86, 87, 88, and 89 of driver 60 are coupled to the gate poles of individual transistors 35, 36, 38, and 37. The PCS output of control section 53 is coupled to the PCS input of driver 60 and an input of generator 50. Outputs 51 and 52 of generator 50 are coupled to individual inputs T0 and TE of driver 60. An inverting input of amplifier 55 is coupled to input 32 and a non-inverting input of amplifier 55 is coupled to receive a reference signal from reference device 56. The output of amplifier 55 is coupled to an input of control section 53. The BO input of driver 60 is commonly coupled to a first input of gate 71, an input of inverter 63, a first input of gate 62, and an input of gate 82. The BU input of driver 60 is commonly coupled to a second input of gate 62, an input of inverter 66, a first input of gate 77, and an input of inverter 76. The PCS input of driver 60 is coupled to a first input of gate 67 and a first input of gate 79. The TO input of driver 60 is coupled to a first input of gate 84. The TE input of driver 60 is coupled to a first input of gate 72. The output of gate 82 is coupled to a second input of gate 72 and a first input of gate 83. The output of inverter 63 is coupled to a first input of gate 85 and the output of gate 85 is coupled to a first input of gate 67. The output of gate 67 is coupled to a first input of gate 68 and a second input of gate 71. The output of gate 71 is coupled to a first input of gate 69, which has an output that is commonly coupled to an input of output 87 and delay 74. An output of the delay 74 is coupled to an input of an inverter 75 having an output commonly coupled to a second input of the gate 79 and coupled to a second of the gate 83 Input. The output of gate 83 is coupled to a second input of gate 84 having an output coupled to a first input of gate 85. The output of gate 85 is commonly connected to output 86 and an input of delay 61. The output of the delay 61 is coupled to an input of an inverter 64 having an output coupled to a second input of the gate 85. An output of inverter 66 is coupled to a second input of gate 68 having an output coupled to a first input of gate 70. The output of gate 72 is commonly connected to a second input of gates 69 and 70. The output of gate 70 is commonly coupled to output 89 and an input of delay 78 having an output coupled to a second input of gate 77. The output of gate 77 is coupled to a third input of gate 79. The output of gate 79 is commonly coupled to a first input of gate 80 and a second input of gate 82. The output of gate 82 is coupled to a second input of gate 85. The output of inverter 76 is coupled to a second input of gate 80, which has an output that is commonly coupled to an input of output 88 and delay 73. The output of delay 73 is coupled to a third input of gate 67.

In an alternate embodiment of system 10, a light emitting diode (LED), such as a white light emitting LED, can be utilized in place of resistor 18. For this particular embodiment, it is generally not necessary to connect a load 15 between the node 13 and the terminal 12.

4 is an enlarged plan view of a portion of a particular embodiment of a semiconductor device 110 formed on a semiconductor die 111. The controller 25 is formed over the die 111. For simplicity of illustration, the die 111 may also include other circuitry not shown in FIG. Controller 25 and device 110 are formed on die 111 by semiconductor fabrication techniques well known to those skilled in the art.

It will be apparent from the foregoing that the present invention discloses a novel apparatus and method. For each feature, a controller 25 is configured to operate a plurality of switches, such as transistors 35 through 38, in a down-boost mode of operation, wherein at least one of the plurality of switches is A substantial fixed amount of time in a cycle of the down-boost mode is actuated. This mode of operation of the controller 25 has less chopping current and, therefore, its utility is higher than the previous one. Drop-boost controller. The configuration of the controller 25 also results in lower consumption in the power switch, further improving efficiency. The configuration of controller 25 also allows for the use of a low saturation current inductor component for inductor 14, thereby facilitating the use of a smaller and less expensive inductor and reducing the cost of a system (system 10).

While the invention has been described with respect to the specific preferred embodiments thereof, those skilled in the <RTIgt; For example, the switching control section 49 explained in one application is a voltage mode controller, however, the switching control section 49 can also be used in various controllers including a voltage mode controller and hysteretic control. And current mode controller. Although the controller 25 is explained herein for driving an inductor, those skilled in the art will appreciate that a transformer can be utilized in place of the inductor 14, and as is well known in the art, one can be utilized. The optical coupler returns the network to replace resistors 18 and 19. The logic of the driver 60 is a logical embodiment of the logic to provide the functionality of the switching control section 49. Block 60 can also be implemented using other logical configurations. Additionally, portions of the down-boost mode loop may also be split in a different manner than the exemplary description of generator 50. In addition, for the sake of simplicity of explanation, the term "connected" is used throughout the text, but its meaning is the same as the word "coupled". Therefore, "connected to" should be interpreted as a direct or indirect connection.

10. . . Power supply system

11. . . Power input terminal

12. . . Power return terminal

13. . . Output node

14. . . Inductor

15. . . load

18. . . Resistor

19. . . Resistor

20. . . Sensing node

25. . . Power supply controller

26. . . Voltage input terminal

27. . . Voltage return terminal

28. . . Inductor input

29. . . Inductor input

31. . . Output

32. . . Sensing input

35. . . Power transistor

36. . . Power transistor

37. . . Power transistor

38. . . Power transistor

40. . . Pattern detection circuit or mode detector

41. . . Buck reference comparator

42. . . Buck current source

43. . . Buck resistor

45. . . Boost comparator one

46. . . Boost current source

47. . . Boost resistor

49. . . Switch control section

50. . . Pulse generator

51. . . Output

52. . . Output

53. . . PWM control section

55. . . Error amplifier

56. . . Reference generator or reference device

58. . . Internal regulator or regulator

59. . . Output

60. . . Logic/driver or logic/drive block

61. . . Delayer

62. . . NOR gate

63. . . Inverter

64. . . Inverter

65. . . AND gate

66. . . Inverter

67. . . OR gate

68. . . AND gate

69. . . AND gate

70. . . AND gate

71. . . NOR gate

72. . . NAND gate

73. . . Delayer

74. . . Delayer

75. . . Inverter

76. . . Inverter

77. . . OR gate

78. . . Delayer

79. . . AND gate

80. . . AND gate

82. . . NOR gate

83. . . NAND gate

84. . . OR gate

85. . . AND gate

86. . . Output

87. . . Output

88. . . Output

89. . . Output

110. . . Semiconductor device

111. . . Grain

1 is a schematic illustration of a specific embodiment of a down-boost power supply system having a down-boost power supply controller in accordance with the present invention; and FIG. 2 is a schematic illustration of the down-boost power supply controller of FIG. 1 in accordance with the present invention; a specific embodiment of a portion; FIG. 3 illustrates a relationship diagram of partial signals of the down-boost power supply system of FIG. 1 according to the present invention; and FIG. 4 schematically illustrates a power controller of FIG. 1 according to the present invention. An enlarged plan view of a semiconductor device.

For the sake of simplicity and clarity of explanation, the elements in the drawings are not necessarily to scale, and the same elements in the different figures represent the same elements. In addition, descriptions and details of well-known steps and components are omitted for simplicity of the description. As used herein, a current-carrying electrode means a carrier current in a device that passes through an element of the device, such as the source or drain of a MOS transistor, or the emitter or collector of a bipolar transistor, or a dipole. A cathode or anode; and a control electrode means a control current in the device through the components of the device, such as the gate of a MOS transistor, or the base of a bipolar transistor. Although such devices are herein explained as specific N-channel devices or P-channel devices, those skilled in the art will appreciate that complementary devices can also be employed in accordance with the present invention. Those skilled in the art will appreciate that the terms "during", "while", and when (when) are not used to mean an exact term that occurs immediately after a start-up action, actually There may be a small but reasonable delay between the reactions initiated by this initial action.

10. . . Power supply system

11. . . Power input terminal

12. . . Power return terminal

13. . . Output node

14. . . Inductor

15. . . load

18. . . Resistor

19. . . Resistor

20. . . Sensing node

25. . . Power supply controller

26. . . Voltage input terminal

27. . . Voltage return terminal

28. . . Inductor input

29. . . Inductor input

31. . . Output

32. . . Sensing input

35. . . Power transistor

36. . . Power transistor

37. . . Power transistor

38. . . Power transistor

40. . . Pattern detection circuit or mode detector

41. . . Buck reference comparator

42. . . Buck current source

43. . . Buck resistor

45. . . Boost comparator

46. . . Boost current source

47. . . Boost resistor

49. . . Switch control section

50. . . Pulse generator

51. . . Output

52. . . Output

53. . . PWM control section

55. . . Error amplifier

56. . . Reference generator or reference device

58. . . Internal regulator or regulator

59. . . Output

60. . . Logic/driver or logic/drive block

86. . . Output

87. . . Output

88. . . Output

89. . . Output

Claims (20)

A method of forming a down-boost power supply controller, comprising: configuring a switching control section to operate a plurality of switches to control an output voltage, wherein the switching control section is responsive to the output voltage Numerically operating the plurality of switches in a buck mode, a boost mode, or a down-boost mode; configuring the switching control section to form a cycle of the down-boost mode into three portions, wherein The switching control section is configured to operate the plurality of switches to couple an inductor to receive an input voltage but not to supply power during a first portion of the cycle in the down-boost mode The output voltage, during a second portion of the cycle in the down-boost mode, coupling the inductor to supply power to the output voltage but not receiving the input voltage, and in the down-boost mode During one of the third portions of the cycle, the inductor is coupled to receive an input voltage and supply power to the output voltage; and the switching control section is configured to form the first or second or the a first duration of at least one of the third portions, the first duration having a substantially fixed time interval, and forming another one of the first or second or third portions of the cycle One of the second durations, the second duration being formed in response to the value of the output voltage. The method of claim 1, further comprising coupling the plurality of switches to drive an inductor. The method of claim 1, wherein the switching control section is configured to be used Operating the plurality of switches includes coupling the plurality of switches in an H-bridge configuration. The method of claim 1, wherein configuring the switching control section comprises configuring the switching control section to respond to a first value of the output voltage to operate the plurality of switches in a buck mode of operation, A second value of the voltage should be output to operate the plurality of switches in the boost mode of operation and a third value of the output voltage to operate the plurality of switches in the boost mode, wherein The second value is greater than the first value and the third value, and wherein the third value is greater than the first value. The method of claim 1, wherein configuring the switching control section to operate the plurality of switches comprises configuring the switching control section to return a value of the output voltage to the first of the cycle of the down-boost mode And a plurality of switches of the plurality of switches are activated during a portion and the second portion, and the substantially fixed portion of the cycle is during the third portion of the cycle of the down-boost mode At least one of the plurality of switches is operated to operate. The method of claim 5, further comprising configuring the switching control section to form the third portion behind the first portion and before the second portion. The method of claim 1, wherein configuring the switching control section to operate the plurality of switches comprises configuring the power supply controller to form the substantially fixed portion of the cycle substantially equal to A fixed time amount of 25% of the switching period. A method of forming a down-boost power supply controller, comprising: configuring the down-boost power supply controller to couple an inductor to receive a first portion of a down-boost mode Input voltage; configuring the down-boost power supply controller to couple the inductor during a second portion of the down-boost mode to supply power to a load; and configuring the down-boost power supply control So that the inductor is coupled to receive the input voltage and supply power to the load during a third portion of the down-boost mode; and the switching control section is configured to form the first or a first duration of at least one of the second or the third portion, the first duration having a substantially fixed time interval, and forming the first or second or the first One of the other three of the three durations, the second duration being formed in response to a value of an output voltage. The method of claim 8, wherein configuring the down-boost power supply controller to couple the inductor during the first portion of the down-boost mode to receive the input voltage comprises configuring the down-boost power supply A controller is provided to receive an input voltage to an input terminal of the coupled inductor and to decouple the output of an output of the inductor. The method of claim 8, wherein the down-boost power supply controller is configured to couple the inductor during the second portion of the down-boost mode to supply power to the load including configuring the down-boost a power supply controller to facilitate one of the inductors during the second portion of the down-boost mode An input terminal decouples the input voltage and an output terminal of the inductor is coupled to the load. The method of claim 8, wherein the down-boost power supply controller is configured to couple the inductor during a third portion of the down-boost mode to receive the input voltage and supply power to the load including configuration The down-boost power supply controller is configured to allow the down-boost power supply controller to couple an input terminal of the inductor to receive the input voltage during the third portion of the down-boost mode and An output terminal of the inductor is coupled to supply power to the load. The method of claim 8, further comprising configuring the down-boost power supply controller to form one of the first portion, the second portion, or the third portion to form the drop- A fixed portion of the cycle of a cycle in boost mode. The method of claim 12, further comprising configuring the down-boost power supply controller to cause one of the first portion, the second portion, or the third portion to form a response The duration of a sense signal representative of an output voltage controlled by the down-boost power supply controller. The method of claim 12, wherein the down-boost power supply controller is configured to form the down-boost of the first portion, the second portion, or the third portion A fixed portion of the cycle of the cycle in the mode includes configuring the down-boost power supply controller to cause one of the first portion, the second portion, or the third portion to form The duration of a fixed amount of time. The method of claim 8, further comprising configuring the switched down-boost power supply controller to actuate a first switch in the first portion of the down-boost mode to couple the inductor For receiving the input voltage; for actuating a second switch in the second portion of the down-boost mode to couple the inductor for supplying power to the load; The first switch and the second switch are actuated in the third portion of the down-boost mode. The method of claim 15, wherein the down-boost power supply controller is configured to actuate a first switch in the first portion of the down-boost mode to couple the inductor Receiving the input voltage; actuating a second switch in the second portion of the down-boost mode to couple the inductor for supplying power to the load; and for Actuating the first switch and the second switch in the third portion of the boost mode includes configuring the down-boost power supply controller to be used for each cycle of the down-boost mode Actuating the first switch in a first portion to couple the inductor for receiving the input voltage; and actuating the second portion in the second portion of each cycle of the down-boost mode Switching to couple the inductor for supplying power to the load; and actuating the first switch and the second switch in the third portion of each cycle of the down-boost mode. The method of claim 8, further comprising configuring the down-boost power supply controller to respond to a value between the input voltage and a value controlled by the output voltage of the down-boost power supply controller a difference between operating in a buck mode or boost mode or the down-boost Among the modes. A down-boost mode power supply controller includes: a detector configured to respond to an output voltage controlled by the down-boost power supply controller and to be supplied to the Forming a first control signal by a first difference between input voltages of the down-boost power supply controller, and forming a second in response to the second value of the difference between the output voltage and the input voltage a control signal; a PWM control section configured to respond to a value of the output voltage to form a PWM control signal; and a switching control section configured to control the plurality of switches to regulate the output voltage, and Responding to a third difference between the output voltage and the input voltage in a fixed portion of a cycle of the PWM control signal to actuate one of the plurality of switches, wherein the third difference is greater than the first The difference is less than the second difference. The down-boost mode power supply controller of claim 18, wherein the switching control section is configured to actuate the plurality of switches in response to the first control signal to control the output voltage a first switch and a second switch of the plurality of switches, and responsive to the second control signal to actuate the second switch and switch the first switch under control of the output voltage. A down-boost mode power supply controller of claim 18, wherein the switching control section is configured to control the plurality of switches to regulate the output voltage and actuate in the fixed portion of the cycle One of the plurality of switches includes the switching control section being configured to form the fixed portion of the cycle for a fixed amount of time.