1377775 年 101f31日修正繼i ___1 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種電源供應器’特別是有關於一種 電源供應器的通信電路° 【先前技術】 電源供應器（power supply)用於向電子電路（例如電 腦、家用電器等）提供穩定電源（regulated p〇Wer source)。 電源供應器退用於保護用戶使其不會觸電。電源供應器因 此成為需要得到安全要求證明的重要單元《此外，電源供 應器將在功率轉換期間產生熱能。因此，多種產品經開發 以使用外部電源供應器或功率適配器來簡化產品設計，例 如攜f式電腦（Portable Computer )和行動電話充電器等。 $而，使用外部電源供應器的缺點在於缺乏電源供應器的 貧讯，例如輪出電壓、輸出電流和工作溫度等，這使得功 率管理和保護變得困難。 【發明内容】 本發明提供一種電源供應系統，其中可將功率轉換器 (power converter )的狀態報告給外部電子電路以用於功^ 管理和保護。 本發明的電源供應系統包含功率轉換器以通過輸出 f電源供應到電子電路。通信單元（eGmmunieati()n u 稱5到輪出，以在轉轉換祕電子電路之間形成通 5 1377775 -—…一 j年月曰修正 1 似 5,_iU-1 101-5-31 信通道（communication channel)以傳送調變後頻移鍵控 的功率轉換器的狀態資料至電子電路的控制單元。通信單 疋包括輸出資料緩衝器、振盪電路、輸出電路、輸入電路 以及濾波電路。輸出資料緩衝器回應於所述功率轉換器的 所述狀態資料而產生輸出資料。振盪電路耦接至所述輸出 資料緩衝器，並響應於所述輸出資料產生頻移鍵控信號。 輸出電路具有運算放大器以及多數個電晶體，所述電晶體 建構多數個電流鏡，所述輸入電路耦合到所述電源供應器 的所述輸出電纜，並接收所述頻移鍵控信號。輸入電路耦 合到所述電源供應器的所述輸出電纜，並接收所述頻移鍵 控信號。濾波電路，具有差分放大器及多個濾波器以對所 述頻移鍵控信號的邏輯準位進行解碼，所述濾波電路耦合 巧所述輸入電路，並響應於所述頻移鍵控信號而產生輸入 貧料。電感裝置（inductive device)進一步耦合到輸出電 纜，以在功率轉換器與通信單元之間提供阻抗。通信單元 通過輸出電纜傳輸通信資料，以便將功率轉換器的狀態報 告給電子電路。通信資料被調製為頻移鍵控 (frequency-shift-key, FSK)信號以進行傳輸。 其中可將功率轉換器（power c〇nverter)的狀態報告 給外部電子電路以用於功率管理和保護。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉較佳實施例，並配合所附圖式，作詳細說明如下。 【實施方式】 6 1377775 I 每1-如曰修正骑7i! ^發日服法通過電祕應 =子電路之間提供通信通道。因此，根據本= 例而提供的通信通道，如圖i和圖2所示 包含功率觀n η，㈣於通_ 3^應子= 2〇供應電源νΕ。電源Ve包含兩個端子私和ε•。通 凡1〇〇耗合到輸出電纜30，以在功率轉換器η *電_^ 路20之間形成通信通道。輸出電纜3〇具有四個端子歡、 :WM和WN。端子WA和WB連接到電源供應器1〇。 &子WM和WN連接到電子電路2G。電源％具有低輸出 阻抗。電感裝置15齡到電源Ve的端子㈣口 £_以 出電 30的端子WA和WB，電感裝置向功率轉換器 11和通信單元100提供阻抗。由電感裝置ls所建立的阻 抗在輸出電纜30上形成通信路徑以進行資料傳輸。 通信單元100通過輸出電纜30傳輸通信資=，以便將 功率轉換器11的狀態報告給電子電路20。通信單元1〇〇 和電感裝置15位於電源供應器10中。通信單元1〇〇經麵 合從功率轉換器11處獲得狀態資料Sn...s。。狀態資料 SN...S〇包含功率轉換器11的資料，例如輸入電壓、輸出 電壓和溫度等。 另一通信單元200和另一電感裝置25装配在電子電路 20中°電感裝置25連接到輸出電欖30的端子WM和WN 以及電子電路20的負載的兩個端子v+和。通信單元2〇〇 接收到的輸入賓料Dn…D〇將被傳遞到電子電路的控制 單元（control unit)(例如CPU)以用於功率管理和保^蒦。 7 1377775 101-5-31 通信單元100和200實現電源供應器1〇與電子電路2〇之 間的通信。 電感裝置15和25是共模扼流圈（comm〇n mode choke) ’其為電源vE提供低阻抗路徑以將功率輸送到電子 電路20。然而，共模扼流圈為共模信號(c〇mm〇n m〇de signal)知:供尚阻抗’這使通信單元1⑻和200的通信信號 與電源VE隔離。 圖3中繪示本發明另一優選實施例，其中單端電感器 (single-end inductor) 16用於在通信單元10〇與電源vEi 間提供高阻抗。此外，單端電感器26用於在通信單元2〇〇 與電子電路20的負載之間提供高阻抗。雖然電感器16和 26不能為電源vE到電子電路20提供低阻抗路徑，但電感 器16和26的成本低於圖2所示的電感裝置15和25。 圖4A繪示根據本發明實施例的通信單元1〇〇。通信單 元100包含輸出資料緩衝器300和介面電路400。 圖4B繪示根據本發明實施例的另一通信單元200的 實施例。通信單元2〇〇包含輸入資料緩衝器5〇〇和介面電 路400。通信單元2〇0的介面電路4〇〇與通信單元1〇〇的 介面電路相同。通信單元1〇〇的通信資料被調製為頻移鍵 控（frequency-shift-key, FSK)信號，頻移鍵控信號耦合到 電源供應器10的輸出電缓30。通信單元1〇〇包含振盡電 路（oscillation circuit，OSC) 150，以回應於通信單元 1〇〇 的輸出資料（DATA)而產生頻移鍵控信號。通過端子χι 和X2,輸出電路410耦合到電源供應器1〇的輸出電緵3〇, 1㈣日修轉赌 以輸出FSK信號。 運算放大器no、電阻器lu和電晶體112、114、115、 116、118和119形成通信單元1〇〇的介面電路4〇〇的輪出 電路410。振盪電路150的輪出信號v〇sc是根據通信單元 100的輸出資料（DATA)而產生的服信號。輸出信號 Vosc連接到運异放大器11〇。運算放大器11〇、電阻器^ 和電晶體112形成電壓·電流轉換器，㈣應於振逵電路 150的輸出信號Vosc而在電晶體112處產生電流信號1⑴。 電晶體114、115和116形成電流鏡，以分別在電晶體115 和116處產生電流信號Im和電流信號12。電流信號k 連接到電晶體114。因此’響應於電流信號—而產生電流 信號ι115和電流信號ι2。電流信號Ιιΐ5輕合到電晶體ii8。 電晶體118和119形成另_電流鏡’以回應於電流信號^ 而在電日ει體119處產生電流信號l。FSK信號回應於電流 信號11和12而形成。FSK信號通過端？ XI和X2而麵合 到輸出電纜30。1377775, 101f31, revised following i ___1 IX. Description of the Invention: [Technical Field] The present invention relates to a power supply device, particularly to a communication circuit for a power supply. [Prior Art] Power Supply ( Power supply) is used to supply a regulated p〇Wer source to an electronic circuit such as a computer or a household appliance. The power supply is retired to protect the user from electric shock. The power supply is therefore an important unit that requires proof of safety requirements. In addition, the power supply will generate heat during power conversion. As a result, a variety of products have been developed to simplify product design using external power supplies or power adapters, such as portable computers and mobile phone chargers. The disadvantage of using an external power supply is the lack of power supply leans, such as turn-off voltage, output current, and operating temperature, which makes power management and protection difficult. SUMMARY OF THE INVENTION The present invention provides a power supply system in which the status of a power converter can be reported to an external electronic circuit for power management and protection. The power supply system of the present invention includes a power converter to supply power to the electronic circuit through the output f. The communication unit (eGmmunieati() nu calls 5 to turn out to form a pass between the transfer and the secret electronic circuit. 5 1377775 -... a j-year 曰 correction 1 like 5, _iU-1 101-5-31 letter channel ( The communication channel) transmits the state data of the power converter of the modulated frequency shift key to the control unit of the electronic circuit. The communication unit includes an output data buffer, an oscillation circuit, an output circuit, an input circuit, and a filter circuit. Generating an output data in response to the state data of the power converter. An oscillating circuit is coupled to the output data buffer and generates a frequency shift keying signal in response to the output data. The output circuit has an operational amplifier and a plurality of transistors, the transistors constructing a plurality of current mirrors, the input circuit being coupled to the output cable of the power supply and receiving the frequency shift keying signal. An input circuit coupled to the power supply The output cable of the device and receiving the frequency shift keying signal. The filter circuit has a differential amplifier and a plurality of filters for the frequency shift keying signal The logic level is decoded, the filter circuit coupling the input circuit and generating an input lean in response to the frequency shift keying signal. An inductive device is further coupled to the output cable for power conversion The impedance is provided between the communication unit and the communication unit. The communication unit transmits the communication data through the output cable to report the status of the power converter to the electronic circuit. The communication data is modulated into a frequency-shift-key (FSK) signal. The transmission is performed. The status of the power converter can be reported to the external electronic circuit for power management and protection. To make the above features and advantages of the present invention more apparent, the following is preferred. The embodiment will be described in detail below with reference to the accompanying drawings. [Embodiment] 6 1377775 I Each rider is modified by the rider 7i! The daily service method provides a communication channel between the sub-circuits. According to this example, the communication channel provided includes power view n η as shown in Fig. i and Fig. 2, and (4) power supply νΕ in the pass_3^应子 = 2〇. The power supply Ve includes two The sub-private and ε•. 通 〇〇 〇〇 〇〇 〇〇 〇〇 〇〇 〇〇 〇〇 〇〇 〇〇 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出The terminals WA and WB are connected to the power supply 1. The sub-WM and WN are connected to the electronic circuit 2G. The power supply % has a low output impedance. The inductive device 15 is connected to the terminal of the power supply Ve (four) port to discharge 30 The terminals WA and WB, the inductive means provide impedance to the power converter 11 and the communication unit 100. The impedance established by the inductive means ls forms a communication path on the output cable 30 for data transmission. The communication unit 100 transmits the communication resource = via the output cable 30 to report the status of the power converter 11 to the electronic circuit 20. The communication unit 1 〇〇 and the inductive device 15 are located in the power supply 10. The communication unit 1 obtains the state data Sn...s from the power converter 11 via the face. . The status data SN...S〇 contains data of the power converter 11, such as input voltage, output voltage, and temperature. Another communication unit 200 and another inductive device 25 are mounted in the electronic circuit 20. The inductive device 25 is connected to the terminals WM and WN of the output terminal 30 and the two terminals v+ of the load of the electronic circuit 20. The input bins Dn...D〇 received by the communication unit 2〇〇 will be passed to the control unit (e.g., CPU) of the electronic circuit for power management and protection. 7 1377775 101-5-31 The communication units 100 and 200 implement communication between the power supply 1 and the electronic circuit 2A. Inductive devices 15 and 25 are common mode chokes that provide a low impedance path for power supply vE to deliver power to electronic circuit 20. However, the common mode choke is known as the common mode signal (c〇mm〇n m〇de signal): the supply impedance is the same, which isolates the communication signals of the communication units 1 (8) and 200 from the power supply VE. Another preferred embodiment of the present invention is illustrated in FIG. 3, in which a single-end inductor 16 is used to provide high impedance between the communication unit 10A and the power supply vEi. In addition, single-ended inductor 26 is used to provide high impedance between communication unit 2A and the load of electronic circuit 20. Although inductors 16 and 26 cannot provide a low impedance path for power supply vE to electronic circuit 20, inductors 16 and 26 are less expensive than inductive devices 15 and 25 shown in FIG. 4A illustrates a communication unit 1 in accordance with an embodiment of the present invention. Communication unit 100 includes an output data buffer 300 and an interface circuit 400. FIG. 4B illustrates an embodiment of another communication unit 200 in accordance with an embodiment of the present invention. The communication unit 2A includes an input data buffer 5A and an interface circuit 400. The interface circuit 4 of the communication unit 2〇0 is the same as the interface circuit of the communication unit 1〇〇. The communication data of the communication unit 1 is modulated into a frequency-shift-key (FSK) signal, and the frequency shift key signal is coupled to the output power of the power supply 10. The communication unit 1 includes an oscillation circuit (OSC) 150 for generating a frequency shift keying signal in response to the output data (DATA) of the communication unit 1〇〇. Through the terminals χι and X2, the output circuit 410 is coupled to the output power of the power supply 1〇, 1 (4), and the FSK signal is output. The operational amplifier no, the resistor lu, and the transistors 112, 114, 115, 116, 118, and 119 form the wheel-out circuit 410 of the interface circuit 4A of the communication unit 1A. The turn-on signal v 〇 sc of the oscillating circuit 150 is a service signal generated based on the output data (DATA) of the communication unit 100. The output signal Vosc is connected to the operational amplifier 11A. The operational amplifier 11A, the resistor ^ and the transistor 112 form a voltage/current converter, and (4) a current signal 1(1) is generated at the transistor 112 in response to the output signal Vosc of the vibrating circuit 150. The transistors 114, 115 and 116 form a current mirror to generate a current signal Im and a current signal 12 at the transistors 115 and 116, respectively. The current signal k is connected to the transistor 114. Therefore, the current signal ι115 and the current signal ι2 are generated in response to the current signal. The current signal Ιιΐ5 is lightly coupled to the transistor ii8. The transistors 118 and 119 form a further current mirror ' in response to the current signal ^ to generate a current signal 1 at the electric day ε body 119. The FSK signal is formed in response to the current signals 11 and 12. FSK signal through the end? The XI and X2 are combined to the output cable 30.
圖4A所示的輸入電路搞合到輸出電繞％的端子WA 21、=^舰信號。電容器21〇、22〇形成輸入電 ^ ϋ電路250 ·合到輸人電路，以響應於F 產生資料信號SH和Sjl。 示通過輸出魏3G的通信通道的等效電路。與 相關聯的電流信號11和12越過輸出電纜30的 k子WA和WB而產生信號vw。The input circuit shown in Fig. 4A is fitted to the terminal WA 21, =^ ship signal of the output power winding %. Capacitors 21A, 22A form an input circuit 250 that is coupled to the input circuit to generate data signals SH and Sjl in response to F. The equivalent circuit of the communication channel through the output Wei 3G is shown. The associated current signals 11 and 12 are passed over the k sub-WAs and WBs of the output cable 30 to produce a signal vw.
Vw = 2nxfxLxAI..................... ⑴ 其中/疋FSK信號的頻率；L是電感裝置的等效電感； 1377775 年月日修正4换頁 101 n 1 一 101-5-31 △I是電流信號1丨和12的差電流(difference current)。 圖6繪示振盪電路150的實施例。當輸出資料（DATA) 為低邏輯(logic-low)時，輸出信號V〇sc是低頻信號。一旦 振盪電路150接收到輸出資料（DATA )為高邏輯 (logic-high)時’輸出信號V〇sc就是南頻信號。電流源151 通過開關161對電容器170進行充電。電流源152通過開 關162對電容器170進行放電。電流源153與開關163串 聯提供。電流源153和開關163與電流源151並聯連接。 電流源154與開關164串聯連接。電流源154和開關164 與電流源152並聯連接。開關163和164由輸出資料 (DATA )控制。具有跳變點電壓（trip-point voltage ) VH 的比較器181連接到電容器170。具有跳變點電壓VL的比 較器182連接到電容器no。反及（NAND)閘183和184 形成閃鎖電路。反及閘183連接到比較器181的輸出。反 及閘184連接到比較器182的輸出。反及閘183的輸出經 連接以控制開關162。 通過反相器185，反及閘183的輸出控制開關161的 接通或斷開。因此在電容器17〇處產生振盪信號，以產生 輸出信號V〇sc。輸出信號Vosc通過開關190而連接到電 容器170。經由啟用信號ENB來啟用或禁用開關19〇。此 =，接地的開關195用於禁用輸出信號v〇sc。通過由反相 器187反相的啟用信號ΕΝβ來控制開關195。針對低頻 F〇sc_l和高頻F0SfH的輸出信號v〇sc的頻移可表達為：’ (Vh-Vl)xCi7〇---------------------------------(2) 10 年10邱-31EI修正替換页 F〇sc,h 士」151+1153__-… ⑴ (Vh - Vl)xCi70 (3) 其中A:是由充電電流與放電電流的比率來確定的常 C，^51是電流源151的電流；1153是電流源153的電流； -电谷益170的電容值；W是跳變點電壓Vh的電壓； Vl是珧變點電壓Vl的電壓。 古因此，輪出信號vosc包含三個狀態。高頻f〇sc h表示 ^輯狀態。侧FqS。』表示低邏輯狀態。輸出信號V〇sc 、禁用代表資料為空白狀態，其由啟用信號ENB控制。 圖7繪示通信單元1〇〇的輸出資料緩衝器300的實施 例。多個觸發器（flip-flop) 319、…、311和31〇串聯連 接，並儲存功率轉換器11的狀態資料SN…S〇。此外，觸 心器319...310被配置為移位寄存器（shift register)以用於 資料輸出。觸發器319的輸出連接到及（AND)閘325。 及閘325的另一輸入連接到啟用信號ENB。及閘325的輸 出產生輸出資料（DATA)。觸發器319、…、311和310 的時鐘輸入通過反相器320而連接到啟用信號ENB。因 此，輸出資料（DATA)根據啟用信號ENB的計時速率 (clocking rate)而連續輸出。 圖8緣示圖4所示的通信單元1〇〇的介面電路4⑻的 遽波電路250的實施例。差分放大器260具有負輸入INM 和正輸入INP ’其分別連接到電容器210和220。濾波器 270和濾、波器280連接到差分放大器260的輸出端。濾、波 器270經開發以提供f〇sc_h的帶通頻率（band-pass frequency) ’以產生高邏輯資料信號Sh。濾波器28〇用於 11 ⑸7775 年月 曰修正替渙$ -W-—1 101-5-31 解碼F0SC L的帶通頻率，以便產生低邏輯資料信號心。 資料信號SH和資料信號Sl進一步連接到輸^資料緩 -，500 ’以產生輸入資料dn D〇，如圖9所示。多個觸 發器35卜352、..·和359經連接以作為移位寄存器，以用 於根據連續輸入資料信號SH和SL而產生資料Dn D〇。觸 發器351的D輸入是移位寄存器的輸入。資料信號^和 Sl連接到或（OR)閘362。或閘362的輸出連接到單觸發 電路（one-shot circuit) 370，以產生脈衝信號（pulse signal) PLS。脈衝信號pls連接到觸發器351、352、…和359的 時鐘輸入。資料信號SH進一步連接到及閘360。資料信號 SL通過反相器361而連接到及閘360的另一輸入。及閘360 的輸出連接到移位寄存器的輸入。Vw = 2nxfxLxAI..................... (1) where /疋FSK signal frequency; L is the equivalent inductance of the inductive device; 1377775 101 n 1 - 101-5-31 ΔI is the difference current of the current signals 1 丨 and 12. FIG. 6 illustrates an embodiment of an oscillating circuit 150. When the output data (DATA) is logic-low, the output signal V〇sc is a low frequency signal. Once the oscillating circuit 150 receives the output data (DATA) as logic-high, the output signal V 〇 sc is the south frequency signal. Current source 151 charges capacitor 170 through switch 161. Current source 152 discharges capacitor 170 through switch 162. Current source 153 is provided in series with switch 163. The current source 153 and the switch 163 are connected in parallel with the current source 151. Current source 154 is coupled in series with switch 164. Current source 154 and switch 164 are connected in parallel with current source 152. Switches 163 and 164 are controlled by the output data (DATA). A comparator 181 having a trip-point voltage VH is connected to the capacitor 170. A comparator 182 having a trip point voltage VL is connected to the capacitor no. The (NAND) gates 183 and 184 form a flash lock circuit. The inverse gate 183 is connected to the output of the comparator 181. The AND gate 184 is coupled to the output of the comparator 182. The output of the anti-gate 183 is connected to control the switch 162. The output of the anti-gate 183 is controlled to be turned on or off by the inverter 185. Therefore, an oscillating signal is generated at the capacitor 17? to generate an output signal V?sc. The output signal Vosc is connected to the capacitor 170 through the switch 190. The switch 19 is enabled or disabled via the enable signal ENB. This =, grounded switch 195 is used to disable the output signal v〇sc. The switch 195 is controlled by an enable signal ΕΝβ inverted by the inverter 187. The frequency shift of the output signal v〇sc for the low frequency F〇sc_l and the high frequency F0SfH can be expressed as: '(Vh-Vl)xCi7〇-------------------- -------------(2) 10 years 10 Qiu-31EI correction replacement page F〇sc, h 士"151+1153__-... (1) (Vh - Vl)xCi70 (3) where A: It is determined by the ratio of the charging current to the discharging current, C is the current of the current source 151; 1153 is the current of the current source 153; - the capacitance of the electric valley 170; W is the voltage of the trip point voltage Vh Vl is the voltage of the enthalpy point voltage Vl. Therefore, the turn-out signal vosc contains three states. The high frequency f〇sc h indicates the state of the series. Side FqS. 』 indicates a low logic state. The output signal V〇sc, disabled representative data is blank, and is controlled by the enable signal ENB. Figure 7 illustrates an embodiment of an output data buffer 300 of the communication unit 1A. A plurality of flip-flops 319, ..., 311, and 31 are connected in series, and the state data SN...S of the power converter 11 is stored. In addition, the haptics 319...310 are configured as shift registers for data output. The output of flip flop 319 is coupled to AND gate 325. Another input of the AND gate 325 is connected to the enable signal ENB. The output of the AND gate 325 produces an output data (DATA). The clock inputs of the flip-flops 319, ..., 311, and 310 are connected to the enable signal ENB through the inverter 320. Therefore, the output data (DATA) is continuously output in accordance with the clocking rate of the enable signal ENB. Fig. 8 shows an embodiment of the chopper circuit 250 of the interface circuit 4 (8) of the communication unit 1A shown in Fig. 4. Differential amplifier 260 has a negative input INM and a positive input INP' which are coupled to capacitors 210 and 220, respectively. Filter 270 and filter, waver 280 are coupled to the output of differential amplifier 260. Filter 280 is developed to provide a band-pass frequency of f 〇 sc_h to generate a high logic data signal Sh. Filter 28〇 is used for 11 (5) 7775 曰 Revision 涣 $ -W--1 101-5-31 Decodes the bandpass frequency of F0SC L to produce a low logic data heart. The data signal SH and the data signal Sl are further connected to the data buffer -, 500' to generate the input data dn D, as shown in FIG. A plurality of flip-flops 35, 352, . . . , and 359 are connected as a shift register for generating data Dn D〇 based on the continuous input data signals SH and SL. The D input of flip flop 351 is the input to the shift register. The data signals ^ and Sl are connected to an OR gate 362. The output of OR gate 362 is coupled to a one-shot circuit 370 to generate a pulse signal PLS. The pulse signal pls is connected to the clock inputs of the flip-flops 351, 352, ... and 359. The data signal SH is further connected to the AND gate 360. The data signal SL is coupled to another input of the AND gate 360 via an inverter 361. The output of AND gate 360 is connected to the input of the shift register.
圖10繪示如圖9所示的單觸發電路370的實施例。單 觸發電路370的輪入信號IN連接到反相器373的輸入和 反及閘380的輸入。反相器373的輸出控制電晶體374。 電流源371經連接以對電容器375進行充電。電流源372 用於通過電晶體374而對電容器375進行放電。電容器375 進一步連接到與反及閘380的另一輸入。反及閘380的輸 出連接到反或（NOR)閘390的輸入。反及閘380的輸出 進一步用於控制電晶體384。電流源381經連接以對電容 器385進行充電。電晶體384用於對電容器385進行放電。 電容器385連接到或非反或閘390的另一輸入，以在或非 反或閘390的輸出處產生脈衝信號PLS。圖11繪示單觸發 電路(one-shot circuit)370的輸入信號IN和脈衝信號PLS 12 u//775 P另31日修正*勤I - _--Λ-.· 2波形，其中電流源371的電流和電容器375的電容量確 疋延遲時間TD。電流源381的電流和電容器385的電容量 確定脈衝信號PLS的脈衝寬度Tw。 里 —雖然本發明已以較佳實施例揭露如上，然其並非用以 限，本發明，任何所屬技術領域中具有通常知識者，在不 脫離本發明之精神和範圍内，當可作些許之更動與潤鋅， 因此本發明之保護範圍當視後附之申請專利範圍所界定者 為準。 【圖式簡單說明】 囷1示思性地繪示電腦通過電源供應器的輸出電欖而 與電源供應器對話。 、圖2疋根據本發明的具有通信通道的電路簡圖越過電 源供應器的輪出電纜的實施例。 圖3疋根據本發明的具有通信通道的電路簡圖越過電 源供應器的輪出電纜的另一實施例。 圖4A繪示根據本發明實施例的通信單元。 圖4B誇示根據本發明實施例的另一通信單元。 圖5緣示根據本發明實施例的通信通道的等效電路。 圖6疋根據本發明實施例的通信單元的振盪電路。 少圖7繪不根據本發明實施例的通信單元的輸出資料緩 衝器。 圖8疋根據本發明實施例的通信單元的渡波電路。 圖9繪示根據本發明實施例的通信單元的輸入資料緩 13 1377775 101-5-31 衝器。 圖10繪示根據本發明實施例的用於產生脈衝信號的 單觸發電路。 圖11繪示根據本發明實施例的輸入信號和脈衝信號 的波形。 【主要元件符號說明】 10 :電源供應器 11 :功率轉換器 15 :電感裝置 20 :電子電路 25 :電感裝置 30 :輸出電纜 WA ' WB ' WM ' WN :端子 V e :電源 E+、E-:端子 100 :通信單元 SN...S〇 :狀態資料 200 :通信單元 V +、V-:端子FIG. 10 illustrates an embodiment of a one shot circuit 370 as shown in FIG. The turn-in signal IN of the one-shot circuit 370 is coupled to the input of the inverter 373 and the input of the inverse gate 380. The output of inverter 373 controls transistor 374. Current source 371 is coupled to charge capacitor 375. Current source 372 is used to discharge capacitor 375 through transistor 374. Capacitor 375 is further coupled to another input of AND gate 380. The output of the inverse gate 380 is connected to the input of the inverse (NOR) gate 390. The output of the inverse gate 380 is further used to control the transistor 384. Current source 381 is coupled to charge capacitor 385. A transistor 384 is used to discharge capacitor 385. Capacitor 385 is coupled to another input of either or non-inverting gate 390 to generate a pulse signal PLS at the output of OR gate 390. 11 shows the input signal IN and the pulse signal PLS 12 u//775 P of the one-shot circuit 370, and the other 31-corrected I- _--Λ-.. 2 waveform, wherein the current source 371 The current and the capacitance of the capacitor 375 are determined by the delay time TD. The current of the current source 381 and the capacitance of the capacitor 385 determine the pulse width Tw of the pulse signal PLS. Although the present invention has been disclosed in the above preferred embodiments, the present invention is not intended to be limited thereto, and the present invention may be made by those skilled in the art without departing from the spirit and scope of the invention. The scope of protection of the present invention is defined by the scope of the appended claims. [Simple description of the diagram] 囷1 shows the computer to talk to the power supply through the output of the power supply. Figure 2 is an embodiment of a circuit diagram with a communication channel in accordance with the present invention over the power supply cable of the power supply. Figure 3 is another embodiment of a circuit diagram with a communication channel in accordance with the present invention over the power supply cable of the power supply. 4A illustrates a communication unit in accordance with an embodiment of the present invention. Figure 4B illustrates another communication unit in accordance with an embodiment of the present invention. Figure 5 illustrates an equivalent circuit of a communication channel in accordance with an embodiment of the present invention. Figure 6 is an oscillating circuit of a communication unit in accordance with an embodiment of the present invention. Figure 7 depicts an output data buffer of a communication unit not according to an embodiment of the present invention. Figure 8 is a diagram showing a wave circuit of a communication unit in accordance with an embodiment of the present invention. FIG. 9 illustrates an input data buffer 13 1377775 101-5-31 of a communication unit in accordance with an embodiment of the present invention. Figure 10 illustrates a one shot circuit for generating a pulse signal in accordance with an embodiment of the present invention. Figure 11 is a diagram showing waveforms of an input signal and a pulse signal in accordance with an embodiment of the present invention. [Description of main component symbols] 10: Power supply 11: Power converter 15: Inductor 20: Electronic circuit 25: Inductor 30: Output cable WA 'WB ' WM ' WN : Terminal V e : Power supply E+, E-: Terminal 100: Communication unit SN...S〇: Status data 200: Communication unit V+, V-: terminal
Dn ... D〇 :輸入貨料 16、26 :單端電感器 300 :輸出資料緩衝器 400 :介面電路 1377775 -* 日修正替染了!：| 500 :輸入資料緩衝器 150 :振盪電路 XI、X2 :端子 110 :運算放大器 111 :電阻器 112、114、115、116、118、119 :電晶體 410 :輸出電路Dn ... D〇: Input material 16, 26: Single-ended inductor 300: Output data buffer 400: Interface circuit 1377775 -* Day correction is replaced!:| 500 : Input data buffer 150: Oscillation circuit XI , X2 : terminal 110 : operational amplifier 111 : resistors 112 , 114 , 115 , 116 , 118 , 119 : transistor 410 : output circuit
Vosc :輸出信號 II、I2、Iii2、Ill5 ·電流信號 250 :濾波電路 SH、SL :資料信號 151、152、153、154 :電流源 161、162、163、164 ··開關 170 :電容器 181、182 :比較器 183、184 :反及（NAND)閘 185、187 :反相器 ENB :啟用信號 190、195 :開關 vH、VL :跳變點電壓 319〜310 :觸發器 320 :反相器 325 :及閘 210、220 :電容器 15 1377775Vosc: output signal II, I2, Iii2, Ill5 · current signal 250: filter circuit SH, SL: data signal 151, 152, 153, 154: current source 161, 162, 163, 164 · · switch 170: capacitor 181, 182 : Comparator 183, 184: NAND gate 185, 187: Inverter ENB: Enable signal 190, 195: Switch vH, VL: Trip point voltage 319~310: Trigger 320: Inverter 325: Gates 210, 220: capacitor 15 1377775
101-5-31 260 :差分放大器 INM :負輸入 INP :正輸入 270、280 :濾波器 SH :高邏輯資料信號 Sil :低邏輯資料信號 351〜359 :觸發器 360 :及閘 361 :反相器 362 :或閘 PLS :脈衝信號 370 :單觸發電路 371、372 :電流源 373 :反相器 374、 384 :電晶體 375、 385 :電容器 380 :反及閘 390 :反或（NOR)閘 TD :延遲時間 Tw :脈衝寬度 IN :輸入信號 16101-5-31 260: Differential amplifier INM: Negative input INP: Positive input 270, 280: Filter SH: High logic data signal Sil: Low logic data signal 351~359: Trigger 360: AND gate 361: Inverter 362: or gate PLS: pulse signal 370: one-shot circuit 371, 372: current source 373: inverter 374, 384: transistor 375, 385: capacitor 380: reverse gate 390: reverse or (NOR) gate TD: Delay time Tw: pulse width IN: input signal 16