TWI317872B - Watch dog circuit - Google Patents

Description

1317872 IX. Description of the invention: • Technical field to which the invention pertains The present invention relates to a control circuit, and more particularly to a computer system state ‘monitoring (WATCHDOG) circuit. [Prior Art], computer system status monitoring (WATCH DOG) is also known as watchdog or dongle, there are two kinds of circuits and software, its main function is to monitor, when a certain piece occurs, the work is performed, the computer The system watchdog can generate a restart signal to the system when the system freezes. First, the user can set a watchdog restart time, for example, 15 seconds. The user must brush #new secondary watchdog (implemented by the resident program) every 15 seconds. If the system crashes, the resident program cannot refresh the watchdog. A restart signal is generated and the system is restarted. System Management Bus (SMBUS) was released by INTEL in 1995. It is based on PHILIPS' I2C (/Inter-IC) bus and is designed to "different systems composing wafers and other parts of the system." Inter-communication, '. There are only two signal lines SMBCLK and SMBDATA on the SMBUS, mainly for the communication between the slower devices and the power management device on the system, so that the system can obtain the manufacturers of these φ devices, Model, some control information, error message and status, different devices are connected to the same SMBUS. When the computer system is running, SMBUS will output data signals through the two signal lines and SMBDATA. When the system freezes, the signal will stop. Out, at this time, a computer system state monitoring circuit is required to respond to this 'generating a restart signal to restore the system to work. [Invention content] In the above content, it is necessary to provide a computer system state monitoring circuit. Computer system status monitoring circuit, including: 6 P17872 conversion chip 'can be connected with a system management bus, to # ^System management bus output _ data 3 CCB string / and conversion, 苴中, 告命命HW<Multiple and will be 5 haibeike 唬 唬 停止 输出 该 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 Management connection (4) drag and drop ϋ conversion chip and - south bridge wafer connection, when the refresh can be stopped, the counter counts the received data line 'and outputs the set number into the second clock generation circuit when the counting is completed, and the counter circuit - Providing a working clock for the circuit; connecting to the data conversion chip and the counter for the first-power source respectively; - the first power source is connected to the clock generation circuit. The computer system state monitoring circuit can be monitored SMmTC material signal, the new startup signal of the SMBUS stop wheel output during the crash, so that the system restarts after the recovery period is generated - heavy [implementation] Referring to the figure - is a circuit block diagram of the computer system type 2 of the present invention, The computer system state monitoring electric good 2 exchange wafer 10, a counter 12, a clock transmission includes a power supply 16 and a second power supply is. The data, a management bus 100 is connected, Take the system slice 10 and a system ^ data signal 'and the data signal is serial/parallel=i00 rounded out the number 12. The count n 12 is 1 2, and the round to the conversion chip 1〇 The received data is used as a preset metric; the data is supplied from the clock generation circuit 14. The 转换$' is connected to the counter 12 and the counter 12 is connected to the data generating circuit 14. The first power source 16 is a 5V power supply, and the second power source 18 is a circuit diagram of the computer system state monitoring circuit of the present invention. 3.3V power supply. The data conversion chip 10 is a PCF8574 chip, which includes two input pins SCL and SDA, a power pin VCC, a ground pin GND, three state pins A0~A2, and four output pins P0~P3. And a control pin P4, wherein the input pins SCL and SDA are respectively connected to the corresponding signal lines SMBCLK and SMBDATA of the system management bus 100 to obtain a data signal, and the power pin VCC is connected to the first power source 16, The ground pin GND is grounded, and the state pins A0 and A1 are grounded, and the state pin A2 is connected to the first power source 16. # The counter 12 is a subtraction counter, which includes four input pins D0 to D3, an output pin Q3, a state control pin PE, a power pin VCC, a ground pin GND, and a clock input pin. The CP and three input control pins CEP, CET and MR, and the input pins D0-D3 are respectively connected to the output pins P0-P3 of the data conversion chip 10, and the power pin VCC is connected to the first power source 16. The grounding pin GND is grounded, and the input control pins CEP, CET, and MR are respectively connected to the first power source 16, and the state control pin PE is connected to the control pin P4 of the data conversion chip 10 to obtain a The work indicator signal, the output pin _ Q3 is connected to the south bridge chip to transmit a restart signal RESET_SIGNAL. The clock generation circuit 14 includes a Schmitt trigger 20, a capacitor 32, and two resistors 28 and 30. The Schmitt trigger 20 includes an input pin 21, an output pin 22, a power pin 24, and a ground pin 26, and the input pin 21 sequentially passes through the resistors 28 and 30 and the output pin. 22, the input pin 21 is further connected to the ground pin 26 through the capacitor 32. The power pin 24 is connected to the second power source 18, the ground pin 26 is grounded, and the output pin 22 and the counter 12 are connected. The clock input pin CP is connected. 8 1317872, the clock period generated by the clock generating circuit 14 is affected by the capacitance values of the resistors 28 and 3〇绉t valley 32, the voltage value of the second power source 18, and the Schmidt view, etc., in this real financial formula. At this time, the capacitance C of the capacitor circuit 14 has a capacitance C of 1 G uF, and the resistors 28 and 9 „ R1 and R2 are both 52.2 Ω, VtW is the input threshold voltage at which the Schmitt trigger becomes high, and vthh is Schmidt. Trigger 2 〇 Η Η ' ' ' ' ' ' i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i [(VCC"Vthl)*Vthh]/[(Vcc-Vthh)/Vthl]}; p± 1+R2 'V<X is 3.3V, so the clock generation period T generated by the clock generation circuit 14 is about 900 ms. The maximum count time of the counter 12 is about the input pin D0~D3 of the new counter 12 to stop the brush 12 from reducing the preset number to zero in the case of '^海ψδ十数益12, then the The number of turns ro 12 in the shai output pin Q3 production Cong T_SIGNAL to the South Bridge chip, so that the system re-start (four) " Shishu computer system state monitoring circuit 1 began to work, then began the control system management Flow 1 〇〇 wheel out ^ ° 季统理理 m Wmrwi 枓讯#u, when the system crashes two: 'The computer system-shaped South Bridge ^ piece, so that the system restarts to restore the business coffee - mail hidden to the above The invention conforms to the invention patent: please.•, the above is only the preferred and simplified of the present invention, and should be covered in the following == for the series [simplified description] The first picture is the invention « System state monitoring circuit New Zealand implementation mode 9 1317872 road block diagram. The second figure is a circuit diagram of a preferred embodiment of the computer system state monitoring circuit of the present invention.

[Main component symbol description] Computer system status monitoring circuit 1 System management bus 100 Data conversion chip 10 Counter 12 Clock generation circuit 14 First power supply 16 Second power supply 18 Schmitt trigger 20 Input pin 21 Output pin 22 Power Pin 24 Ground Pin 26 Resistor 28 > 30 Capacitor 32

Claims (1)

{Preparation year {Month day revision 1137872 X. Patent application scope: • Brain system status monitoring circuit, including: • Chip 'can be connected with system management bus to obtain zhijin: data signal' and Information Management System St. 2: 'When the computer system crashes, the system is connected to the data channel; :BeibΪ exchanges the output data of the chip 'When the counter receives the capital == counts, and outputs when the count is completed - restarts the signal generation circuit' to connect with the counter, provides one and two power supplies for the counter, respectively Connected to the data conversion chip and counter; and brother. A power supply is coupled to the clock generation circuit. The computer system state monitoring circuit described in the above, the remote control circuit comprises two input pins, a control pin and an output pin, the counter includes a plurality of input pins and an output lead pin system. The pin, the clock input pin and the complex input control, and the two input pins of the negative conversion chip are connected to the system management switch, and the output pins of the data conversion chip are respectively connected to the input pin The pin is connected to the output pin of the counter and the south bridge, and the input control pin of the counter is connected to the first power source, 曰, the clock input pin of the counter and the clock. A circuit connection, a state control pin of the gas = device, and a control circuit of the data conversion chip. 3. The computer system state monitoring circuit according to claim 2, wherein the data conversion crystal moon further includes a a power pin and a ground pin, the counter further includes a power pin and a ground pin, and the data 11 1317872 conversion chip power pin and the counter power pin are connected to the first power source, the data turn The ground pin of the wafer changer and the ground pin are grounded. 4. The computer system state monitoring circuit according to the application-patent scope item 2, wherein the bedding conversion chip further comprises three status pins, wherein one of the pins is connected to the first power source, The other two status pins are grounded. 5. The computer system status monitoring circuit according to claim 2, wherein the data conversion chip is a PCF8574 chip. 6. If the computer system status monitoring circuit described in item 2 of the application scope is 'the number of ^, the - subtraction counter, when the counter reduces the preset number to zero, the output pin output of the counter The restart signal. 7. The computer system state monitoring circuit according to claim 1, wherein the clock generating circuit comprises a Schmitt trigger, a capacitor and two electric/electrical, and the Schmitt trigger comprises a An input pin and an output lead-to-center Schmitt trigger input pin are sequentially connected to the output pin through the two resistors, and the Schmitt trigger input pin is also grounded through the ^ capacitor, the Schmidt The output pin of the flip-flop is connected to the counter. ° ° 疋 8. = The computer system status monitoring circuit described in claim 7 of the patent scope, wherein the Schmitt trigger further includes a power pin and a ground lead power pin connected to the second power source. This ground pin is grounded. Potentiometer: The computer system state monitoring circuit according to item 7 of the patent scope, wherein the Schmitt trigger of the clock generating circuit is a 141 〇 6 && uF resistance of both resistors 52.2 Ω, the capacitance value of the capacitor I 1 〇, t the computer system state monitoring power according to the first item of the patent scope, wherein the first power source is a -5V power source, and the second power source is a power source. · 12 1317872 VII. Designated representative map: (1) The representative representative of the case is: (1). (2) Simple description of the component symbols of this representative diagram: Computer system status monitoring circuit 1 System management busbar 100 tribute conversion chip 10 Counter 12 Clock generation circuit 14 First power supply 16 Second power supply 18 VIII. When revealing the chemical formula that best shows the characteristics of the invention: 5