TW202135446A - High voltage gain converter comprising three switches, two inductors, four diodes, and three capacitors - Google Patents

Abstract

A high voltage gain converter comprises three switches, two inductors, four diodes, and three capacitors. The third switch is connected in series with a diode to form a one-way current switch. The first inductor and the second inductor are two inductors with the same inductance. The first capacitor and the second capacitor are voltage-lift capacitors to increase the voltage gain. The first and second diodes and the output diodes are used as the voltage difference and current adjustment between the blocking elements. Due to the introduction of dual conduction ratio control technology, the design freedom of voltage gain is increased. Therefore, the converter does not need to operate at an extremely large conduction ratio to achieve high voltage gain.

Description

High voltage gain converter

The present invention relates to a boost converter, in particular to a high voltage gain converter for connecting renewable energy and high-voltage busbars in a renewable energy power system.

，參數V_O 、V_in 、D分別為輸出電壓、輸入電壓、開關的責任導通比，但是實務上受到寄生元件的影響，當導通比超過0.9以上時而使電壓增益不增反減，不符高電壓增益的需求，因此，無需極高導通比且同時為符合高電壓增益的需求的高電壓增益轉換器是未來的研究方向。Refer to Figure 1, a conventional boost converter. The conventional boost converter operates at a very high conduction ratio to achieve a higher voltage gain.

, The parameters V _O , V _in , D are the output voltage, input voltage, and the responsible conduction ratio of the switch, but they are affected by parasitic elements in practice. When the conduction ratio exceeds 0.9, the voltage gain will not increase but decrease, which is not high. The demand for voltage gain, therefore, a high voltage gain converter that does not require a very high conduction ratio and at the same time meets the demand for high voltage gain is a future research direction.

Therefore, the object of the present invention is to provide a high voltage gain converter.

Therefore, the high voltage gain converter of the present invention includes a first inductor, a first switch, a second switch, a second inductor, a first diode, a second diode, a first capacitor, and a second inductor. The third diode, a third switch, a second capacitor, and an output stage.

The first inductor has a first terminal and a second terminal for receiving a DC voltage. The first switch has a first terminal electrically connected to the second terminal of the first inductor and a grounded second terminal, and is controlled to switch between conduction and non-conduction. The second switch has a first terminal and a second terminal electrically connected to the first terminal of the first inductor, and is controlled to switch between conduction and non-conduction. The second inductor has a first end electrically connected to the second end of the second switch and a second end electrically connected to the second end of the first switch. The first diode has an anode electrically connected to the first end of the first inductor and a cathode. The second diode has a cathode electrically connected to the second end of the first switch, and an anode. The first capacitor has a first end electrically connected to the cathode of the first diode and a second end electrically connected to the second end of the first inductor. The third diode has an anode electrically connected to the second end of the first inductor, and a cathode. The third switch has a first end electrically connected to the cathode of the third diode, and a second end electrically connected to the second end of the second switch, and is controlled to switch between conduction and non-conduction. The second capacitor is electrically connected between the second terminal of the second switch and the anode of the second diode. The output stage is electrically connected to the first end of the first capacitor and the second end of the second capacitor to provide an output voltage proportional to the sum of the cross voltage of the first capacitor and the cross voltage of the second capacitor.

The effect of the present invention is that because the dual conduction ratio control technology is introduced, the design freedom of voltage gain is increased, so that high voltage gain is achieved without the converter having to operate at a great conduction ratio.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same numbers.

Referring to FIG. 2, an embodiment of the high voltage gain converter of the present invention includes a first inductor L ₁ , a first switch S ₁ , a second switch S ₂ , a second inductor L ₂ , and a first diode D ₁ , a second diode D ₂ , a first capacitor C ₁ , a third diode D ₃ , a third switch S ₃ , a second capacitor C ₂ , an output stage 2 and a control unit 3.

The first inductor L ₁ having a first end and a receiving end of a second DC voltage Vi.

The first switch S ₁ has a first terminal electrically connected to the _{second terminal of the first inductor L 1} and a grounded second terminal, and is controlled to switch between conducting and non-conducting; the first switch S ₁ is a N type power semiconductor transistor, and a first terminal of the first switch S ₁ is the drain, the second terminal of the first switch S ₁ is the source.

Having a second switch S ₂ is electrically connected to a first end of the first inductor L _1, a first end and a second end, and controlled to switch between conducting and nonconducting; a second switch S ₂ is N-type power the semiconductor transistor, and a first end of the second switch S ₂ is a drain, the second terminal of the second switch S ₂ is the source.

The second inductor L ₂ has a first end electrically connected to the second end of the second switch S _{2 and} a second end electrically connected to the second end of _{the first switch S 1.}

The first diode D ₁ has an anode electrically connected to a first end of the first inductance of L _1, and a cathode.

The second diode D ₂ has a cathode electrically connected to the _{second end of the first switch S 1} and an anode.

The first capacitor C ₁ is electrically connected with a cathode of the first diode D _1, the first inductor is electrically connected to a first terminal and a second terminal of a second L _1.

The third diode D ₃ having an anode electrically connected to a second terminal of the first inductance of L _1, and a cathode.

A first end, and an electrical switch S ₃ having a third electrically connected to the cathode of the third diode D ₃ is connected to the second end of the second end of the second switch S _2, and controlled to switch ON and not Conduction room. The third switch S ₃ is an N-type power semiconductor transistor, the first and the third switch S ₃ is a drain terminal, a second terminal of the third switch S ₃ is the source.

The second capacitor C _{2 is} electrically connected between the second _{end of the second switch S 2} and the anode of the second diode D _2.

The output stage 2 is electrically connected to the first _{end of the first capacitor C 1} and the second end of the second capacitor C ₂ to provide a voltage proportional to the _{cross voltage of the first capacitor C 1} and the second capacitor C ₂ The total output voltage of the cross-voltage. The output stage 2 includes an output diode D _O and an output capacitor C _O. The output diode D _O has an anode electrically connected to the _{first end of the first capacitor C 1} and a cathode. The output capacitor C _{O is} electrically connected between the _{cathode of the output diode D O} and the second end of the second capacitor C _2.

The control unit 3 generates a first switching of the first switch S ₁ pulse modulation signal, the third switch of the second switch S a second pulse modulation signal ₂ and a switching of the third switch S ₃ A pulse wave modulated signal. The first pulse wave modulated signal and the second pulse wave modulated signal have the same cycle time.

Refer to FIGS. 3 and 4, respectively, the operation timing diagrams of the continuous conduction mode (Continuous Conduction Mode, CCM) and the discontinuous conduction mode (DCM) of this embodiment, where the parameters v _gs1 , v _gs2 , and v _gs3 Respectively represent the voltage of the pulse signal that controls whether the first to third switches S ₁ , S ₂ , S ₃ are turned on, and the parameters v _L1 and v _L2 represent the two ends of the first and second inductors L ₁ , L _{2 respectively} Across voltage, the parameters i _L1 and i _L2 represent the currents of the first and second inductors L ₁ and L ₂ respectively, and the parameters v _D1 , v _D2 , and v _DO represent the first diode D ₁ and the second diode respectively Body D ₂ , output diode D _O across the two ends, the parameters i _D1 , i _D2 , i _DO , i _C1 , i _C2 , i _CO represent the first diode D ₁ , the second diode respectively D _2, the output diode D _O, the first capacitor C _1, the second capacitor C _2, the current of the output capacitor C _O, T _S parameter is the cycle time of the first pulse signal.

The following is a circuit diagram of each of the three stages of CCM operation in this embodiment, in which the conductive elements are represented by solid lines, and the non-conductive elements are represented by dashed lines. The following describes each phase separately.

The first stage (time: t ₀ ~t ₁ ):

3 and 5, the first switch S ₁ and the second switch S ₂ are turned from non-conducting to conducting, and the third switch S _{3 is} non-conducting, the first diode D _{1 is} conducting, and the second diode D ₂ Conduction, the third diode D _{3 is} not conductive, and the output diode D _{O is} not conductive.

The first inductor L ₁ and the second inductor L ₂ and the voltage across the equivalent parallel are input voltage V _i, the inductance current increases linearly, because the two are identical inductance L, the slope are thus V _i / L, a first input voltage V _i via the diode D ₁ and the second diode D ₂ of the first capacitor C ₁ and the second capacitor C ₂ is charged at this stage in

When t=t1, the first switch S ₁ and the second switch S _{2 are} switched to be non-conducting, and the third switch S _{3 is} switched to be conducting, this stage ends.

The second stage (time: t ₀ ~t ₁ ):

Referring to FIGS. 3 and 6, the first switch S ₁ and the second switch S ₂ are turned from conducting to non-conducting, and the third switch S _{3 is} conducting, the first diode D _{1 is} not conducting, and the second diode D ₂ nonconductive, the third diode D ₃ is turned on, the output diode DO nonconductive.

S ₃ and the third diode D ₃ is formed via a third switch circuit, a first input voltage V _i to the equivalent series inductance of the second inductor L ₁ and L ₂ charging, while the first inductor L ₁ and the second inductor The voltage across L _{2 is V i} /2, the inductor current continues to rise, and the slope is V _i /2L. In this stage, the inductor current can be expressed as

When t=t ₂ and the third switch S _{3 is} switched to non-conducting, this stage ends.

The third stage (time: t ₂ ):

Referring to Figures 3 and 7, the first switch S _{1 is} not conductive, the second switch S _{2 is} not conductive, and the third switch S _{3 is} switched to be non-conductive, the first diode D _{1 is} not conductive, and the second diode D _{2 is} not conducting, the third diode D _{3 is} not conducting, and the output diode D _{O is} conducting.

，其電流呈線性下降，在本階段中電感電流可表示為This stage of the input voltage source V _i, connected to the first and second inductor L ₁ and L _2, the first capacitor C _1, the second capacitor C ₂ in series through the output diode D _O, and the output load capacitance C _O R Transfer energy. The voltage across the first inductor L ₁ and the second inductor L _{2 is}

, Its current decreases linearly, and the inductor current in this stage can be expressed as

When t=t ₃ , the first switch S ₁ and the second switch S _{2 are} switched to conduction, and the third switch S ₃ remains non-conducting. This stage ends and the next switching cycle is entered.

The following is a circuit diagram of each of the four stages of operation in the DCM of this embodiment, in which the conductive elements are represented by solid lines, and the non-conductive elements are represented by dashed lines. The following describes each phase separately.

The first stage (time: t ₀ ~t ₁ ):

。定義t=t1時的第一電感電流值，Referring to Figures 4 and 5, the operating principle of this stage is the same as the first stage of CCM operation. At this stage, the maximum current of the _{first inductor L 1} and the second inductor L _{2 is}

. Define the first inductor current value when t=t1,

When t=t1, the first switch S ₁ and the second switch S _{2 are} switched to non-conducting, and the third switch S _{3 is} switched to conducting at the same time, and this stage ends.

The second stage (time: t ₁ ~t ₂ ):

。當t=t₂ ，第三開關S₃ 切換為不導通，本階段結束。Referring to Figures 4 and 6, the operating principle of this stage is the same as the second stage of CCM operation. The first switch S ₁ and the second switch S ₂ are non-conductive, and the third switch S ₃ is conductive. The input voltage V _i transfers energy to the first inductor L ₁ and the second inductor L ₂ , and the output capacitor C _O supplies load current. The maximum current of the first inductor L ₁ and the second inductor L _{2 is}

. When t=t ₂ , the third switch S _{3 is} switched to be non-conducting, and this stage ends.

The third stage (time: t ₂ ~t ₃ ):

Referring to FIG. 4 and FIG. 7, the operation principle of this stage is the same as that of the third stage of CCM operation, and the first to third switches S ₁ to S ₃ are not turned on. The output diode D _{O is} turned on. The input voltage Vi, the first inductor L ₁ and the second inductor L ₂ , the first capacitor C ₁ and the second capacitor C _{2 are} equivalently connected in series to charge _{the output capacitor C O.} The currents of the first inductor L ₁ and the second inductor L ₂ decrease linearly, and the voltage across the _{first to third switches S 1} to S _{3 is}

When t=t3, when _{the currents of the first inductor L 1} and the second inductor L ₂ drop to 0, the output diode D _O naturally turns into non-conducting state, and this stage ends.

The fourth stage (time: t ₃ ~t ₄ ):

。輸出電容C_O 放電至負載，負載電流

。當t=t₄ ，第一開關S₁ 和第二開關S₂ 切換為導通，本階段結束，新的一個切換週期開始。Referring to Figure 4 and Figure 8, all switches and diodes are non-conducting at this stage, and the currents of the _{first inductor L 1} and the second inductor L ₂

. The output capacitor C _{O is} discharged to the load, the load current

. When t=t ₄ , the first switch S ₁ and the second switch S _{2 are} switched on, this stage ends, and a new switching cycle starts.

> CCM mode voltage gain analysis>

Apply the volt-second balance principle to the first inductance L ₁ and the second inductance L _{2, so that:}

Substituting the inductor voltage in the operating mode into the available

In the case of CCM mode, the voltage gain M _CCM is

It can be seen from the above formula that the voltage gain has two design degrees of freedom for the _{conduction ratio d 1} and d _2. When operating in the CCM mode, the voltage gain corresponding to the conduction ratios d ₁ and d _{2 of the first switch S 1} and the second switch S _{2 is shown} in Fig. 9 and Fig. 10.

> DCM mode voltage gain analysis>

When the converter is operating in discontinuous conduction mode (DCM), since the inductance still satisfies the volt-second balance theorem, it can be obtained

Organize available

(1)

(1)

In the steady state, the current waveform i _{CO of the output capacitor C O} , the average current can be expressed as

(2)

(2)

與輸出電流I_O 可分別計算如下(17) The maximum inductor current in the formula

And the output current I _O can be calculated separately as follows

(3)

(3)

(4)

(4)

Substituting formula (1)(3)(4) into formula (2), we can get

(5)

(5)

，因此(5)式可化簡為In steady state, the output capacitor C _O satisfies the amp-second balance principle, namely

, Therefore (5) can be simplified to

(6)

(6)

，將規一化電感時間常數

代入(6)式，整理可得DCM模式的電壓增益為Define the normalized inductor time constant:

, To normalize the inductance time constant

Substituting into equation (6), we can get the voltage gain of DCM mode as

(7)

(7)

及導通比d₁ 和d₂ 的函數。若以L=74.2μH，T_S =20μs，R=1600Ω為例，經由計算

，則電壓增益與導通比d₁ 和d₂ 的關係曲線如圖11、12，其中圖11是當d₁ 在不同的定值時，電壓增益與導通比d₂ 的關係曲線；另一方面，圖12是當導通比d₂ 在不同的定值時，電壓增益和導通比d₁ 的關係曲線。It can be seen from the above formula that when operating in DCM mode, the voltage gain is the normalized inductor time constant

And the conduction ratio as a function of _{d 1} and d _2. If L=74.2μH, T _S =20μs, R=1600Ω as an example, through calculation

, The voltage gain and the conduction ratio d ₁ and d ₂ are shown in Fig. 11 and 12, where Fig. 11 is the relation curve of the voltage gain and the conduction ratio d _{2 when d 1 is} at different fixed values; on the other hand, Fig. 12 is the relationship curve between the voltage gain and the conduction ratio d ₁ when the conduction ratio d _{2 is at different fixed values.}

>BCM operation mode analysis>

When the converter is operating in Boundary Conduction Mode (BCM), we can get that the voltage gain of CCM mode is equal to the voltage gain of DCM mode, namely

M _CCM =M _DCM (8)

，則由上述公式的結果可推導得到Let the boundary normalization inductance time constant be

, Then can be derived from the result of the above formula

(9)

(9)

，則操作在CCM；若

，則操作在DCM。Therefore, if

, The operation is in CCM; if

, The operation is in DCM.

>Switching voltage stress analysis>

、

。According to the analysis of the operation principle of the converter, the first to third switches S ₁ to S ₃ and the cross voltages of each diode D ₁ , D ₂ , and D _{O in different operation stages can be obtained. The first to third switches can be sorted out.} The electrical stresses of S ₁ ~S _{3 are}

,

.

、

、

。The voltage stresses of the multiple diodes D ₁ , D ₂ , D ₃ , and D _{O are respectively}

,

,

.

The voltage stress of the power switch and the diode which is different from the traditional boost converter is the output voltage, and the voltage stress of all the switches and diodes of this embodiment is less than the output voltage. In high output voltage applications, MOSFETs with low rated withstand voltage and lower R _DS(ON) can be used to reduce switch conduction losses. In addition, a diode with lower voltage stress can be a Schottky diode or a diode with a relatively low conduction voltage drop, which can reduce the conduction loss and improve the conversion efficiency of the converter.

The above embodiment has the following advantages:

1. Due to the introduction of dual conduction ratio control technology, the design freedom of voltage gain is increased, so high voltage gain is achieved without the converter having to operate at a great conduction ratio.

2. Since the voltage stress of the first to third switches S ₁ to S ₃ is much lower than the output voltage, a low-rated piezoelectric crystal with a smaller on-resistance can be used to reduce the conduction loss.

3. Since the voltage stress of the first and second diodes D ₁ and D ₂ is much lower than the output voltage, a diode with a smaller turn-on voltage drop can be used to reduce the turn-on loss. In summary, it can indeed achieve the purpose of the invention.

However, the above are only examples of the present invention. When the scope of implementation of the present invention cannot be limited by this, all simple equivalent changes and modifications made in accordance with the scope of the patent application of the present invention and the content of the patent specification still belong to This invention patent covers the scope.

L ₁ : first inductance S ₁ : first switch S ₂ : second switch L ₂ : second inductance D ₁ : first diode D ₂ : second diode C ₁ : first capacitor D ₃ : first Triode S ₃ : third switch C ₂ : second capacitor 2: output stage 3: control unit Vi: DC voltage C _O : output capacitor _DO : output diode

Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, in which: Figure 1 is a circuit diagram of a conventional boost converter; 2 is a circuit diagram of an embodiment of the high voltage gain converter of the present invention; FIG. 3 is an operation timing diagram of the continuous conduction mode of this embodiment; FIG. 4 is an operation timing diagram of the discontinuous conduction mode of this embodiment; Figure 5 is a circuit diagram of this embodiment operating in the first stage; Figure 6 is a circuit diagram of this embodiment operating in the second stage; FIG. 7 is a circuit diagram of this embodiment operating in the third stage; FIG. 8 is a circuit diagram of this embodiment operating in the fourth stage; FIG. 9 is a graph showing the relationship between different conduction ratios and voltage gains of the embodiment operating in continuous conduction mode; FIG. 10 is a graph showing the relationship between different conduction ratios and voltage gains of the embodiment operating in continuous conduction mode; FIG. 11 is a graph of the relationship between different conduction ratios and voltage gains of the embodiment operating in the discontinuous conduction mode; and FIG. 12 is a graph showing the relationship between different conduction ratios and voltage gains when the embodiment operates in a discontinuous conduction mode.

L ₁ : first inductance

S ₁ : The first switch

S ₂ : The second switch

L ₂ : second inductance

D ₁ : The first diode

D ₂ : The second diode

C ₁ : The first capacitor

D ₃ : The third diode

S ₃ : third switch

C ₂ : second capacitor

2: output stage

3: control unit

Claims (6)

A high voltage gain converter, including: A first inductor having a first terminal and a second terminal for receiving a DC voltage; A first switch having a first terminal electrically connected to the second terminal of the first inductor and a second terminal grounded, and controlled to switch between conduction and non-conduction; A second switch having a first terminal and a second terminal electrically connected to the first terminal of the first inductor, and is controlled to switch between conduction and non-conduction; A second inductor having a first terminal electrically connected to the second terminal of the second switch and a second terminal electrically connected to the second terminal of the first switch; A first diode having an anode electrically connected to the first end of the first inductor and a cathode; A second diode, having a cathode electrically connected to the second end of the first switch, and an anode; A first capacitor having a first end electrically connected to the cathode of the first diode and a second end electrically connected to the second end of the first inductor; A third diode, having an anode electrically connected to the second end of the first inductor, and a cathode; A third switch having a first end electrically connected to the cathode of the third diode, and a second end electrically connected to the second end of the second switch, and controlled to switch between conduction and non-conduction; A second capacitor, electrically connected between the second terminal of the second switch and the anode of the second diode; and An output stage, electrically connected to the first end of the first capacitor and the second end of the second capacitor, to provide an output proportional to the sum of the cross voltage of the first capacitor and the cross voltage of the second capacitor Voltage. The high voltage gain converter according to claim 1, wherein the output stage includes: An output diode, having an anode electrically connected to the first end of the first capacitor, and a cathode; An output capacitor is electrically connected between the cathode of the output diode and the second end of the second capacitor. The high voltage gain converter according to claim 1, wherein the first switch is an N-type power semiconductor transistor, the first terminal of the first switch is a drain, and the second terminal of the first switch is Source. The high voltage gain converter according to claim 1, wherein the second switch is an N-type power semiconductor transistor, the first terminal of the second switch is a drain, and the second terminal of the second switch is Source. The high voltage gain converter according to claim 1, wherein the third switch is an N-type power semiconductor transistor, the first terminal of the third switch is a drain, and the second terminal of the third switch is Source. The high voltage gain converter according to claim 1, further comprising a control unit that generates a first pulse wave modulation signal for switching the first switch and a second pulse wave modulation signal for switching the second switch The first pulse wave modulated signal and the second pulse wave modulated signal have the same cycle time.

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