TW201223110A

TW201223110A - Multi-phase non-inverting buck boost voltage converter

Info

Publication number: TW201223110A
Application number: TW100125420A
Authority: TW
Inventors: Xue-Lin Wu; Cong-Zhong Huang; Shea Petricek
Original assignee: Intersil Inc
Priority date: 2010-08-02
Filing date: 2011-07-19
Publication date: 2012-06-01
Also published as: KR20120012767A; CN102347689A; TW201440409A; CN102347689B; TWI454037B; TWI511436B; KR101379047B1

Abstract

A multi-phase non-inverting buck boost voltage converter has a plurality of buck boost voltage regulators. Each regulator is associated with a separate phase for generating a regulated output voltage responsive to an input voltage. A plurality of current sensors are each associated with one of the plurality of buck boost voltage regulators for monitoring an input current to the associated buck boost voltage regulator and generating a current sense signal for the associated phase. A plurality of buck boost mode control circuitries are each associated with one of the buck boost regulator for controlling an associated buck boost voltage regulator using peak current mode control in a buck mode of operation and valley current mode control in boost mode of operation responsive to a common error voltage and the associated current sense signal. The plurality of buck boost mode control circuitries provides current balancing between the phases. A voltage error circuit generates the error voltage responsive to the regulated output voltage.

Description

201223110 六、發明說明：【相關申請案之交互參照】此申請案係主張2011年6月14曰申請的名稱為多位準非反相 BB電壓轉換器的美國專利申請案號 13/160,162(代理人檔案號INTS_30,622)的益處，該美國專利申請案是2010年8月2日申請的名稱為非反相升降壓電壓轉換器的美國專利申請案號12/848,579(代理人檔案號 INTS-29,982)的一部分接續案。【發明所屬之技術領域】本發明係關於升降壓電壓轉換器，並且更具體而言係有關於一種用於控制非反相升降壓轉換器以提供在降壓及升壓操作模式間之平順的轉換的系統及方法。 L尤刖枝術】非反相升降壓轉換器係能夠根據操作模式來達成一高低於”輪入電壓的輸出電壓。由於以電池供電的裝置變得越來越普A，這些類型的轉換器正變得更有吸引力，利用電池的放電週期。當-電池輸入電壓高中：：降广Γ時，一升降壓轉換器係工作在降壓操作模式要的位進、式中’該轉換器係減小輸入電壓至-必 }以供在其輸出處的使用。一輸出電壓時，嗜井降厭M t池輸入電壓低於其中於人升降壓轉換11係卫作在升壓操作模式中， "㈣增南到一在其輸出處所需的位準。在純降 201223110201223110 VI. INSTRUCTIONS: [Reciprocal References for Related Applications] This application claims US Patent Application No. 13/160,162, entitled "Multiple Quasi-Non-Inverting BB Voltage Converters", filed June 14, 2011. U.S. Patent Application Serial No. 12/848,579, filed on Aug. 2, 2010, filed on Aug. 2, 2010 (Attorney Docket No. INTS- Part of the 29,982) continuation case. BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a buck-boost voltage converter, and more particularly to a control for a non-inverting buck-boost converter to provide smoothing between buck and boost modes of operation. Conversion system and method. L eucalyptus] Non-inverting buck-boost converters are capable of achieving an output voltage that is lower than the "in-wheel voltage" depending on the mode of operation. These types of converters It is becoming more attractive, taking advantage of the battery's discharge cycle. When the battery input voltage is high::, the buck-boost converter works in the step-down mode of the buck operation mode. The input voltage is reduced to - must be used for use at its output. When an output voltage is applied, the input voltage of the well-beating M t cell is lower than that of the human-boosting voltage conversion system in the boost operating mode. , "(4) Zengnan to a level required at its output. In pure drop 201223110

產生以及輸出漣波的產生，立輸出電壓，此係為—穩態效能的問題。由各種相關的功率開關當輪出電壓接近輸入電壓時，轉換係提供各種的控制挑戰。式間的此種轉換期間控制該，、係為一動態響應的線暫態的其中產生的輸入電壓係接近該【發明内容】如同在此所揭露及敘述的，在本發明的一觀點中，本發明係包括一種非反相升降壓轉換器。該升降壓轉換器係包含用於響應於一輸入電壓以產生一調節後的輸出電壓的升降壓電壓调節電路。一電流感測器係監測該升降壓調節電路的一輸入電流。升降壓模式控制電路係響應於該監測到的輸入電流以控制該升降壓電壓調節電路在一降壓操作模式中利用深電流模式控制，並且在一升壓操作模式中利用有效的電流模式控制。【實施方式】現在參照到圖式，其中相同的元件符號在此被用以指明全文中相似的元件，一種非反相升降壓電壓轉換器的各種視圖及實施例係被描繪及敘述，並且其它可行的實施例係被描述。該些圖並不一定按照比例繪製，並且在某些實例中，該圖式僅為了說明之目的已經在一些地方被誇大及/ 201223110 或簡化具有此項技術的通常知識者將會體認到根據以下可打的實施例的例子之許多可能的應用及變化。。非反相升降壓轉換器係能夠達成—高於或低於其輸入電壓的正輸出電壓。由於以带田於以電池供電的裝置變得越來越普及，此種拓撲正變得更有吸引力，因為其可以利用電池的放電週期。當-電池輸入電壓高於其輸出電壓時，一升降壓轉換器係工作在降壓操作模式卜在降壓操作模式中，該轉換器係減小輸入電壓至必要的位準以供在其輸出處的使用。當该電池輸入電壓低於輸出電壓時，該升降壓轉換益係工作在升麼操作模式中，其中輸入電壓係增高到一在 ^出處所需的位準。藉由讓某些功率開關被導通或關閉以了施在-純降壓操作模式或是—純升壓操作模式中的控制是相當容易的。該挑戰仍然存在於#輸出電a接近輸入電壓時的降壓及升壓操作模式間之轉換。在降壓及升壓操作模式間的此種轉換期間有兩項控制該升降壓轉換器的挑减。一項挑戰係牽涉到線暫態，其係為一動態響應。另一項挑喊係為輪出漣波，丨中產生的輸人電㈣接近該輸出電壓’此係為一穩態效能的問題。以下所敘的實施係包括一種控制非反相升降壓轉換器又汁並且提供一種達成在模式間之平順的轉換及線暫態之方法，同時在輸出電壓接近輸入電壓時仍然維持最小的連波電壓。在该設計中只有一個整合的電流感測器被利用到，而不是多個感測器，以降低複雜度並且簡化整體的設汁。該控制器係利用逐週期的偵測以在降壓操作模式中使 201223110 用峰值電流模式控制，並且在升壓操作模式中使用一谷拉制模式。此方法係在該轉換器内提供平順的轉換及線暫態。在輸出電壓接近輸入電壓的狀況中，該升降壓轉換器係藉由監測最大的工作週期，自動地從該降壓操作模，切換至料壓操作模式、或是從料壓操作模式切換至5亥降m操作模式。此係簡化該升降a轉換器的控制並且降低該輸出電壓漣波。降壓模式的操作及升塵模式的操作都使用相同的整合的電流感測器，此係降低該系統的複雜度並且增加整體的可靠度。 β非反相升降壓轉換器係能夠達成高於或低於其輸入電的輸出電壓。_多應用較喜歡非反相升降壓轉換器，例如’渴望利用電池的放電週期的以電池供電的裝置。以電池仏電的電子設備及汽車因為發生負載突降或冷車啟動的情況而遭受到較差的電池電壓。在這些情況下，非反相升降壓轉換器是-理想的候選者。若負载功率是高的，為了低成本及散熱而需要多相升降壓轉換器。現在參照圖式，並且更特別參照圖i，其描繪有一種升降壓轉換器的概要圖。該升降壓轉換器係包含—施加輸入電壓vIN的輸入電壓節點102。一高側的降壓電晶體刚係包括一使得其源極/汲極路徑連接到節點ι〇2及節點1〇6之間的P通道電晶體。一低側的降壓電晶體1〇8係包括一使得其沒極/源極路徑連接到節1G6及接地之間的N通道電晶體。-電感H U0係連接到節點1〇6及節點112之間。 -高側的P通道升壓電晶體114係使得其源極/祕路徑連 201223110 接到該輸出電壓節點ν〇υτ 116及節點112之間。一低側的升壓電sb體11 8係包括—使得其源極〇及極路徑連接到節點 112及接地之間的N通道電晶體。如同熟習此項技術者非常瞭解的’該些高側的降壓及升壓電晶體亦可藉由N通道電日日體來加以實施〇再者’所有的開關電晶體都可藉由雙載子電晶體或是任何其它適當的受控開關裝置來加以實施。該輸出電容120係連接到該輸出電壓節點116及接地之間。該輸出負載電阻122係和該電& 12〇在節點ιΐ6及接地之間並聯連接。該高側的降壓電晶體1〇4、低側的降壓電晶體刚、高側的升壓電㈣114以及低側的升壓電晶體 U8的每一個都使得其問極連接至升降壓控制電路124。咳升降壓控制電…係利用内部的控制邏輯，經由複數個輸出來產生閘極控制信號，㈣部的控制邏輯係、負責至少從節點"6施加的輸出電壓ν〇υτ。在該降壓操作模式中的工作週期係定義為D)/τ，其中^係開關電晶體刚的導通時間’並且τ是該轉換器的切換期間。τ是切換頻率 fsw的㈣（TM/fsw)。在升壓動作期間，該工作週期係義為亦即同步的高側的升壓電晶體…的導通時間除以該切換期間。現在參照圖2,其描繪有根據本揭露内容操作的一種非反相升降壓轉換器的功能方塊圖。該升降壓轉換器電路2〇2 係在輸入節點204接收輸入電壓Vin並且在節點2〇6提供輸 ^壓W。在該升降壓轉換器2G2内之開關電晶體係根據由驅動邏輯提供的驅動控制信號來加以驅動。該驅 201223110 動邏輯208係響應於由PWM控制邏輯21〇提供的pwM控制信號以產生驅動控制信號至該些開關電晶體。該誤差放大器及PWM控制邏輯21〇係響應於在節點2〇6監測到的輸出電壓並且亦響應於由電流斜率控制補償邏輯212提供的電流控制電壓VSUM以產生該些ρ·控制信號。該電流斜率控制補償邏輯係響應於該升降壓轉換器2〇2内由一電流感測器214提供之一監測到的電流以及模式控制邏輯η。以產生忒VSUM電壓至該誤差放大器及pWM控制邏輯 21〇。該電流感測器214係量測在該升降壓轉換器2〇2的輸入節點204所提供的輸入電流。該模式控制邏輯216係藉由監測由該PWM控制邏輯210提供的PWM信號來判斷該升降壓轉換器202是操作在該降壓操作模式或升壓操作模式令。該模式控制邏輯216係另外提供模式控制信號至該驅動:邏輯208以控制在該升降壓轉換器2〇2内之開關電晶體的操作。現在參照圖3 ’其描繪有本揭露内容的非反相升降壓轉換器的方塊圖。該升降壓轉換器3〇2係包含一施加輸入電壓的輸入電壓節點304。一電流感測器3〇6係感測通過節點304的輸入電壓電流並且提供一感測到的輸入電流 “ns。一高側的降壓電晶體3〇8係連接到該電流感測器3〇6 及節點3 10之間。該高側的降壓電晶體308係包括一 p通道電晶體。該高側的降壓電晶體308係連接以接收該驅動信號HD—BUCK。一低側的降壓電晶體3 12係包括一使得其没極/源極路徑連接到節點310及接地節點314之間的N通 201223110 道電晶體》該低側的降壓電晶體312係連接以接收該驅動控制#號LD_BUCK。-電感器3 16係連接到節點3 1〇及節點3 18之間。一高側的升壓電晶體32〇係包括一使得其源極/汲極路徑連接到該輸出電壓節點V0UT 322及節點3 18之間的P通道電晶體。該低側的升壓電晶體321係包括一使得其汲極/ 源極路徑連接到節點3 1 8及節點3 14之間的N通道電晶體。電晶體324的閘極係連接以接收該驅動控制信號 LD-B〇〇ST。高側的升壓電晶體320的閘極係連接以接收該驅動控制信號HD_B00ST。一輸出電容器326係連接至輸出電壓節點322且在該輸出電壓節點322及接地節點314 之間。此外’ 一負載328係和該輸出電容326在輸出電壓節點322及接地節點3 14之間並聯連接。The generation and output of chopping, the output voltage, is the problem of steady state performance. By various related power switches, the switching system provides various control challenges when the wheel-out voltage is close to the input voltage. In the case of such a transition between modes, the input voltage generated in a dynamically responsive line transient is close to the present invention. As disclosed and described herein, in one aspect of the present invention, The present invention includes a non-inverting buck-boost converter. The buck-boost converter includes a buck-boost voltage regulating circuit responsive to an input voltage to produce a regulated output voltage. A current sensor monitors an input current of the buck-boost regulating circuit. The buck-boost mode control circuit is responsive to the monitored input current to control the buck-boost voltage regulation circuit utilizing deep current mode control in a buck mode of operation and utilizing active current mode control in a boost mode of operation. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings, wherein like reference numerals are used to refer to the like elements throughout, the various views and embodiments of a non-inverted buck-boost voltage converter are depicted and described, and others Feasible embodiments are described. The figures are not necessarily drawn to scale, and in some instances, the drawings have been exaggerated in some places for purposes of illustration and / 201223110 or simplified by those of ordinary skill in the art will recognize There are many possible applications and variations of the examples of embodiments that can be played below. . A non-inverting buck-boost converter is capable of achieving a positive output voltage above or below its input voltage. This topology is becoming more attractive as it is becoming more and more popular with battery-powered devices because it can take advantage of the battery's discharge cycle. When the battery input voltage is higher than its output voltage, a buck-boost converter operates in a buck mode of operation. In the buck mode of operation, the converter reduces the input voltage to the necessary level for output. Use of the office. When the battery input voltage is lower than the output voltage, the buck-boost conversion operation operates in the boost mode of operation, wherein the input voltage is increased to a level required at the source. Control in the -pure buck mode of operation or the pure boost mode of operation is quite easy by having certain power switches turned "on" or "off". This challenge still exists in the transition between the buck and boost modes of operation when the output power a approaches the input voltage. There are two options to control the buck-boost converter during this transition between the buck and boost modes of operation. One challenge involves a line transient, which is a dynamic response. Another scream is the round-trip chopping, and the input power generated by the ( (4) is close to the output voltage'. This is a problem of steady-state performance. The implementations described below include a method of controlling the non-inverting buck-boost converter and providing a smooth transition and line transient between modes while maintaining a minimum continuous wave when the output voltage is close to the input voltage. Voltage. Only one integrated current sensor is utilized in this design, rather than multiple sensors, to reduce complexity and simplify overall sizing. The controller utilizes cycle-by-cycle detection to enable the 201223110 to be controlled in peak current mode in the buck mode of operation and a valley mode in the boost mode of operation. This method provides smooth transitions and line transients within the converter. In the condition that the output voltage is close to the input voltage, the buck-boost converter automatically switches from the step-down operation mode to the material pressure operation mode or from the material pressure operation mode to 5 by monitoring the maximum duty cycle. Hai down m operation mode. This simplifies the control of the elevating a converter and reduces the output voltage ripple. Both the buck mode operation and the dust mode operation use the same integrated current sensor, which reduces the complexity of the system and increases overall reliability. The beta non-inverting buck-boost converter is capable of achieving an output voltage above or below its input current. Multiple applications prefer non-inverting buck-boost converters, such as 'battery-powered devices that are eager to utilize the discharge cycle of the battery. Electronic devices and vehicles that are battery-powered suffer from poor battery voltage due to load dump or cold start. In these cases, non-inverting buck-boost converters are ideal candidates. If the load power is high, a multi-phase buck-boost converter is required for low cost and heat dissipation. Referring now to the drawings, and more particularly to Figure i, an overview of a step-up converter is depicted. The buck-boost converter includes an input voltage node 102 that applies an input voltage vIN. A high side buck transistor rigid includes a P-channel transistor that connects its source/drain path to node ι2 and node 1〇6. A low side buck transistor 1 〇 8 includes an N-channel transistor having its immersed/source path connected between node 1G6 and ground. - Inductor H U0 is connected between node 1〇6 and node 112. The high side P-channel boost transistor 114 is such that its source/secret path connection 201223110 is coupled between the output voltage node ν 〇υ τ 116 and node 112. A low side boosted sb body 11 8 includes an N-channel transistor having its source and drain paths connected between node 112 and ground. As is familiar to those skilled in the art, 'the high-side buck and boost transistors can also be implemented by N-channel electric solar cells.' All switching transistors can be double-loaded. The sub-transistor or any other suitable controlled switching device is implemented. The output capacitor 120 is coupled between the output voltage node 116 and ground. The output load resistor 122 is connected in parallel with the electric & 12 〇 between the node ι 6 and the ground. Each of the high-side step-down transistor 1〇4, the low-side step-down transistor, the high-side booster (four) 114, and the low-side boost transistor U8 each cause its pole to be connected to the buck-boost control. Circuit 124. The coughing and buckling control system uses internal control logic to generate a gate control signal via a plurality of outputs, and the control logic of the (fourth) portion is responsible for the output voltage ν〇υτ applied from at least the node "6. The duty cycle in this buck mode of operation is defined as D) / τ, where ^ is the on-time of the switching transistor just ' and τ is the switching period of the converter. τ is (4) (TM/fsw) of the switching frequency fsw. During the boosting operation, the duty cycle is defined as the on-time of the synchronized high-side boosting transistor... divided by the switching period. Referring now to Figure 2, a functional block diagram of a non-inverting buck-boost converter operating in accordance with the present disclosure is depicted. The buck-boost converter circuit 2〇2 receives the input voltage Vin at the input node 204 and the input voltage W at the node 2〇6. The switching cell system in the buck-boost converter 2G2 is driven in accordance with a drive control signal provided by the drive logic. The drive 201223110 logic 208 is responsive to the pwM control signal provided by the PWM control logic 21 to generate drive control signals to the switch transistors. The error amplifier and PWM control logic 21 are responsive to the output voltage monitored at node 2〇6 and also to the current control voltage VSUM provided by current slope control compensation logic 212 to generate the ρ· control signals. The current ramp control compensation logic is responsive to the current monitored by one of the current sensers 214 and the mode control logic η in the buck-boost converter 2〇2. To generate the 忒VSUM voltage to the error amplifier and the pWM control logic 21〇. The current sensor 214 measures the input current provided at the input node 204 of the buck-boost converter 2〇2. The mode control logic 216 determines whether the buck-boost converter 202 is operating in the buck mode or boost mode mode by monitoring the PWM signal provided by the PWM control logic 210. The mode control logic 216 additionally provides mode control signals to the drive: logic 208 to control operation of the switching transistor within the buck-boost converter 2〇2. Referring now to Figure 3', a block diagram of a non-inverting buck-boost converter of the present disclosure is depicted. The buck-boost converter 3〇2 includes an input voltage node 304 that applies an input voltage. A current sensor 3〇6 senses the input voltage current through node 304 and provides a sensed input current “ns. A high side buck transistor 3〇8 is connected to the current sensor 3 Between the 〇6 and the node 3 10. The high side buck transistor 308 includes a p-channel transistor. The high-side buck transistor 308 is coupled to receive the drive signal HD-BUCK. The buck transistor 3 12 includes a N-pass 201223110 transistor that connects its immersed/source path between node 310 and ground node 314. The low side buck transistor 312 is connected to receive the drive. Control #号 LD_BUCK. - Inductor 3 16 is connected between node 3 1〇 and node 3 18. A high side boost transistor 32 includes a source/drain path connected to the output voltage a P-channel transistor between node V0UT 322 and node 3 18. The low-side boosting transistor 321 includes an N-channel that connects its drain/source path to node 3 1 8 and node 3 14 The gate of the transistor 324 is connected to receive the drive control signal LD-B〇〇ST. The gate of the boost transistor 320 is connected to receive the drive control signal HD_B00ST. An output capacitor 326 is connected to the output voltage node 322 and between the output voltage node 322 and the ground node 314. In addition, a load 328 system The output capacitor 326 is connected in parallel between the output voltage node 322 and the ground node 314.

s亥咼側的降壓電晶體3 〇 8、低側的降壓電晶體3 12、高側的升壓電晶體320以及低側的升壓電晶體324的每一個的驅動控制信號係分別由該降壓模式電流邏輯及驅動器 330以及升壓模式控制邏輯及驅動器332提供。該降壓模式控制邏輯及驅動器3 3 0係響應於一由s R閂鎖3 3 4提供的 pWM信號（PWM—BUCK)以及一由該模式控制邏輯336提供的模式控制信號，以產生該HD_BUCK信號至該高側的降壓電晶體308以及產生該LD_BUCK信號至該低側的降壓電晶體312。該升壓模式控制邏輯及驅動器332係響應於一來自 SR閂鎖338的PWM控制信號（PWM—BOOST)以及一來自該模式控制邏輯336的模式控制信號，以產生該hd_BOOST 201223110 驅動#號至電晶體320以及產生該LD_BO〇ST驅動信號至電晶體324。該電晶體308及312是升降壓轉換器302在該降壓操作模式中的功率開關。在該降壓操作模式中，電晶體320總是被導通，並且電晶體324總是被關閉。同樣地，在該升壓操作模式中，該降壓模式控制邏輯及驅動器33〇以及該升壓模式控制邏輯及驅動器332係控制該升壓電晶體320及324以構成功率FET開關。在該升壓操作模式中，該電晶體308總是被導通，而該電晶體3 12是關閉的。該SR閂鎖334係響應於一在讓SR閂鎖334的s輸入提供的時脈信號以及—施加至該SR閂鎖334的尺輸入的邏輯佗號以產生遠降壓PWM信號至該降壓模式控制邏輯及驅動斋330。該PWM信號pWMJB〇〇ST係響應於一提供至該 ]、貞38的R輸入的時脈輸入以及一提供至sr閂鎖338 的s輸入的邏輯輸入而由SR閂鎖338的q輸出來提供。該板式控制邏輯336係提供該M〇DE信號給該降壓模式控制邏輯及驅動胃33〇以及升壓模式控制邏輯及驅動器 332的每一個。該模式控制邏輯336係分別響應於由sr閃鎖334及338的輸出提供的pwM_BUCK以及信號而產生該輸出控制信號MODE給該降壓模式控制邏輯及驅動益330以及升壓模式控制邏輯及驅動器的每一個。&最大卫作週㈣測電路34G係響應於輸出電壓ν〇υτ 接近輸入電壓 VIN以主丨啦7 + π d斷何時一最大的工作週期狀況存在於該降壓及升壓操作模式 ^曰+从 ^ %之間。當一取大的工作週期狀況偵測到時，該最大工你：« . A 作週期偵測電路.340係產生一邏輯“高 201223110 的”值給MAX D作號，兮Λ/Γ λ v ^ 邏輯342 β &MAX-D信號被提供至模式選擇該模式選擇邏輯342係決定該升降壓轉換器302是否需要切換到該降麼操作模式或是該升壓操作模式，並且產，一模式控制信號M0DE以指出此改變。為了平順地從降堅動作切換到升麗動作或是從升壓動作切換到降麼動作，該最大的工作週期的判斷係藉由該最大工作週期偵測電路 340而被引入該控制設計中。任何時候谓測到—最大的工作週=狀況時，該MAX—D信號係變為一邏輯“高的，，位準。此通吊發生在輸入電廢Vin接近輸出電壓或是在負載暫態出現於輸出巾的時候。職式選擇邏輯342係決定該升降壓轉換H 302的操作模式是降壓或升壓。—種簡單的控制方法係被實施成使得每當伯測到一 ΜΑχ』邏輯“高的” 信號時，該操作模式係被切換。較複雜的控制方法可藉由利用夕個MAX一D信號來加以應用。在該升降壓轉換器十有兩個刼作模式，並且也只有兩個操作模式，不是降壓就是升壓。該模式選擇邏輯的輸出“M〇DE”信號係作用像是一多工益控制信號，以根據該轉換器是在降壓或升壓操作模式 :來選擇操作電路（例如’電流感測）並且切換驅動器控制邏因此°亥M0DE控制信號係依據該操作模式來選擇該降壓模式控帝J邏輯驅動$ 33〇 $是該升壓模式控制邏輯及驅動器332 ’並且亦選擇由多工器344的輸出所提供的電流感測補償信號。 VSUM—BUCK信號或 3亥多工器344係連接以接收 12 201223110 VSUM一BOOST信號。該VSUM_BUCK信號係包括來自電流感測器306之感測到的電流、一降壓模式偏移（offset)信號以及一降壓斜率補償信號的加總，其係在加法器電路346 加總在一起。該VSUM_BOOST信號係在一加法器電路348 藉由將來自電流感測器306的ISNS輸入電流的量測、一升壓模式偏移信號以及一升麼斜率補償信號加總在一起來加以產生。來自該電流感測器306之感測到的電流ISNS係和該降壓模式偏移或升壓模式偏移加總，以確保誤差放大器 352是以一適當的DC偏壓來操作。該降壓或升壓補償斜率係被加到該感測到的電流以避免在大的工作週期的操作中之次證波的振盪。該VSUM-BUCK及VSUM—B00ST補償信號的每一個係被提供至該多工器344的一輸入。根據該升降壓:轉換器302是操作在該降壓操作模式或升壓操作模式，不是VSUM_BUCK(降壓模式）就是VSUM_B00ST(升壓模式）會響應於在多工器344的MODE信號而被選出，並且該所選的信號係被提供作為該輸出電流補償信號vsum。該VSUM信號係從該多工器344被提供至一 pwM比較器350的反相的輸入。該PWM比較器35〇的非反相的輸入係連接以從一誤差放大器352接收該電壓誤差信號。 s亥§吳差放大器352的輸出係透過一電容器354與一電阻器 356的串聯來連接至接地。該誤差放大器352的反相的輸入係透過由一連接在節點322及節點36〇間之電阻器358以及一連接到節點360及接地間之電阻器所構成的一電阻分壓益來監測在節點322的輸出電壓νουτ。誤差放大器352 13 201223110 的反相的輸入係連接至節點360。該誤差放大器352係比較施加在其非反相的輸入之參考電壓VREF與來自該升降壓轉換器302的輪出回授電壓以產生誤差信號VC0MP。該The drive control signals of each of the step-down transistor 3 〇 8 on the 咼咼 side, the step-down transistor 3 12 on the low side, the boost transistor 302 on the high side, and the boost transistor 324 on the low side are respectively The buck mode current logic and driver 330 and boost mode control logic and driver 332 are provided. The buck mode control logic and driver 320 is responsive to a pWM signal (PWM_BUCK) provided by the s R latch 3 3 4 and a mode control signal provided by the mode control logic 336 to generate the HD_BUCK. The signal is applied to the high side buck transistor 308 and the LD_BUCK signal is generated to the low side buck transistor 312. The boost mode control logic and driver 332 is responsive to a PWM control signal (PWM_BOOST) from the SR latch 338 and a mode control signal from the mode control logic 336 to generate the hd_BOOST 201223110 drive #号 to power The crystal 320 and the LD_BO〇ST drive signal are generated to the transistor 324. The transistors 308 and 312 are power switches of the buck-boost converter 302 in the step-down mode of operation. In this step-down mode of operation, the transistor 320 is always turned on and the transistor 324 is always turned off. Similarly, in the boost mode of operation, the buck mode control logic and driver 33 and the boost mode control logic and driver 332 control the boost transistors 320 and 324 to form a power FET switch. In this boost mode of operation, the transistor 308 is always turned on and the transistor 3 12 is turned off. The SR latch 334 is responsive to a clock signal provided at the s input of the SR latch 334 and a logic apostrophe applied to the scale input of the SR latch 334 to generate a remote buck PWM signal to the buck. Mode control logic and drive fast 330. The PWM signal pWMJB〇〇ST is provided by the q output of the SR latch 338 in response to a clock input provided to the R input of the 贞38, and a logic input provided to the s input of the sr latch 338. . The panel control logic 336 provides the M〇DE signal to the buck mode control logic and the drive stomach 33 and the boost mode control logic and driver 332. The mode control logic 336 generates the output control signal MODE to the buck mode control logic and the drive benefit 330 and the boost mode control logic and driver in response to the pwM_BUCK and the signal provided by the outputs of the sr flash locks 334 and 338, respectively. Every. &Maximum Guard Week (4) Measure circuit 34G is in response to the output voltage ν 〇υ τ approaching the input voltage VIN to the main 7 7 + π d break when a maximum duty cycle condition exists in the buck and boost mode of operation ^ 曰+ from ^% between. When a large duty cycle condition is detected, the maximum work is: « . A cycle detection circuit .340 generates a logic "high 201223110" value for MAX D, 兮Λ / Γ λ v ^ Logic 342 β & MAX-D signal is supplied to mode selection. The mode selection logic 342 determines whether the buck-boost converter 302 needs to switch to the reduced operation mode or the boost operation mode, and a mode The signal M0DE is controlled to indicate this change. In order to smoothly switch from the lowering action to the lifting action or from the boosting action to the falling action, the determination of the maximum duty cycle is introduced into the control design by the maximum duty cycle detecting circuit 340. The MAX-D signal becomes a logic "high," level at any time when the maximum working week = condition is detected. This pass occurs when the input electrical waste Vin approaches the output voltage or is in the load transient. When appearing in the output towel, the job selection logic 342 determines that the operating mode of the buck-boost conversion H 302 is buck or boost. A simple control method is implemented such that every time a test is detected The "high" signal is switched when the operating mode is switched. The more complicated control method can be applied by using the MAX-D signal. There are two modes in the buck-boost converter, and only The two modes of operation, either buck or boost, the output of the mode select logic "M〇DE" signal acts like a multi-benefit control signal, depending on whether the converter is in buck or boost mode of operation: To select the operating circuit (such as 'current sensing') and switch the driver control logic. Therefore, the M0DE control signal is selected according to the operating mode to select the buck mode control J logic drive $ 33 〇 $ is the boost mode control logic The driver 332' also selects the current sense compensation signal provided by the output of the multiplexer 344. The VSUM-BUCK signal or the 3 multiplexer 344 is connected to receive the 12 201223110 VSUM-BOOST signal. The VSUM_BUCK signal is included from The sum of the sensed current of current sensor 306, a buck mode offset signal, and a buck slope compensation signal are summed together in adder circuit 346. The VSUM_BOOST signal is tied An adder circuit 348 is generated by summing the measurement of the ISNS input current from the current sensor 306, a boost mode offset signal, and a liter slope compensation signal. From the current sensor The sensed current ISNS of 306 and the buck mode offset or boost mode offset are summed to ensure that the error amplifier 352 operates with an appropriate DC bias. The buck or boost compensation slope is The sensed current is applied to avoid oscillation of the secondary syndrome during operation of a large duty cycle. Each of the VSUM-BUCK and VSUM-B00ST compensation signals is provided to one of the multiplexers 344. lose According to the buck-boost: converter 302 is operating in the buck mode or boost mode, not VSUM_BUCK (buck mode) or VSUM_B00ST (boost mode) is responsive to the MODE signal at multiplexer 344 Selected, and the selected signal is provided as the output current compensation signal vsum. The VSUM signal is supplied from the multiplexer 344 to the inverted input of a pwM comparator 350. The PWM comparator 35 The non-inverting input is coupled to receive the voltage error signal from an error amplifier 352. The output of the sigma amplifier 352 is coupled to ground through a capacitor 354 in series with a resistor 356. The inverting input of the error amplifier 352 is monitored at a node by a resistor divided by a resistor 358 connected between the node 322 and the node 36 and a resistor connected between the node 360 and the ground. The output voltage of 322 is νουτ. The inverted input of error amplifier 352 13 201223110 is coupled to node 360. The error amplifier 352 compares the reference voltage VREF applied to its non-inverted input with the round-trip feedback voltage from the buck-boost converter 302 to produce an error signal VC0MP. The

Vc〇MP仏號係被用來判斷在升降壓轉換器操作在降壓操作模式時的一峰值電流模式以及在升降壓轉換器操作在升壓操作模式時的一谷值電流模式中通過電感器316的電感器電机降壓操作與升壓操作係共用相同的電壓誤差信號。來自多工益344的輸出的Vsum與該電壓誤差信號Vc〇Mp的比較係決定功率電晶體則、312、32G&似的導通/關閉狀態。忒PWM比較器350的輸出（Vc〇Mp〇UT)係被提供作為_ 反相器362的一輸入以及AND閘364的一第一輸入。來自反相器362之反相的輸出係被提供至〇尺閘366的一第—輸入。OR閘366的另一輸入係連接以接收來自該最大工作週期偵測電路340的輸出的MAX_D信號。該〇R閘抓的輸出係提供邏輯信號關鎖334的R輸人以致能該降壓pwM 信號的產生。AND閘364的另一輸入係連接至一反相器細的輸出。反相器368的輸入係連接以從該最大工作週期保護電路340接收該MAX_D信號。AND閘364的輸出係連接至另一反相器370。該反相器370的輸出係提供一邏輯俨號至SR閃鎖338的S輸入以提供該升壓pwM信號。。現在參照圖4,其描繪有-描述圖3的升降壓轉換器的操作之流程圖。當該轉換器的操作在步驟4〇2起始時，該轉換器最初在步驟404操作於降壓操作模式中並且工作在 14 201223110 4峰值電流控制的操作模式中。查詢步驟A%係監測最大的工作週期，並且若目前未偵測到最大的工作週期時，則控制傳回到步驟404。當偵測到最大的工作週期時，該轉換器係在步驟408進入升壓操作模式並且利用谷值電流控制模式來操作。查詢步驟41〇係監測最大的工作週期，並且若未偵測到最大的工作週期時，控制係傳回到步驟4〇1當偵測到最大的工作週期時，該轉換器係在步驟4〇4轉回^ 操作於降壓操作模式中。現在參照圖5,其描繪有當該升降壓轉換器3〇2從降壓操作模式轉換至升壓操作模式時的各種與該料壓轉換器相關連的波形。電晶體3〇8纟312係構成降壓操作模式; 的主要功率開關。電晶冑32〇在該降壓操作模式中總是導通’並且電晶It 324在降壓操作模式中總是關閉。隨著輸入電壓VIN 502 T降，㈣的工作週期係因$ D〜v〇ut/Vin 而增加。當輸入電壓Vin 502下降至某—值，該工作週期係到達一最大的臨界值（最大的工作週期）時，該最大工作週期偵測電路340(其在一實施例中係包括一數位比較器)係響應於此狀況並且將該信號MAX—D設定為一邏輯“高的，，位準。同時，該高側的電晶體308係被關閉，並且該電晶體 312係被導通。該模式選擇邏輯342知道下一個週期並且當該時脈信號出現在該SR閃鎖334的輸入時，該升降壓轉換器302冑會轉換成為升壓模式。該控制㈣Μ_係在該時脈脈衝到達時被設定到一邏輯“高的，，位準（升壓"並且該升降壓轉換器現在被組態設定在升壓操作中。然而，在 15 201223110 ^狀況中，輸入電壓VlN 5〇2仍然是比輸出電壓v〇UT 5〇4 尚一點，因而該升壓操作模式可能正在泵送過多的能量到負載中並且進步增尚輸出電壓νοι；τ。因此，該升降壓轉換器302係在升壓週期之後回到降屋操作模式，並且維持在降屋操作模式中超過—週期，直到輪出電塵ν_ 5〇4下降到輸入電堡VIN以下為止。隨著Vin5〇2進一步下降，將會有更多升塵週期。以此種方式，從降塵操作模式至升壓操作模式之平順的轉換係被提供。圖5亦描繪該多工器Μ# 的輸出vSUM 506、誤差放大器ν_ρ 5〇8的輸出以及電感器電流5 1 0。現在參照圖6,其描繪有該升降壓轉換器3〇2從升壓操作模式至降壓操作模式的轉換。當輸入電壓Vi“〇2遠低於輸出電壓VQUT 6G4時，該升降壓轉換器係運行在—純升壓操作模式中。電晶冑32。及324係構成在升壓操作模式中之主要的功率開關，而電晶m總是導通，並且電晶體川總是關閉。隨著輸入電壓Vin6〇2增高，切換的工作週期係增加，因為該升降壓轉換器3〇2是在谷值控制操作模士中。當輸入電壓Vin 602增高到某一位準是工作週期到達 -最大的臨界值位準(最大的工作週期)時，該包括一數位比較器的最大工作週期偵測電& 34〇係響應於此狀況並且將 =信號M A X—D設定為-邏輯“高的，，位準。同時，該高側的 ▲晶體320係被關閉，並且低側的電晶體似係被導通。 :模式選擇邏II 342知道下一個週期，當一時脈信號出現時’該轉換器將會轉換成為降壓模式。當該時脈信號到達 16 201223110 時，該信號“MODE”係被設定為一邏輯“低的，，位準（降壓模式）’並且該整個升降壓轉換器係被組態設定在降壓操作模式十。然而，在此狀況中，輸入電壓Vin6〇2仍然是低於輸出電遂V0UT 604。因此，該降壓操作模式可能正在拉走過多至負載的能量，並且輸出電壓ν〇υτ 6〇4係減小。因此，該升降壓轉換器302係在降壓週期之後回到升壓操作模式，並且維持在升壓操作模式中超過一週期，直到輸出電壓604增高為止。隨著輸入電壓Vin 6〇2進—步增高，可能有更多的降壓週期。以此種方式，從升壓至降壓之平順的轉換係被提供。圖6的繪圖進一步描繪多工器344的輸出Vs_ 6〇6、 3吳差電壓輸出vCOMP 608以及電感器電流61〇。备輸出電壓νουτ接近輸入電壓vIN時，該升降壓轉換器302:係從降壓切換至升壓，以及從升壓切換至降壓模式。沒有只是降壓模式及升壓模式之獨立的升降壓模式。該控制方法係藉由在降壓操作模式中利用峰值電流控制模式以及在升壓操作模式中利用谷值電流控制模式來確保平順的轉換。此方法之一主要的優點是該誤差信號vc〇Mp在模式轉換期間並沒有任何突然的變化。由於Vc〇Mp信號是輸出電壓 V0UT的一直接的函數’若該誤差信號vC0MP是穩定的，則 έ亥輸出電壓VOUT是穩定的。如先前所述，該多工器的輪出 Vsum是該輸入電流ISNS、降壓或升壓模式偏移以及—斜率補償信號的總和。在該降壓及升壓操作模式中不同的偏移值係根據在一全週期中之最大的斜率補償來加以選出。通 17 201223110 常該些不同的偏移值是該最大的斜率補償電壓的兩倍。例如，若該斜率補償是！ V/us並且該切換頻率是1ΜΗζ，則該不同的偏移值是1V/US*1US*2，此係2V。因此，若在降壓模式中的偏移是Vos，則用於升壓模式的偏移是v〇s+2v。一種以此方式操作的系統係提供在輕負載以及重負載狀況中都是優異的線暫態。當輸出電壓接近輸入電壓時，電壓漣波亦是小的。控制方法是簡單的，此只需要單一整合的電流感測器以及逐週期的彳貞測。現在參照圖7，其描繪有該多相非反相升降壓轉換器的一方塊圖。該誤差放大器702係提供一回授分壓器以及迴路補償給該多相非反相升降壓轉換器。該誤差放大器7〇2 係產生一補償信號VC0MP，該補償信號vC0MP係被提供至和該多相非反相升降壓轉換器的每個相位相關連的調變器及驅動器電路704的每一個。該調變器及驅動器電路7〇4係響應於來自誤差放大器702的Vc〇Mp信號以及一來自相關的電流感測器708的電流信號Isns以產生驅動信號至一相關的升降壓轉換器706。該電流感測器708係監測相關的升降壓轉換器706的一輸入電流，以便產生Isns電壓信號至相關的調變器及驅動器7〇4。該升降壓轉換器7〇6係產生被誤差放大器702監測的輸出電壓νουτ，以便產生該補償電壓Vc⑽ρ。現在參照圖8，其描繪有該調變器及驅動器電路7〇4的一方塊圖’該調變器及驅動器電路7〇4係和該多相非反相升降壓轉換器的每個相位相關連。該PWM邏輯802係產生 18 201223110 该些PWM控制信號至驅動邏輯8〇4及模式控制邏輯_。該驅動邏輯_係響應於由PWM邏輯802提供的pwM控制信號來產生驅動信號至相關的升降壓轉換器的開關電晶體。該模式控制邏輯806係藉由監測來自該邏輯⑽2 的PWM信號來判斷該升降㈣換器是操作在降壓操作模式或是升壓操作模式中。該模式控制輯，係另外提供模式控制信號至該驅動邏輯8〇4以控制升降壓轉換器内之開關電晶體的動作。該電流斜率補償電@ 8G8係響應於來自該升降壓轉換器且由該電流感測器7〇8(圖7)提供之一監測到的電流iSNS以產生一 VsUM電壓至該PWM邏輯8〇2。現在參照圖9，其係提供有該多相非反相升降壓轉換器之一更詳細的方塊圖，該多相非反相升降壓轉換器係提供在該升降壓轉換器的不同相位間之本質電流分擔。如先前所述’ §亥s吳差放大器部分702係監測在節點9〇2的來自該升降壓轉換器706的多個相位之結合的輸出的輸出電壓。該誤差放大器電路702係包含由一連接到節點9〇2及節點 906間之電阻器904以及一連接到節點906及接地間之電阻器908所構成的一分壓器。一回授電壓Vfb係在節點9〇6 藉由一 5吳差放大器910的一反相的輸入來加以監測。嗔差放大器9 10的非反相的輸入係接收一用於和該回授電壓VpB 比較的參考電壓VREF。該誤差放大器910的輸出係連接至節點912以提供一 VC0MP輸入到和該多相非反相升降壓轉換器的每個相位相關連的調變器及驅動器704的每—個。串聯連接的比較器914及電阻器916係連接到節點912及 19 201223110 接地之間。該比較器914係連接到節點912及節點91 8之間’並且該電阻器916係連接到節點91 8及接地之間。該誤差放大器910係包括一互導放大器，該互導放大器係產生一饋送到調變器及驅動器電路704的每一個的補償信號 Vcomp。該系統只需要單一誤差放大器910。然而，多個誤差放大器910可以並聯方式設置’並且該誤差放大器的總增益將包括該些誤差放大器的每一個的總和。圖9中所繪的系統的第二部分係包括調變器及驅動器 7 0 4。這些s周變器及驅動器7 〇 4係分別連接以接收來自該誤差放大器910的補償信號VC0MP以及一電流感測信號 Isnsn ’ s亥電流感測信號ISNSN係相關於在該升降壓轉換器的輸入電壓節點與該多相轉換器的特定相位相關連之感測到的輸入電流。§亥轉換器的每個相位都需要一個別的調變器，因為用於每個相位的時脈信號是不同的，以便產生交錯的電感器電流以及比單一相位轉換器小的輸出及輸入漣波。一個N相位的轉換器理想上在相鄰的相位間會具有 360/n的相移。每個相位亦具有獨立的電流感測，從到IsNSn。此架構係提供一種本質電流平衡的機構。不論在降壓操作模式中的峰值電流模式或是在升壓操作模式中的谷值電流模式控制，該感測電流電壓isNSn係和補償信號 vC0MP做比較。由於Vc〇Mp是一在每個調變器間之共同的信號，因此該信號係平衡每個相位的電流。此係為該多相轉換器中之一大益處，其係降低設計的複雜度，同時達成優異的效能。每個相位都具有其本身的最大工作週期偵測電 20 201223110 路及模式選擇電路。當Vin接近v斯時，某些相位可能運作在降塵模式中，而其它則運作在升麗模式中，此係產生較小的輸出漣波。用於每個相位的調變器及驅動器電路取係產生該 HD一BUCKn、LD_BUCKn、HD—B00STn 及 LD_BOOSTn、給和其相關的相位之升降塵轉換器相關連的開關電晶體的每一個。化些驅動裔的輸出係被提供至該升降麼轉換器706之相關的功率開關電晶體。每個升降壓轉換器7〇6係包含一提供待調節的輸入電壓的輸入電壓節點915。一電流感測器 917係感測通過節點915的輸入電壓電流並且提供一感測到的輸入電流電壓iSNSn。一高側的降壓電晶體919係連接到該電流感測器917及節點920之間。該高側的降壓電晶體 91 9係包括P通道電晶體。該高側的降壓電晶體9丨9係連接以接收α亥驅動心號HD—BUCKn。-低側的降麗電晶體922 係包括一使得其汲極/源極路徑連接到節點92()及接地節點 924間之N通道電晶體。該低側的降壓電晶體922係連接以接收該驅動控制信號LD_BUCKn。一電感器926係連接到節點920及節點928之間。一高側的升壓電晶體930係包括一使得其源極/汲極路徑連接到該輸出電壓節點ν〇υτ 932及節點928間之p通道電晶體。該低侧的升壓電晶體934係包括一使得其汲極/源極路徑連接到節點928及接地節點9M間之N通道電晶體。電bb體934的閘極係連接以接收該驅動控制信號 HD—BOOSTn。在與該多相升降壓轉換器的每個相位相關連 21 201223110 的升降壓轉換器的每一個内的高側及低側的降壓及升壓開關電晶體以及電流感測器是相同的。每個升降壓轉換器係使得其輸出連接至節點932。此外，由一電阻器935所構成的一負載係連接到節點932及接地之間。一電容器936係和電阻器935並聯連接，而連接到節點932及接地之間。傳送到該高側的降壓電晶體918、低側的降壓電晶體 922、高側的升壓電晶體930及低側的升壓電晶體934的每一個的驅動控制信號係由該調變器及驅動器電路7〇4所提供。現在參照圖1 〇 ’其更特別描繪有用於產生這些閘極驅動開關信號的調變器及驅動器電路704之一概要的方塊圖。該降壓模式控制邏輯及驅動器1 〇〇2係響應於一由Sr 閂鎖1004提供的PWM信號（PWM—BUCK)以及由該最大的工作週期偵測及模式選擇邏輯1 〇〇6提供的模式控制信號，以產生該HD_BUCKn信號至該高側的降壓電晶體918並且產生s亥LD_BUCKn信號至該低側的降壓電晶體922。該升壓模式控制邏輯及驅動器1 〇〇8係響應於一來自 SR閂鎖1010的PWM控制信號（PWM_BO〇ST)以及一來自該最大的工作週期偵測及模式選擇邏輯1〇〇6的模式控制信號’以產生該HD—BOOSTn驅動信號至電晶體930，並且產生該LD_BOOSTn驅動信號至電晶體934。該電晶體91 8及 922是該升降壓轉換器在降壓操作模式中的功率開關。在降壓操作模式中，電晶體930總是被導通，並且電晶體934 總疋被關閉。同樣地，在升壓操作模式中，該降壓模式控制邏輯及驅動器1002以及該升壓模式控制邏輯及驅動器係 22 201223110 控制構成功率FET開關的升壓電晶體320及324。在升壓操作模式中’該電晶體91 8總是被導通，而電晶體922總是被關閉。該SR閂鎖1〇〇4係響應於一在該SR閂鎖1004的 S輸入提供的時脈信號以及一施加至該SR閂鎖1 004的R 輸入的邏輯信號，以產生該PWM_BUCK信號至該降壓模式控制邏輯及驅動器1002 »該PWM信號PWM_BO〇ST係響應於一在SR閂鎖1010的尺輸入接收的時脈輸入以及一提供至SR閂鎖101〇的s輸入的邏輯輸入，而由SR閂鎖1010 的Q輸出來加以提供。該最大的工作週期偵測及模式選擇邏輯1006係提供該模式信號至該降壓模式控制邏輯及驅動器1 〇〇2以及升壓模式控制邏輯及驅動器.1〇08的每一個。該最大的工作週期偵測及模式選擇邏輯1006係分別響應於由SR閂鎖1 〇〇4及 1010的輸出提供的PWM—BUCK及pWM—b〇〇St信號，以產生該輸出控制信號MODE至該降壓模式控制邏輯及驅動器1002以及升壓模式控制邏輯及驅動器丨〇〇8的每一個。該最大的工作週期偵測及模式選擇邏輯1〇〇6係響應於輸出電壓V0UT接近輸入電壓判斷一最大的工作週期狀況存在於該降壓及升壓操作模式間的何時。當偵測到該最大的工作週期狀況時，該最大的工作週期偵測及模式選擇邏輯1006係產生一邏輯“高的，，值給該MAX_D信號。該最大的工作週期偵測及模式選擇邏輯1〇〇6係決定該升降壓轉換器是否需要切換至該降壓操作模式或升壓操^ 模式並且產生一模式控制信號M〇DE以指出此項改變^為 23 201223110 了千順地從降麗操作切換至升麼操作或是從升壓操作切換至降壓操作，該最大的工作週期的判斷係藉由該最大的工作週期们収模式選擇邏輯贿而被以該㈣設計中。任何時㈣測到-最大的工作週期狀況時，該ΜΑχ師號係變為-邏輯“高，，。此通常發生在以„〜接近輸^電壓ν〇υτ或是在負載暫態出現於輸出中的時候。該最大的工作週期偵測及模式選擇邏輯祕係決定料降壓轉換器的操作模式是降壓或升壓…種簡單的控制方法係被實施成使得每當彳貞測到一 MAX_D邏輯“高的，，信號時，該操作模式係被切換。較複雜的控制方法可藉由利用多個MM』信號來加以應用。在該升降壓轉換器中有兩個操作模式，並且也只有兩個操作模式，不是降壓就是升壓。該最大的工作週期偵測及模式選擇邏輯1〇〇6的模式輸出“MODE”信號係作用像是一多工器控制信號，以根據該轉換器是在降壓或升壓操作模式中來選擇操作電路（例如，電流感測）並且切換驅動器控制邏輯。因此，該模式控制信號係依據該操作模式來選擇該降壓模式控制邏輯驅動器1002 或是該升壓模式控制邏輯及驅動器1008，並且亦選擇由多工器1012的輸出所提供的電流感測補償信號。该多工器1012係連接以輸出vsum_BUCK信號或 vsum_boost信號。該VsuM_BUCK信號係包括來自電流感測器916之感測到的電流、該降壓模式偏移信號以及一降壓斜率補償信號的加總，其係在加法器電路1〇14加總在一起。該乂別1^_30〇87'信號係在加法器1〇16藉由將來自電流 24 201223110 感測器916 # ISNS輸人電流的量測、一升壓模式偏移信號以及一升壓斜率補償信號加總在一起來加以產生。來自該電流感測H 91 6之感測到的電流電壓係和該降壓模式偏移或升壓模式偏移加總，以確保誤差放大器9丨〇是以一適當的D C偏壓來操作。該降壓或升壓補償斜率係被加到該感測到的電流以避免在大的工作週期的操作甲之次諧波的振盪。該VSUM—BUCK及VsuM一B〇〇ST補償信號的每一個係被提供至該多工器1012的輸入。根據該升降壓轉換器是操作在一降壓刼作模式或是一升壓操作模式中，不是該 Vsum_BUCK(降壓模式）就是該VsuM—B〇〇ST(升壓模式）響應於多工器1012的模式信號而被選出，並且該所選的信號係被提供作為該輸出電流補償信號VSUM。諸VSUM信號係被提供至P WM比較器1 〇丨5的反相的輸入。談iPWM比較器丨015的非反相的輸入係連接以從一誤差放大器910接收該電壓誤差信號Vc〇Mp。該Vc〇Mp信號係如同先則相關在s亥多相操作模式中的單一相位操作模式所述地來加以利用。該PWM比較器1015的輸出係被提供作為一反相器1017的一輸入。來自反相器1〇17之反相的輸出係被提供至OR閘101 8的一第一輸入以及AND閘i 〇2〇的—第一輸入。OR閘101 8的另一輸入係連接以從該最大的工作週期偵測及模式選擇邏輯1〇〇6的輸出接收該 MAX—D信號。該AND閘1020的另一輸入係連接以從一反相器1022接收一反相的MAX—D信號。該〇R閘1〇18的輸出係提供該邏輯信號至該SR閂鎖1〇〇4的r輸入以致能該 25 201223110 降壓PWM信號的產生。AND閘1〇2〇的輪出係被提供至一反相器1024 »反相器1024的輸出係提供至SR閂鎖丨〇 i 〇的S輸入以助於該升壓PWM信號的產生。該最大的工作週期偵測及模式選擇邏輯1 006係響應於來自sR閂鎖i 〇〇4的輸出的PWM—BUCK信號、來自該SR閂鎖1010的 PWM_BOOST信號以及一時脈輸入信號以產生該max_d 控制信號以及模式控制信號。現在參照圖11，其描繪有該最大的工作週期偵測及模式選擇邏輯1006的一種實施方式。該MAX_D信號係被提供至一 SR閂鎖11 〇2的一 S輸入。一時脈輸入clk係被提供至該SR閂鎖1102的R輸入。該SR閂鎖11〇2的Q輸出係被提供至一對AND閘1104及1106的一輸入。該AND 閘11〇4係在其輸入接收該PWM_BUCK信號、來自反相器 1108之一反相的模式信號輸入以及SR閂鎖【丨〇2的輸出。類似地，該AND閘1106係在其輸入接收SR閃鎖11〇2的輸出、該模式信號以及來自反相器U1〇之該pWMJB〇〇ST 佗號的一反相的版本^ AND閘11 〇4的輸出係被提供至SR 閂鎖1112的S輸入。該SR閂鎖的R輸入係接收AND閘 11〇6的輸出。SR閂鎖1112的Q輸出係提供一 m〇de_pre 信號’該MODE—PRE信號係被提供至延遲閂鎖m4的一 D 輸入。該延遲閂鎖1114的時脈輸入係連接以接收該clK信號’並且延遲閂鎖1114的q輸出係提供該M〇dE信號。圖11的電路的基本操作係如下。當VIN接近νουτ時，該工作週期係接近1 〇〇%。為了維持每個週期的切換，一最 26 201223110 大的工作週期信號(MAX_D)係被預設。任何時候該些醜信號（PWM—BUCK以及PWM一B〇〇ST)到達該ΜΑχ d值時，一信號MODE—PRE係依據目前的操作模式（降塵或升屬）來加以設定或重置。然而，言亥M〇DE—咖最初並未施加至該調變器’而是只有在收到下一個時脈信號脈衝後才變成有效的’該時脈的上升邊緣係設定該模式信號並且調整該調變器的操作模式。每個調變器都具有其本身之獨立的決策電路。現在參照圖12，其描緣有一運作在其中Vin大於v蒙的降屋模式穩態中的雙相非反相升降壓轉換器。這些波形係描繪升降壓模式運作在„於％的降壓模式。該電感器電流係被交錯，以達成電流分擔及小的輸出漣波。母個相位的電流係被平衡。 …現在參照圖13,其描繪有—在其中〜更接近v_的降㈣作模式中的雙相非反相升降壓轉換器。該電感器電、"宁 L係以一種比純降壓及姑# T至及炖升壓模式更複雜的方式來加以交 .曰在此操作區域中，該轉換器係在一降壓及升壓模式間來回也4乍’以便调節該輸出電壓。以此種方式，一相位可運作在降壓模式中，而另_相位係操作在升壓模式中。以此種方式’冑出漣波係被減低。The Vc〇MP 仏 is used to determine a peak current mode when the buck-boost converter operates in the buck mode of operation and through the inductor in a valley current mode when the buck-boost converter operates in the boost mode of operation. The inductor motor step-down operation of 316 shares the same voltage error signal as the boost operating system. The comparison of the Vsum of the output from the multi-benefit 344 with the voltage error signal Vc 〇 Mp determines the on/off state of the power transistor, 312, 32G & The output (Vc 〇 Mp 〇 UT) of the 忒 PWM comparator 350 is provided as an input to the _ inverter 362 and a first input to the AND gate 364. The output from the inverting of inverter 362 is provided to a first input of scale switch 366. Another input of OR gate 366 is coupled to receive the MAX_D signal from the output of the maximum duty cycle detection circuit 340. The output of the 〇R gate captures the R input of the logic signal lock 334 to enable the generation of the buck pwM signal. The other input of AND gate 364 is coupled to an inverter fine output. The input of inverter 368 is coupled to receive the MAX_D signal from the maximum duty cycle protection circuit 340. The output of AND gate 364 is coupled to another inverter 370. The output of the inverter 370 provides a logic signal to the S input of the SR flash lock 338 to provide the boosted pwM signal. . Referring now to Figure 4, there is depicted a flow diagram depicting the operation of the buck-boost converter of Figure 3. When the operation of the converter begins at step 4〇2, the converter initially operates in the step-down mode of operation at step 404 and operates in the operating mode of the peak current control of 14 201223110 4 . The query step A% monitors the maximum duty cycle, and if the maximum duty cycle is not currently detected, then control passes back to step 404. When the maximum duty cycle is detected, the converter enters the boost mode of operation at step 408 and operates with the valley current control mode. The query step 41 monitors the maximum duty cycle, and if the maximum duty cycle is not detected, the control returns to step 4〇1. When the maximum duty cycle is detected, the converter is in step 4. 4 Turn back to ^ Operation in the step-down operation mode. Referring now to Figure 5, there are depicted various waveforms associated with the material pressure converter when the buck-boost converter 3〇2 transitions from the step-down mode of operation to the step-up mode of operation. The transistor 3〇8纟312 system constitutes the step-down mode of operation; the main power switch. The transistor 32 is always conducting in the step-down mode of operation and the transistor It 324 is always off in the step-down mode of operation. As the input voltage VIN 502 T drops, the duty cycle of (4) increases due to $ D~v〇ut/Vin. When the input voltage Vin 502 drops to a value that reaches a maximum threshold (maximum duty cycle), the maximum duty cycle detection circuit 340 (which in one embodiment includes a digital comparator) In response to this condition and setting the signal MAX-D to a logic "high, level. At the same time, the high side transistor 308 is turned off and the transistor 312 is turned "on". The logic 342 knows the next cycle and when the clock signal appears at the input of the SR flash lock 334, the buck-boost converter 302 turns into a boost mode. The control (four) Μ_ is when the clock pulse arrives Set to a logic "high, level (boost) and the buck-boost converter is now configured to be set in the boost operation. However, in the 15 201223110 ^ condition, the input voltage VlN 5〇2 is still It is a little more than the output voltage v〇UT 5〇4, so the boost mode of operation may be pumping too much energy into the load and progressing to increase the output voltage νοι;τ. Therefore, the buck-boost converter 302 is boosted. week Then return to the down mode operation mode and maintain the over-period in the down mode operation mode until the battery ν_ 5〇4 falls below the input VIN. As the Vin5〇2 drops further, there will be more A multi-dust cycle. In this way, a smooth transition from the dust-reduction mode to the boost mode is provided. Figure 5 also depicts the output of the multiplexer Μ# output vSUM 506, error amplifier ν_ρ 5〇8 And inductor current 5 1 0. Referring now to Figure 6, there is depicted a transition of the buck-boost converter 3〇2 from a boost mode of operation to a step-down mode of operation. When the input voltage Vi "〇2 is much lower than the output voltage VQUT At 6G4, the buck-boost converter operates in a pure boost mode of operation. The transistors 324 and 324 form the main power switch in the boost mode of operation, while the transistor m is always conducting and electrically The crystal channel is always off. As the input voltage Vin6〇2 increases, the switching duty cycle increases because the buck-boost converter 3〇2 is in the valley control operation mode. When the input voltage Vin 602 is increased to some Level is the duty cycle When the maximum threshold level (maximum duty cycle) is reached, the maximum duty cycle detection power of the one-bit comparator is responsive to this condition and the = signal MAX-D is set to - logic " At the same time, the high side ▲ crystal 320 is turned off, and the low side transistor seems to be turned on. : Mode select logic II 342 knows the next cycle, when a clock signal appears 'this The converter will be converted to buck mode. When the clock signal reaches 16 201223110, the signal "MODE" is set to a logic "low, level (buck mode)" and the entire buck-boost conversion The device is configured to be set in the buck mode of operation ten. However, in this case, the input voltage Vin6〇2 is still lower than the output power VOUT 604. Therefore, the buck mode of operation may be pulling too much energy to the load, and the output voltage ν 〇υ τ 6 〇 4 is reduced. Thus, the buck-boost converter 302 returns to the boost mode of operation after the buck cycle and remains in the boost mode of operation for more than one cycle until the output voltage 604 is increased. As the input voltage Vin 6〇2 increases step by step, there may be more buck cycles. In this way, a smooth transition from boost to buck is provided. The plot of FIG. 6 further depicts the output Vs_6〇6, 3 differential voltage output vCOMP 608, and inductor current 61〇 of the multiplexer 344. When the standby output voltage νουτ is close to the input voltage vIN, the buck-boost converter 302 switches from buck to boost and from boost to buck mode. There is no separate buck-boost mode for the buck mode and boost mode. The control method ensures smooth transitions by utilizing the peak current control mode in the buck mode of operation and the valley current control mode in the boost mode of operation. One of the main advantages of this method is that the error signal vc 〇 Mp does not have any sudden changes during mode switching. Since the Vc 〇 Mp signal is a direct function of the output voltage VOUT, if the error signal vC0MP is stable, the output voltage VOUT is stable. As previously described, the multiplexer's turn-out Vsum is the sum of the input current ISNS, the buck or boost mode offset, and the -slope compensation signal. The different offset values in the buck and boost modes of operation are selected based on the largest slope compensation in a full cycle. Pass 17 201223110 Often these different offset values are twice the maximum slope compensation voltage. For example, if the slope compensation is! V/us and the switching frequency is 1 ΜΗζ, then the different offset value is 1V/US*1US*2, which is 2V. Therefore, if the offset in the buck mode is Vos, the offset for the boost mode is v 〇 s + 2v. A system that operates in this manner provides excellent line transients in both light and heavy load conditions. When the output voltage is close to the input voltage, the voltage ripple is also small. The control method is simple, requiring only a single integrated current sensor and cycle-by-cycle speculation. Referring now to Figure 7, a block diagram of the multiphase non-inverting buck-boost converter is depicted. The error amplifier 702 provides a feedback divider and loop compensation to the multiphase non-inverting buck-boost converter. The error amplifier 7〇2 generates a compensation signal VC0MP which is supplied to each of the modulator and driver circuit 704 associated with each phase of the multiphase non-inverting buck-boost converter. The modulator and driver circuit 7〇4 is responsive to the Vc〇Mp signal from the error amplifier 702 and a current signal Isns from the associated current sensor 708 to generate a drive signal to a associated buck-boost converter 706. The current sensor 708 monitors an input current of the associated step-up converter 706 to generate an Isns voltage signal to the associated modulator and driver 〇4. The buck-boost converter 7〇6 generates an output voltage νουτ monitored by the error amplifier 702 to generate the compensation voltage Vc(10)ρ. Referring now to Figure 8, a block diagram of the modulator and driver circuit 7〇4 is depicted. The modulator and driver circuit 7〇4 is associated with each phase of the multiphase non-inverting buck-boost converter. even. The PWM logic 802 generates 18 201223110 of the PWM control signals to the drive logic 8〇4 and the mode control logic_. The drive logic is responsive to the pwM control signal provided by PWM logic 802 to generate a drive signal to the switching transistor of the associated buck-boost converter. The mode control logic 806 determines whether the up/down converter is operating in a buck mode or a boost mode by monitoring a PWM signal from the logic (10)2. The mode control sequence additionally provides a mode control signal to the drive logic 8〇4 to control the switching transistor operation in the buck-boost converter. The current slope compensation power @8G8 is responsive to the current iSNS from the buck-boost converter and provided by the current sensor 7〇8 (FIG. 7) to generate a VsUM voltage to the PWM logic 8〇2 . Referring now to Figure 9, there is provided a more detailed block diagram of one of the multiphase non-inverting buck-boost converters provided between the different phases of the buck-boost converter Essential current sharing. The output voltage of the output from the combination of the plurality of phases of the buck-boost converter 706 at node 9〇2 is monitored as previously described. The error amplifier circuit 702 includes a voltage divider formed by a resistor 904 connected between the node 9〇2 and the node 906 and a resistor 908 connected to the node 906 and the ground. A feedback voltage Vfb is monitored at node 9〇6 by an inverted input of a differential amplifier 910. The non-inverting input of the sigma amplifier 9 10 receives a reference voltage VREF for comparison with the feedback voltage VpB. The output of the error amplifier 910 is coupled to node 912 to provide a VC0MP input to each of the modulators and drivers 704 associated with each phase of the multiphase non-inverting buck-boost converter. A series connected comparator 914 and resistor 916 are connected between nodes 912 and 19 201223110 ground. The comparator 914 is coupled between node 912 and node 91 8 and the resistor 916 is coupled between node 91 8 and ground. The error amplifier 910 includes a transconductance amplifier that produces a compensation signal Vcomp that is fed to each of the modulator and driver circuit 704. This system requires only a single error amplifier 910. However, multiple error amplifiers 910 can be set in parallel' and the total gain of the error amplifiers will include the sum of each of the error amplifiers. The second portion of the system depicted in Figure 9 includes a modulator and driver 704. The s-variant and driver 7 〇4 are respectively connected to receive the compensation signal VC0MP from the error amplifier 910 and a current sensing signal Isnsn's current sensing signal ISNSN is related to the input at the buck-boost converter The sensed input current associated with the voltage node and a particular phase of the multiphase converter. § Each phase of the converter requires a different modulator because the clock signals for each phase are different to produce interleaved inductor current and smaller output and input than a single phase converter. wave. An N-phase converter would ideally have a phase shift of 360/n between adjacent phases. Each phase also has independent current sensing from IsNSn. This architecture provides a mechanism for intrinsic current balancing. The sense current voltage isNSn is compared with the compensation signal vC0MP regardless of the peak current mode in the step-down mode of operation or the valley current mode control in the step-up mode of operation. Since Vc 〇 Mp is a common signal between each modulator, the signal balances the current of each phase. This is one of the great benefits of this multiphase converter, which reduces the complexity of the design while achieving superior performance. Each phase has its own maximum duty cycle detection circuit 201222110 and mode selection circuit. When Vin is close to Vs, some phases may operate in the Dust mode, while others operate in the Ascending mode, which produces a smaller output chopping. The modulator and driver circuit for each phase generates each of the HD-BUCKn, LD_BUCKn, HD-B00STn, and LD_BOOSTn associated with the switching transistor associated with its associated phase lift filter. The output of the driver is provided to the associated power switch transistor of the riser converter 706. Each buck-boost converter 7〇6 includes an input voltage node 915 that provides an input voltage to be regulated. A current sensor 917 senses the input voltage current through node 915 and provides a sensed input current voltage iSNSn. A high side buck transistor 919 is coupled between the current sensor 917 and node 920. The high side step-down transistor 91 9 includes a P-channel transistor. The high-side step-down transistor 9丨9 is connected to receive the alpha-drive heart HD-BUCKn. The low side OLED 922 includes an N-channel transistor that connects its drain/source path to node 92 () and ground node 924. The low side buck transistor 922 is coupled to receive the drive control signal LD_BUCKn. An inductor 926 is coupled between node 920 and node 928. A high side boost transistor 930 includes a p-channel transistor having its source/drain path connected to the output voltage node ν 〇υ τ 932 and node 928. The low side boost transistor 934 includes an N-channel transistor having its drain/source path connected between node 928 and ground node 9M. The gate of the electric bb body 934 is connected to receive the drive control signal HD_BOOSTn. The high-side and low-side buck and boost switching transistors and current sensors in each of the buck-boost converters of the 201223110 are the same as each phase of the multiphase buck-boost converter. Each buck-boost converter has its output connected to node 932. Further, a load system composed of a resistor 935 is connected between the node 932 and the ground. A capacitor 936 is connected in parallel with resistor 935 and is connected between node 932 and ground. The drive control signal transmitted to each of the high side step-down transistor 918, the low side step-down transistor 922, the high side booster transistor 930, and the low side booster transistor 934 is modulated by the modulation And driver circuit 7〇4 are provided. Referring now to Figure 1 ’', a block diagram of an overview of a modulator and driver circuit 704 for generating these gate drive switch signals is more particularly depicted. The buck mode control logic and driver 1 响应2 are responsive to a PWM signal (PWM_BUCK) provided by the Sr latch 1004 and the mode provided by the maximum duty cycle detection and mode selection logic 1 〇〇6 The control signal is generated to generate the HD_BUCKn signal to the high side buck transistor 918 and generate a s LD_BUCKn signal to the low side buck transistor 922. The boost mode control logic and driver 1 响应8 is responsive to a PWM control signal (PWM_BO〇ST) from the SR latch 1010 and a mode from the maximum duty cycle detection and mode selection logic 1〇〇6. The control signal 'produces the HD-BOOSTn drive signal to the transistor 930 and generates the LD_BOOSTn drive signal to the transistor 934. The transistors 91 8 and 922 are power switches of the buck-boost converter in a step-down mode of operation. In the reduced voltage mode of operation, transistor 930 is always turned on and transistor 934 is turned off. Similarly, in the boost mode of operation, the buck mode control logic and driver 1002 and the boost mode control logic and driver system 22 201223110 control the boost transistors 320 and 324 that make up the power FET switch. In the boost mode of operation, the transistor 91 8 is always turned on, and the transistor 922 is always turned off. The SR latch 1〇〇4 is responsive to a clock signal provided at the S input of the SR latch 1004 and a logic signal applied to the R input of the SR latch 1 004 to generate the PWM_BUCK signal to the Buck mode control logic and driver 1002 » The PWM signal PWM_BO〇ST is responsive to a clock input received at the scale input of the SR latch 1010 and a logic input provided to the s input of the SR latch 101〇, The Q output of the SR latch 1010 is provided. The maximum duty cycle detection and mode selection logic 1006 provides the mode signal to each of the buck mode control logic and driver 1 〇〇 2 and boost mode control logic and drivers .1〇08. The maximum duty cycle detection and mode selection logic 1006 is responsive to the PWM-BUCK and pWM_b〇〇St signals provided by the outputs of the SR latches 1 〇〇 4 and 1010, respectively, to generate the output control signal MODE to The buck mode controls the logic and driver 1002 as well as the boost mode control logic and driver 丨〇〇8. The maximum duty cycle detection and mode selection logic 1-6 determines when a maximum duty cycle condition exists between the buck and boost modes of operation in response to the output voltage VOUT approaching the input voltage. When the maximum duty cycle condition is detected, the maximum duty cycle detection and mode selection logic 1006 generates a logic "high, value to the MAX_D signal. The maximum duty cycle detection and mode selection logic The 1〇〇6 system determines whether the buck-boost converter needs to switch to the buck operation mode or the boost operation mode and generates a mode control signal M〇DE to indicate that the change is 23 201223110 The operation is switched to the operation or the step-down operation is switched from the step-up operation to the step-down operation, and the judgment of the maximum duty cycle is adopted in the (four) design by the maximum duty cycle mode selection logic bribe. (4) When the maximum duty cycle condition is measured, the division number becomes - logical "high,,. This usually occurs when „~ is close to the voltage ν〇υτ or when the load transient appears in the output. The maximum duty cycle detection and mode selection logic determines the operating mode of the buck converter. Buck or boost... A simple control method is implemented such that each time a MAX_D logic "high" signal is detected, the mode of operation is switched. More complex control methods can be applied by utilizing multiple MM's signals. There are two modes of operation in the buck-boost converter, and there are only two modes of operation, either buck or boost. The maximum duty cycle detection and mode selection logic 1 的 6 mode output "MODE" signal acts like a multiplexer control signal to select according to whether the converter is in a buck or boost mode of operation. Operate the circuit (eg, current sensing) and switch the driver control logic. Therefore, the mode control signal selects the buck mode control logic driver 1002 or the boost mode control logic and driver 1008 according to the operation mode, and also selects the current sensing compensation provided by the output of the multiplexer 1012. signal. The multiplexer 1012 is connected to output a vsum_BUCK signal or a vsum_boost signal. The VsuM_BUCK signal includes a sum of the sensed current from current sensor 916, the buck mode offset signal, and a buck slope compensation signal, which are summed together in adder circuits 1〇14. The screening 1^_30〇87' signal is applied to the adder 1〇16 by measuring the current from the current 24 201223110 sensor 916 # ISNS, a boost mode offset signal, and a boost slope compensation. The signals are summed together to produce. The sensed current voltage from the current sense H 91 6 and the buck mode offset or boost mode offset are summed to ensure that the error amplifier 9 is operated with an appropriate D C bias. The buck or boost compensation slope is applied to the sensed current to avoid oscillation of the harmonics of the operation A during a large duty cycle. Each of the VSUM-BUCK and VsuM-B〇〇ST compensation signals is supplied to the input of the multiplexer 1012. According to the buck-boost converter operating in a step-down mode or a boost mode, not the Vsum_BUCK (buck mode) is the VsuM-B〇〇ST (boost mode) in response to the multiplexer The mode signal of 1012 is selected and the selected signal is provided as the output current compensation signal VSUM. The VSUM signals are supplied to the inverted inputs of P WM comparator 1 〇丨5. The non-inverting input system of iPWM comparator 丨 015 is coupled to receive the voltage error signal Vc 〇 Mp from an error amplifier 910. The Vc 〇 Mp signal is utilized as described above in relation to the single phase mode of operation in the sho multiphase mode of operation. The output of the PWM comparator 1015 is provided as an input to an inverter 1017. The output from the inverting of the inverters 1〇17 is supplied to a first input of the OR gate 101 8 and the first input of the AND gate i 〇2〇. Another input of OR gate 101 8 is coupled to receive the MAX-D signal from the output of the maximum duty cycle detection and mode selection logic 1-6. The other input of the AND gate 1020 is coupled to receive an inverted MAX-D signal from a inverter 1022. The output of the R gate 1〇18 provides the logic signal to the r input of the SR latch 1〇〇4 to enable the generation of the 25 201223110 buck PWM signal. The AND gate of the AND gate is supplied to an inverter 1024. The output of the inverter 1024 is supplied to the S input of the SR latch 丨〇 i 以 to facilitate the generation of the boost PWM signal. The maximum duty cycle detection and mode selection logic 1 006 is responsive to a PWM-BUCK signal from the output of the sR latch i 〇〇 4, a PWM_BOOST signal from the SR latch 1010, and a clock input signal to generate the max_d Control signals and mode control signals. Referring now to Figure 11, an embodiment of the maximum duty cycle detection and mode selection logic 1006 is depicted. The MAX_D signal is provided to an S input of an SR latch 11 〇2. A clock input clk is provided to the R input of the SR latch 1102. The Q output of the SR latch 11 〇 2 is provided to an input of a pair of AND gates 1104 and 1106. The AND gate 11〇4 receives the PWM_BUCK signal at its input, the mode signal input from one of the inverters 1108, and the output of the SR latch [丨〇2. Similarly, the AND gate 1106 is at its input receiving the output of the SR flash lock 11〇2, the mode signal, and an inverted version of the pWMJB〇〇ST 佗 from the inverter U1〇. The output of 4 is provided to the S input of the SR latch 1112. The R input of the SR latch receives the output of the AND gate 11〇6. The Q output of the SR latch 1112 provides a m〇de_pre signal. The MODE-PRE signal is provided to a D input of the delay latch m4. The clock input of the delay latch 1114 is coupled to receive the clK signal' and the q output of the delay latch 1114 provides the M〇dE signal. The basic operation of the circuit of Figure 11 is as follows. When VIN approaches νουτ, the duty cycle is close to 1 〇〇%. In order to maintain the switching of each cycle, a maximum duty cycle signal (MAX_D) of 201223110 is preset. Whenever the ugly signals (PWM-BUCK and PWM-B〇〇ST) reach the value of ΜΑχd, a signal MODE-PRE is set or reset according to the current operating mode (dusting or ascending). However, it is not applied to the modulator at first, but only becomes valid after receiving the next clock signal pulse. The rising edge of the clock sets the mode signal and adjusts The mode of operation of the modulator. Each modulator has its own independent decision circuit. Referring now to Figure 12, the description has a two-phase non-inverting buck-boost converter operating in a home mode steady state where Vin is greater than v. These waveforms depict the buck-boost mode operating at 5% of the buck mode. The inductor currents are interleaved to achieve current sharing and small output chopping. The parent phase current is balanced. ...refer now to Figure 13. , which is characterized by a two-phase non-inverting buck-boost converter in which ~ is closer to v_ in the falling (four) mode. The inductor is electrically, "Ning L is a ratio of pure buck and abundance #T to And the stew boost mode is more complicated to hand in. In this operating region, the converter is also looped back and forth between a buck and boost mode to adjust the output voltage. In this way, One phase can operate in the buck mode while the other phase operates in the boost mode. In this way, the chopping system is reduced.

現在參照圖14 ,苴炉έ合亡 π AReferring now to Figure 14, the furnace is collapsed and π A

，、描、會有一運作在其中VIN小於v0UT 的降壓模式中的雙相非反〆、非夂相升降壓轉換器。該電感器電流係被交錯，以達成雷、、*八 ^ ^ 成電机刀擔及小的輸出漣波。每個相位的電流係被平衡 27 201223110 因此，藉由並聯設置多個升降壓功率級，更大的功率係被達成。該設計係達成電流平衡而無須增加達成該電流平衡結果所需的額外電路。具有小的輸出漣波之模式間平順的線轉換亦被提供。熟習此項技術者在有此揭露内容的助益下將會體認到此非反相升降壓電壓轉換器係提供當在降壓及升壓操作模式間轉換時之改良的動作。應瞭解的是，該圖式以及在此的詳細說明係欲以一待，並且並不欲限制到該些揭露的特定形式及例子。相反, there is a two-phase non-reverse, non-夂 phase buck-boost converter operating in buck mode where VIN is less than v0UT. The inductor currents are interleaved to achieve lightning, *8^^ motor knives and small output ripple. The current of each phase is balanced. 27 201223110 Therefore, by setting a plurality of buck-boost power levels in parallel, a larger power is achieved. This design achieves current balancing without the need to add additional circuitry needed to achieve this current balance. A smooth line transition between modes with small output chopping is also provided. Those skilled in the art, with the benefit of this disclosure, will recognize that the non-inverting buck-boost voltage converter provides improved operation when switching between buck and boost modes of operation. It is understood that the drawings and the detailed description of the invention are intended to be in contrast

選擇、設計選項及實施例。種說明的方式而不是限制的方式來看【圖式簡單說明】為了更完整的理解現在係參考到以上結合所附的圖式所做的說明，其中：圖1是一種并降原一種升降壓棘桅Choices, design options, and examples. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT For a more complete understanding, reference is now made to the above description in conjunction with the accompanying drawings, in which: Figure 1 is a Thorny

壓轉換器的功能Pressure converter function

細的万塊圖；升降壓轉換器之更詳 28 201223110 圖4是描繪圖3的非反相升降壓轉換器的操作的流程圖；圖5a-5c係描繪當從降壓操作模式轉換至升壓操作模式時，該升降壓轉換器操作的波形；圖6a-6c係描繪當從升壓操作模式轉換至降壓操作模式時，該升降壓轉換器操作的波形；圖7是一種多相非反相升降壓轉換器的功能方塊圖；圖8是該多相升降壓轉換器的調變器及驅動器電路的方塊圖；圖9是該具有本質電流分擔的多相非反相升降壓轉換器之更詳細的方塊圖；圖1 0是該調變器及驅動器電路之概要的方塊圖；圖11是該最大的工作週期偵測及模式選擇電路之概要圖；圖12係描繪一運作在一降壓模式穩態中的雙相非反相升降壓轉換器的操作；圖13係描繪一運作在一降壓模式穩態中的雙相非反相升降壓轉換器；以及圖14係描繪一運作在一升壓模式穩態中的雙相升降壓轉換器。【主要 102 元件符號說明】輸入電壓節點降壓電晶體 29 104 201223110 106 節點 108 降壓電晶體 110 電感器 112 節點 114 升壓電晶體 116 節點 118 升壓電晶體 120 輸出電容 122 輸出負載電阻 124 升降壓控制電路 202 升降壓轉換器電路 204 輸入節點 206 輸出節.點 208 驅動邏輯 210 PWM控制邏輯 212 控制補償邏輯 214 電流感測器 216 模式控制邏輯 302 升降壓轉換器 304 輸入電壓節點 306 電流感測器 308 高側的降壓電晶體 310 節點 312 低側的降壓電晶體 30 201223110 314 接地節點 3 16 電感器 318 節點 320 高側的升壓電晶體 321 低側的升壓電晶體 322 輸出電壓節點 324 低側的升壓電晶體 326 輸出電容器 328 負載 330 降壓模式電流邏輯及驅動器 332 升壓模式控制邏輯及驅動器 334 SR閂鎖 336 模式控制邏輯 338 SR閂鎖 340 最大工作週期偵測電路 342 模式選擇邏輯 344 多工器 346 加法電路 348 加法電路 350 PWM比較器 352 誤差放大器 354 電容器 356 電阻器 358 電阻器 31 201223110 360 節點 362 反相器 364 AND閘 366 OR閘 368 反相器 370 反相器 402 步驟 404 步驟 406 查詢步驟 408 步驟 410 查詢步驟 502 VlN 504 V〇uT 506 VsUM 508 v COMP 510 電感Is電流 602 VlN 604 V OUT 606 VsUM 610 電感Is電流 702 誤差放大器 704 驅動器電路 706 升降壓轉換器 708 電流感測器 32 201223110 802 PWM邏輯 804 驅動邏輯 806 模式控制邏輯 808 補償電路 902 即點 904 電阻器 906 即點 908 電阻器 906 /rA- 即點 910 誤差放大器 912 々Λ* 即點 914 比較器 915 Ψηί 入電壓 /r/r 即點 917 電流感測器 918 即點 919 側的降壓電晶體 920 即點 922 低側的降壓電晶體 924 接地 Λ-Α* 即點 926 電感器 928 々Λ* 即點 930 尚側的升壓電晶體 932 V OUT 934 低側的升壓電晶體 33 201223110 935 電阻器 936 電容器 1002 控制邏輯及驅動器 1004 SR閂鎖 1006 模式選擇邏輯 1008 驅動器 1010 SR閂鎖 1012 多工器 1014 加法器電路 1015 PWM比較器 1016 加法器 1017 反相器 1018 OR閘 1020 AND閘 1022 反相器 1024 反相器 1102 SR閂鎖 1104 AND閘 1106 AND閘 1108 反相器 1110 反相器 1112 SR閂鎖 1114 延遲閂鎖 34Detailed diagram of the buck-boost converter 28 201223110 Figure 4 is a flow chart depicting the operation of the non-inverting buck-boost converter of Figure 3; Figures 5a-5c depict the transition from the buck mode of operation to the rise The waveform of the buck-boost converter operation in the press mode; Figures 6a-6c depict the waveform of the buck-boost converter operation when transitioning from the boost mode to the buck mode; Figure 7 is a multiphase non- Figure 4 is a block diagram of the modulator and driver circuit of the multiphase buck-boost converter; Figure 9 is the multiphase non-inverting buck-boost converter with intrinsic current sharing A more detailed block diagram; FIG. 10 is a block diagram of an outline of the modulator and driver circuit; FIG. 11 is a schematic diagram of the maximum duty cycle detection and mode selection circuit; Operation of a two-phase non-inverting buck-boost converter in buck mode steady state; Figure 13 depicts a two-phase non-inverting buck-boost converter operating in a buck mode steady state; and Figure 14 depicts a Operating in a boost mode steady state Biphasic down converter. [Main 102 component symbol description] Input voltage node buck transistor 29 104 201223110 106 node 108 buck transistor 110 inductor 112 node 114 boost transistor 116 node 118 boost transistor 120 output capacitor 122 output load resistor 124 Voltage Control Circuit 202 Buck-Boost Converter Circuit 204 Input Node 206 Output Section. Point 208 Drive Logic 210 PWM Control Logic 212 Control Compensation Logic 214 Current Sense 216 Mode Control Logic 302 Buck-Boost Converter 304 Input Voltage Node 306 Current Sensing 308 high side buck transistor 310 node 312 low side buck transistor 30 201223110 314 ground node 3 16 inductor 318 node 320 high side boost transistor 321 low side boost transistor 322 output voltage node 324 Low Side Boost Transistor 326 Output Capacitor 328 Load 330 Buck Mode Current Logic & Driver 332 Boost Mode Control Logic & Driver 334 SR Latch 336 Mode Control Logic RIS SR Latch 340 Maximum Cycle Detection 342 Mode Select logic 344 multiplex 346 Addition Circuit 348 Addition Circuit 350 PWM Comparator 352 Error Amplifier 354 Capacitor 356 Resistor 358 Resistor 31 201223110 360 Node 362 Inverter 364 AND Gate 366 OR Gate 368 Inverter 370 Inverter 402 Step 404 Step 406 Query Step 408 Step 410 Query Step 502 VlN 504 V〇uT 506 VsUM 508 v COMP 510 Inductance Is Current 602 VlN 604 V OUT 606 VsUM 610 Inductance Is Current 702 Error Amplifier 704 Driver Circuit 706 Buck-Boost Converter 708 Current Sense 32 201223110 802 PWM Logic 804 Drive Logic 806 Mode Control Logic 808 Compensation Circuit 902 Point 904 Resistor 906 Point 908 Resistor 906 /rA- Point 910 Error Amplifier 912 々Λ* Point 914 Comparator 915 Ψηί In Voltage /r/r That is, point 917 current sensor 918 is the step-down transistor 920 on the side of point 919, that is, the step-down transistor 924 on the low side of point 922 is grounded Λ-Α*, point 926 inductor 928 々Λ* ie point 930 side of the boost transistor 932 V OUT 934 low side boost transistor 33 201223110 935 resistor 936 capacitor 1002 control logic and driver 1004 SR latch 1006 mode select logic 1008 driver 1010 SR latch Lock 1012 multiplexer 1014 adder circuit 1015 PWM comparator 1016 adder 1017 inverter 1018 OR gate 1020 AND gate 1022 inverter 1024 inverter 1102 SR latch 1104 AND gate 1106 AND gate 1108 inverter 1110 Phaser 1112 SR latch 1114 delay latch 34

Claims

201223110 VII. Patent application scope: 1. A multi-phase non-inverting buck-boost voltage converter, comprising: a plurality of buck-boost voltage regulators respectively associated with one other phase for responding to input Voltage to produce a regulated output voltage; - a plurality of current sensors 'which are associated with the plurality of buck-boost voltage regulators respectively" for monitoring the boost voltage regulators Inputting a current and generating a current sense signal for the associated phase; a plurality of buck-boost mode control circuits respectively associated with one of the buck-boost voltage regulators for responding to a common error voltage and The associated current sense signal controls an associated buck-boost voltage regulator to utilize peak current mode control in a buck mode of operation and utilizes the plurality of buck-boosts in the valley current mode control 1 in the boost mode of operation a mode control circuit provides current balancing between the phases; and: a voltage error circuit responsive to the adjusted The output power is reversed to produce the common error voltage. For multi-phase non-inverting lifting dust and dust switching in the range of 帛1, the differential circuit further includes an error amplifier for responding to the adjusted output voltage and a reference voltage. ΜThe common error is expected. 3. If the patent application scope is the first item, the cypress ^, ^ Φ ^ ^ ^, the phasic non-inverted buck-boost voltage subcontract: · /, the multiple buck-boost mode Each of the control circuits further 35 201223110 PWM control logic for responding to a maximum duty cycle detection signal, the error voltage and the current sense signal to generate a buck PWM control signal and a boost pwM a control signal; a dust reduction mode control and driving circuit for responding to the buck PWM control signal and a mode signal to generate a high side buck switching transistor control signal and a low side buck switching transistor control a boost mode control and drive circuit responsive to the boost PWM control signal and the mode signal to generate a high side boost switch transistor control signal and a low side boost switch transistor control And a mode control logic responsive to the buck pWM control signal and the boost PWM control signal to generate the maximum duty cycle detection signal and the Type signal. 4. The apparatus of claim 3, further comprising: for generating a circuit, wherein in response to the first voltage system responding to the monitored input power and a buck mode slope compensation signal, a second The mode signal of the state is generated by the complementary input current and a boost mode offset signal. a multi-phase non-inverted buck-boost voltage to a current signal of a compensation voltage control mode, the compensation current, a buck mode offset signal is generated, and in response to the compensated voltage system responding to the monitoring And a boost mode slope compensation 7 m open phase phase rise and fall converter, wherein the current control compensation circuit further comprises: an electric first adder, which is used to add her ~, 忒 monitored input power 36 201223110 The buck mode offset signal and the buck mode slope compensation signal are used to generate a buck voltage compensation signal; - the second adder is used to sum up the monitored turn-in current, the boost mode bias Transmitting m the boost mode slope compensation signal to generate a boost voltage compensation signal; and a multiplexer 'in response to the mode signal between the buck voltage compensation signal and the (four) voltage compensation signal Select as the electric castle compensation signal. 6. The multiphase non-inverting buck-boost voltage converter of claim 3, wherein the sig mode control logic further comprises: a maximum duty cycle detection circuit responsive to the buck pwM control signal and The boost PWM control signal detects a maximum duty cycle condition and generates the maximum duty cycle detection signal; and a mode selection circuit for detecting the signal in response to the maximum duty cycle and a clock signal to generate the mode signal, the mode signal indicating an operation in one of the boost mode of operation and the step-down mode of operation. 7. 7. The multiphase non-inverting buck-boost voltage of claim 3 The converter, the mode control logic further comprising: first control logic for setting a first value in response to a buck PWM control or a boost pwM control signal reaching a maximum duty cycle value; The first control logic is configured to output the first value as the mode signal in response to a clock signal. 37 201223110 8. The multiphase non-inverting lifting piezoelectric converter according to claim 3, wherein the buck-boost voltage regulating circuit further comprises: a high side buck switching transistor; a low side buck a switching transistor; a high side boost switching transistor; a low side boost switching transistor; wherein in the buck mode of operation, the high side boost switching transistor control signal and the low side a boost switch transistor control signal, the south side boost switch transistor system is turned on and the low side boost switch transistor system is turned off, and responsive to the high side buck switch transistor control signal and the a low side buck switch transistor control signal, the high side buck switch transistor and the low side buck switch cell system being selectively switched; and wherein in the boost mode of operation, in response to the The high side buck switch transistor control signal and the low side buck switch transistor control signal, the side buck switching cell system is turned on and the low side buck switch cell Is turned off' and in response to the high side boost switch transistor control signal and the low side boost switch transistor control signal, the high side boost switch transistor and the low side boost switch transistor The system is selectively switched. 9. The multiphase non-inverting buck-boost voltage converter of claim 3, wherein the P WM control logic further comprises: a PWM comparator for comparing the error voltage with the compensation voltage and responsive to The error voltage and the compensation voltage are used to generate a pWM signal 38 201223110 *; PWM control logic for generating a first PWM signal and a response in response to the p WM signal and the maximum duty cycle detection signal a second PWM signal; a first latch' for responding to the first PWM signal and a clock signal to generate the buck PWM control signal; and a second lock for responding to the first The PWM signal and the clock signal are used to generate the boost PWM control signal. 10. The multiphase non-inverting buck-boost voltage converter of claim i, wherein the common voltage error provided to each of the plurality of buck-boost mode control circuits provides a current between the plurality of phases balance. 11. A method for controlling a multiphase non-inverting buck-boost voltage converter, comprising the steps of: ???a plurality of input voltages corresponding to a buck-boost conversion associated with a respective phase Generating an adjusted output voltage; monitoring an input current of each of the buck-boost converters; generating a current sensing signal for each of the buck-boost converters; responding to an error voltage and the buck-boost a current sense signal associated with the converter to control each buck-boost voltage converter to utilize peak current mode control in a buck mode of operation and to utilize valley current mode control in a boost mode of operation; responsive to A common error voltage between each of the buck-boost converters and the current sense signal of the buck-boost converter provides current balancing between each of the plurality of 20120232 buck-boost converters. 12. The method of claim n, further comprising the step of generating the error voltage in response to the adjusted turn-on voltage and a reference voltage. 13. The method of claim 11, wherein the step of controlling further comprises the steps of: generating a buck PWM control signal in response to a maximum duty cycle detection signal, an error voltage, and a compensation voltage; The buck PWM control signal and a mode signal are responsive to generate a buck switch transistor control signal on the one side and a buck switch transistor control signal on the low side. 14. The method of claim 13, wherein the step of controlling in a boost operating mode further comprises the steps of: detecting a signal, an error voltage, and a compensation in response to a maximum duty cycle Μ voltage to generate a boost PWM control signal; responsive to the boost PWM control signal and the mode signal to generate a high side boost switch transistor control signal and a low side boost switch transistor control signal; The maximum duty cycle detection signal and the mode signal are generated in response to the buck PWM control signal and the boost pWM control signal. 15. The method of claim 14, further comprising the step of generating the compensation voltage 'in response to the mode signal in a first state', the compensation signal comprising the monitored input current, a step-down a mode offset signal and a buck mode slope compensation signal, and responsive to the mode signal of the second state at 40 201223110, the compensation signal includes the monitored wheeling current, a boost mode offset signal, and a Boost mode slope compensation signal. The method of claim 15, wherein the step of generating the compensation voltage further comprises the steps of: summing the monitored wheeling current, the buck mode offset signal, and the buck mode a slope compensation signal to generate a step-down voltage compensation signal; summing the monitored input current, the boost mode offset signal, and the boost mode slope compensation signal to generate a boost voltage compensation signal; responsive to the mode signal The first state or the second state is selected as the voltage compensation signal between the step-down voltage compensation signal and the boost voltage compensation signal. 17. The method of claim 14, wherein the generating the maximum duty cycle detection signal and the mode signal further comprises the steps of: detecting a maximum in response to the buck PWM signal and the boosting pwM signal a duty cycle condition; generating a maximum duty cycle detection signal in response to the maximum duty cycle condition detected by the delta; and responding to the maximum duty cycle debt signal and a clock signal to generate a formula 'The mode signal indicates the operation in one of the boost mode of operation and the S-th step-down mode of operation. 18. The method of claim 14, wherein the step of generating the buck PWM control signal and the boosting pWM control signal further includes 41 201223110 comprising the steps of: comparing the error voltage to the compensation voltage and responding to the error a voltage and the compensation voltage to generate a PWM signal; responsive to the PWM signal and the maximum duty cycle detection signal to generate a first PWM signal and a second pwiV [signal; responsive to the first PWM signal and a clock Signaling to generate the buck PWM control signal; and providing a second latch for responding to the second PWM signal and the clock signal to generate the boost PWM control signal. 19. The method of claim 11, wherein the step of controlling further comprises the steps of: comparing the error voltage to the compensation voltage and responsive to the error voltage and the compensation voltage to generate a PWM signal; responsive to s-hai PWM And the maximum duty cycle detection signal to generate a first PWM signal and a second PWM signal; generating the buck PWM control signal in response to the first PWM signal and a clock signal; and in response to the The PWM signal and the clock signal are used to generate the boost PWM control signal. 20. The method of claim 11, wherein the step of providing current balancing further comprises comparing a common voltage error associated with each phase of the phases of the buck-boost voltage converter and the buck-boost converter The step of the current sensing signal for each phase. 42