200952086 九、發明說明： 【發明所屬之技術領域】 • 本發明涉及一種薄膜電晶體的製備方法，尤其涉及一 •種基於奈米碳管的薄膜電晶體的製備方法。 【先前技術】 薄膜電晶體（Thin Film Transistor, TFT )係現代微電 子技術中的一種關鍵性電子元件，目前已經被廣泛的應用 於平板顯示器等領域。薄膜電晶體主要包括閘極、絕緣層、 半導體層、源極和汲極。其中，源極和汲極間隔設置並與 半導體層電連接，閘極通過絕緣層與半導體層及源極和汲 極間隔絕緣設置。所述半導體層位於所述源極和汲極之間 的區域形成一通道區域。薄膜電晶體中的閘極、源極、汲 極均由導電材料構成，該導電材料一般爲金屬或合金。當 於閘極上施加一電壓時，與閘極通過絕緣層間隔設置的半 導體層中的通道區域會積累載子，當載子積累到一定程 ❹度’與半導體層電連接的源極汲極之間將導通，從而有電 流從源極流向汲極。於實際應用中，對薄膜電晶體的要求 係希望得到較大的開關電流比。影響上述開關電流比的因 素除薄膜電晶體的製備工藝外，薄膜電晶體半導體層中半 導體材料的載子移動率爲影響開關電流比的最重要的影響 因素之一。 先前技術中’薄膜電晶體中形成半導體層的材料爲非 晶石夕、多晶矽或有機半導體聚合物等（R E L Schr〇pp，B Stannowski, J. K. Rath, New challenges in thin film 6 200952086 transistor research, Journal of Non-Crystalline Solids, 299-302, 1304-1310 (20〇2))。以非晶矽作爲半導體層的非 晶石夕薄膜電晶體的製造技術較爲成熟，但於非晶;δ夕薄膜電 晶體中，由於半導體層中通常含有大量的懸挂鍵，使得载 子的移動率很低（一般小於lcm2V-is-i)，從而導致薄膜電 晶體的響應速度較慢。以多晶矽作爲半導體層的薄膜電晶 體相對於以非晶矽作爲半導體層的薄膜電晶體，具有較高 o200952086 IX. Description of the Invention: [Technical Field] The present invention relates to a method for preparing a thin film transistor, and more particularly to a method for preparing a thin film transistor based on a carbon nanotube. [Prior Art] Thin Film Transistor (TFT) is a key electronic component in modern microelectronics technology and has been widely used in flat panel displays and the like. The thin film transistor mainly includes a gate, an insulating layer, a semiconductor layer, a source, and a drain. Wherein, the source and the drain are spaced apart from each other and electrically connected to the semiconductor layer, and the gate is insulated from the semiconductor layer and the source and the drain by an insulating layer. The semiconductor layer is located in a region between the source and the drain to form a channel region. The gate, source, and drain of the thin film transistor are each composed of a conductive material, which is typically a metal or an alloy. When a voltage is applied to the gate, the channel region in the semiconductor layer spaced apart from the gate through the insulating layer accumulates carriers, and when the carrier accumulates to a certain extent, the source is electrically connected to the semiconductor layer. The current will be turned on so that current flows from the source to the drain. In practical applications, the requirements for thin film transistors are expected to result in a larger switching current ratio. Factors affecting the above-mentioned switching current ratio In addition to the preparation process of the thin film transistor, the carrier mobility of the semiconductor material in the thin film transistor semiconductor layer is one of the most important factors affecting the switching current ratio. In the prior art, the material for forming a semiconductor layer in a thin film transistor is amorphous, polycrystalline germanium or an organic semiconductor polymer (REL Schr〇pp, B Stannowski, JK Rath, New challenges in thin film 6 200952086 transistor research, Journal of Non-Crystalline Solids, 299-302, 1304-1310 (20〇2)). The fabrication technology of amorphous Aussie thin film transistor with amorphous germanium as a semiconductor layer is relatively mature, but in amorphous; delta-shaped thin film transistor, since the semiconductor layer usually contains a large number of dangling bonds, the carrier is moved. The rate is very low (generally less than lcm2V-is-i), resulting in a slower response of the thin film transistor. A thin film transistor having a polycrystalline germanium as a semiconductor layer has a higher affinity with respect to a thin film transistor having an amorphous germanium as a semiconductor layer.
的載子移動率（一般約爲lOcn^V^s·1)，故響應速度也較 快。但多晶矽薄膜電晶體低溫製造成本較高，方法較複雜， 大面積製造困難，且多晶矽薄膜電晶體的關態電流較大。 相較於上述傳統的無機薄膜電晶體，採用有機半導體聚合 物做半導體層的有機薄膜電晶體具有成本低、製造溫度低 的優點，且有機薄膜電晶體具有較高的柔韌性。但由於有 機半導體於常溫下多爲跳躍式料，表現出較高的電阻 率、較低的載子移動率，使得有機薄臈電 較慢。 《源迷度 奈米碳管具有優異的力學及電學性能。並且， 来碳管螺旋方式的變化，奈米碳管可呈現出金屬 ^ 體=。半導體性的奈米碳管具有較高的載子移動率^一般 :達麵〜测⑽⑽叫，係製備晶體 先前技術中已有報道採用半導體性奈米碳管形成 層作爲薄膜電晶體的半導體層:厌e 法主要自括以下㈣ 疋溽犋電晶體的製備方 法主要。括以下步驟：將奈米碳管粉末 中丨通過喷墨打印的方法將太 於有機洛劑 万击將不未碳官與有機溶劑的混合液 7 200952086 ^印在絕緣基板± ’待有機溶劑揮發後，在絕緣基板的預 疋位置上形成-奈米碳管層；通過沈積及钱刻金屬薄膜的 方法在不米碳管層上形成源極及没極；在奈米碳管層上沈 •積-層氮化㈣成-絕緣層；及在絕緣層上沈積—金 膜形成閘極。然而’在上述方法中，奈米碳管需要通過有 機溶劑進行分散，奈米碳管易圏聚，在半導體層中無法均 勻分布。且分散奈米碳管所用的有機溶劑易殘留在奈米碳 管層中，影響薄膜電晶體的性能。並且，在上述奈米碳管 〇層中，奈米碳管隨機分布。載子在上述無序奈米碳管層中 的傳導路徑較長，故上述奈米碳管層中奈米碳管的排列方 式不能使奈米碳管的高載子移動率得到有效利用，進而不 利於獲得具有較高載子移動率的薄膜電晶體。另外，有機 溶劑結合的奈米碳管層結構鬆散，柔韌性差’不利於製備 柔性的薄膜電晶體。 有鑒於此，提供一種方法簡單、適於低成本大量生産 ❹的薄膜電晶體的製備方法實為必要，且所製備的薄膜電晶 體具有較高的載子移動率，較高的響應速度，及較好的柔 韌性。 【發明内容】 一種薄膜電晶體的製備方法，包括以下步驟：提供一 絕緣基底’·形成一奈米碳管層於所述絕緣基底表面，所述 奈米碳管層包括多個奈米碳管，進而形成一半導體層；間 隔形成一源極及一汲極於所述半導體層表面，並使該源極 及汲極與上述半導體層中的部分奈米碳管的兩端電連接； 8 200952086 形成一絕緣層於所述形成有源極和没極的半導體層表面. 及形成一閘極於所述絕緣層表面，得到一薄膜電晶體。 • 一種薄膜電晶體的製備方法，包括以下步驟：提供一 •生長基底；形成一奈米碳管層於所述生長基底表面，所述 奈米碳管層包括多個奈米碳管；提供一絕緣基底；形成一 閘極於所述絕緣基底表面；形成一絕緣層覆蓋所述閘極； 轉印該奈米碳管層至所述絕緣層表面，形成一半導體層； 及間隔形成一源極及一汲極，並使該源極及汲極與上述半 導體層中的部分奈米碳管的兩端電連接，形成一薄膜電晶 體。 、曰 一種薄膜電晶體的製備方法，包括以下步驟：提供一 絕緣基底；在絕緣基底表面均勻形成多個奈米碳管層，所 述奈米碳管層包括多個奈米碳管，進而形成多個半導體 層；間隔形成多個源極及多個汲極，並使上述每一半導體 層中的。卩分奈米碳管的兩端均與一源極及一沒極電連接； ❹形成絕緣層於每一半導體層表面；形成一閘極於每一絕 緣層表面’得到多個薄膜電晶體。 相較於先前技術，本技術方案實施例提供的薄膜電晶 體的製備方法具有以下優點：其一，由於所述半導體層可 直接形成在所述絕緣基底上，或通過對形成在所述生長基 ，上的奈米碳管陣列進行倒扣處理而製備，該方法較爲簡 早。其二’所製備的奈米碳管層+的奈米碳管之間沿一定 方向平行排列，故將該奈米碳管層作爲半導體層時，可以 t迻控制奈米碳官層的設置方向來控制源極至汲極間奈米 9 200952086 反5的排列方向’從而使薄膜電晶體獲得較大的載子移動 率，進而有利於提高薄膜電晶體的響應速度。 '【實施方式】 & . 以下將結合附圖詳細說明本技術方案實施例提供的'薄 膜電晶體的製備方法。 、# 請參閱圖1及圖2,本技術方案第一實施例提供 頂閘型薄膜電晶體10的製備方法，具體包括以下步驟： 步驟一：提供一絕緣基底11〇。 〇 所述絕緣基底110爲一耐高溫基板，其材料不限，只 要確保其溶點高於所述奈米碳管的生長溫度即可。所述絕 緣基底110的形狀不限，可爲方形、圓形等任何形狀。所 述絕緣基底110的大小尺寸不限，具體可根據實際情况而 定。另外，所述絕緣基底110也可選用大規模集成電路中 的基板。 本技術方案實施例中，所述絕緣基底110爲一方形矽 ❹基底’該石夕基底的長度和寬度均爲3厘米。 步驟二：形成一奈米碳管層於所述絕緣基底ιι〇表 面，所述奈米碳管層包括多個奈米碳管，進而形成一半導 體層140。 所述奈米碳管層可通過以下兩種方法形成：其一，在 所述絕緣基底110上形成一奈米碳管陣列，及處理所述奈 来碳管陣列，形成一奈米碳管層。其二，直接在所述絕= 基底110表面形成一奈米碳管層。 所述在絕緣基底110上形成一奈米碳管陣列，及處理 200952086 所述奈米碳管陣列，形成一奈米碳管層的步驟包括以下步 •驟··在所述絕緣基底表面形成一帶狀催化劑薄膜，該 •帶狀催化劑薄膜的寬度爲i微米〜2〇微米；採用化學氣相 積法生長一帶狀奈米碳管陣列；及處理所述帶狀奈米碳 管陣列，使所述帶狀奈米碳管陣列沿垂直於其長度的方向 傾倒，在絕緣基底110表面形成一奈米碳管層。 所述帶狀催化劑薄膜用於生長奈米碳管。該帶狀催化 ❹f薄膜的材料可選用鐵（⑷、銘（C〇)i (Ni)或其任 合金之一。本實施例中，所述帶狀催化劑薄膜的 所述帶狀催化劑薄膜可通過熱沈積法、電子束沈積法 形成於所述絕緣基底110表面。所述帶狀催化劑 f爲1微米〜2〇微米。所述帶狀催化劑薄膜的厚 度爲0.1奈米〜;[〇奈米。 色、去具用化學氣相沈積法生長帶狀奈米碳管陣列的方 ❹在具體包括以下步驟： 入 將上述形成有所述帶狀催化劑薄膜的絕緣基底110放 反應室中； - 通入保護氣體，將反應室内的空氣排出； 保持^護氣體環境下將反應室加熱至6〇〇t〜9_，並 分鐘通St爲B〜1:3的碳源氣及载氣，反應5〜 趨生長奈米碳管；及 停止通入碳源氣，奈米碳管停止生長，同時停止加熱， 11 200952086 並降溫，待降至室溫後，蔣 緣基底m)從反應室尹取=成有帶狀奈米碳管陣列的絕 ••所述保賴體錢氣或餘氣體。所述碳源氣可選用 都々E 、乙稀等化學性質較活潑的碳氫化合物。所述 載氣爲風氣。通入瑞源齑认泣 ..,Λ ,ηη 及/原巩的流量爲2〇〜20〇Sccm，載氣的流 佯n rem。在所述停切人碳源氣後，要繼續通入 =化直到反應室溫度降爲室温，以防止生長的奈米 及摩财所述保護氣體爲氬氣，碳源氣爲乙快， 度爲峨，奈米碳管的生長時間爲60分鐘。 另外’可料調節碳源氣和減㈣量比 =;=的性如管徑、透明度、電阻等。= 疗方案實轭例中，當所述碳源氣和載 至10:100時，可生县屮罝辟太业*咕 里吣舄himj μ 管。當繼續增大碳源氣 ❹ 乎:管陳❹可生長出雙壁奈米碳管。故所形成的帶狀奈 管可爲單壁奈米碳管或雙壁奈来碳 官該早壁不未石厌管的直徑爲0.5奈米〜5〇夺米， 奈米碳管的直捏爲U奈米〜5。奈米。優選二= 碳管的直徑小於1〇奈米。 斤这不未 生條件下，所述帶狀奈米碳管陣列的生長高度隨 2長而增大。所述帶狀奈米碳管陣列的生長高 ί及截"ί 毫米。本技術方案實施例中，通入碳源 反應60分鐘，所生長出的帶狀奈米碳管陣列的 回度爲1毫米〜2毫米。 12 200952086 形成==: =管陣列爲由多個長度較長的奈米碳管 溫度，“:陣列。通過上述控制生長條件’如生長 反心、氧和载氣的流量比等 的奈米碳管Λ太尤人士 狀不木石厌管陣列中 金屬顆粒等? 3有雜質，如無定型碳或殘留的摧化劑 :述處理帶狀奈米碳管陣列，形成奈米 ^通過以下三種方式實現：其―，採 ^ 理所述帶狀奈米碳管陣列，形成一奈米碳管層齊η 用機，外力處理法處理所述帶狀奈米碳管陣列，形成一奈 層。其三’使用氣流處理法處理所述帶狀奈米碳 陣列，形成一奈米碳管層。 鲁 、所述採用有機溶劑處理法處理所述奈米碳管陣列，形 成奈米碳官層的方法具體包括以下步驟：提供一盛有有 機/谷齊丨的各器，將形成有帶狀奈米碳管陣列的絕緣基底 U0次入盛有有機溶劑的容器中；及將所述絕緣基底U0 ^垂直於所述帶狀奈米碳管陣列的長度方向從有機溶劑中 取出，所述奈米碳管陣列在有機溶劑表面張力的作用下傾 倒，黏附在所述絕緣基底110表面；使有機溶劑揮發，形 成一奈米碳管層。所述有機溶劑可選用揮發性有機溶劑， 如乙醇、甲醇、丙酮、二氯乙烷或氣仿，本實施例中採用 乙醇。所形成的奈米碳管層在揮發性有機溶劑的表面張力 的作用下，可貼附在所述基底表面，且表面體積比减小， 點性降低，具有良好的機械强度及韌性。 所述使用機械外力處理法處理所述帶狀奈米破管陣 13 200952086 列，形成一奈米碳管層的方法具體包括以下步驟··提供一 •壓頭；及將該壓頭沿垂直於所述帶狀奈米碳管陣列的長度 '方向碾壓所述帶狀奈米碳管陣列，奈米碳管沿垂直於所述 .帶狀奈米石炭管陣列的長度#向傾倒，形成一奈米碳管層。 所述壓頭爲滾軸狀壓頭。所述機械外力的施加裝置不限於 上述壓頭，也可爲一具有一定平整表面的其它裝置，只要 旎使所述帶狀奈米碳管陣列中的奈米碳管沿垂直於所述帶 狀奈米碳管陣列的長度方向傾倒即可。在壓力的作用下， 所述帶狀奈米碳管陣列可與生長的基底分離’從而形成由 多個奈米碳管組成的具有自支撑結構的奈米碳管層。 所述使用氣流處理法處理所述帶狀奈米碳管陣列，形 成一奈米碳管層的方法具體包括以下步驟：提供一風機， 該風機可産生一軋流，及將該風機沿垂直於所述帶狀奈米 碳管陣列的長度方向施加一氣流於所述帶狀奈米碳管陣 列，奈米碳管沿垂直於所述帶狀奈米碳管陣列的長度方向 ❹傾倒，形成一奈求碳管層。所述氣流的施加裝置不限於上 述風機，可爲任何可産生氣流的裝置。 本實施例中，所述奈米碳管層的密度與上述帶狀催化 劑薄膜的寬度有關。所述帶狀催化劑薄膜的寬度越大，所 製備的奈米碳管層的密度則越大；反之，所述帶狀催化劑 薄膜的寬度越小，所製備的奈米碳管層的密度則越小。可 以理解，通過控制帶狀催化劑薄膜的寬度，即可控制所製 備的奈米碳管層的密度。 可以理解，由於上述奈米碳管的生長溫度較高，故上 200952086 = 的材料必須選用耐高溫的硬性材料，從而 廣'乏的：麻純的選擇。爲使該薄臈電晶體10能够採用更 基底材料，尤其爲一柔性基底材料，從而形成一柔 ❹ ❹ =膜電晶體Η)’在生長奈米碳管層後可以進—步通過一 :步驟’將該奈米碳管層轉印在其它基底上。具體地， ::印步驟包括以下步驟:首先，提供一轉印基底;其次， 卜成有奈米碳管層的絕緣基底110倒扣在該轉印基底 t ’使不米碳管層表面與轉印基底表面接觸，從而形成一 人i括絕緣基底110、奈米碳管層及轉印基底 ::層：構，再次’熱壓該三層結構；最後，移去絕緣基 -10從而使上述奈米碳管層黏附於所述轉印基底表面。 “轉卩基底的材料爲—柔性材料，如塑料或樹脂材料 等。本實施例中’該轉印基底爲一 PET薄膜。熱壓的溫度 及時間取决於所述轉印基底的材料種類。當該轉印基底的 材料爲-塑料或樹脂時’熱壓溫度爲50〜200oc，熱壓時間 爲5〜30分鐘。通過熱壓步驟，奈米碳管與轉印基底表面 的結:更爲緊密’從而能够容易地與絕緣基底⑽分離。 月參見圖3所製備的奈米碳管層包括多個擇優取向 排列的奈米碳管。所述奈米碳管層中的多個奈米碳管具有 大致相等的長度。優選地，所述奈米碳管潛中的多個夺米 碳管相互平行。 ” μ 所述直接在絕緣基底11G表面形成—奈米碳管層的步 驟具體包括以下步驟：提供一生長基底，該生長基底表面 形成有-單分散性催化劑層；將所述生長基底和絕緣基底 15 200952086 110放入一反應室中，且使所述生長基底和絕緣基底11〇 間隔設置，在保護氣體環境下加熱到奈米碳管的生長溫 *度，通入碳源氣’沿著氣流的方向生長奈米碳管，在所述 '絕緣基底110表面形成一奈米碳管薄膜，進而形成一奈米 碳管層。 Μ 所述催化劑的材料可爲鐵、鈷、鎳或其任意組合的合 金材料，或金屬鹽的單分散性溶液或者金屬的單分散性溶 液。當選用鐵、鈷、鎳或其任意組合的合金材料製備單分 ❹散性催化劑層時，可採用沈積方法將催化劑材料沈積到生 長基底表面；當選用金屬鹽的單分散性溶液或者金屬的單 分散性溶液製備單分散性催化劑層，可將金屬鹽或者金屬 的單分散性溶液塗敷於生長基底上，烘乾後即形成所述催 化劑層。 所述生長基底爲一耐高溫基板，其材料不限，只要確 保其熔點高於所述奈米碳管的生長溫度即可。所述基底形 ❹狀不限，可爲方形、圓形等任何形狀。本技術方案實施例 所述生長基底採用與所述絕緣基底110同樣材料，同樣尺 寸的基底。 所述奈米碳管的生長溫度爲8〇〇〇c〜1〇〇〇°C。當通入碳 源氣後，在生長基底表面催化劑顆粒的作用下開始生長奈 米碳管。奈米碳管一端固定於生長基底上，另一端不斷生 長。由於催化劑層包括多個單分散性催化劑顆粒，所以生 長的奈米碳管不會很密，從而使得部分奈米碳管可以長成 爲長度較長的奈米碳管。將所述碳源氣從靠近生長基底處 200952086 通入’所以隨著碳源氣的不斷通人，生長的奈米碳管隨著 .碳源氣漂浮於絕緣基底110上空。該生長機理稱作“放風 ‘箏機理”。奈米碳管的生長時間與所要製備的奈米碳管的 .長度有關。本實施例中，生長時間爲30分鐘時’所生長出 的奈=碳管的長度可達8厘米。當停止通入碳源氣，奈米 碳管停^生長’平行且間隔的形成於絕緣基底11〇上，形 成-奈米碳管薄膜。該奈米碳管薄膜中相鄰兩個奈来碳管 之間的距離大於20微米。 ^ 步地，爲了提高所生長出的奈米碳管薄膜中奈米 碳官的密度，可通過更換新的生長基底或將原生長基底取 出清洗後沈積新的催化劑薄膜的方式來實現奈米碳管的多 Y欠生長，形成多個奈米碳管薄膜，進而提高所生長出的奈 米碳管薄膜的密度，所述多個奈米碳管薄膜形成一奈来碳 e層另外，在上述奈米碳管的多次生長中，也可將所述 絕緣基底110旋轉一定角度，從而使相鄰兩層奈米碳管薄 ❹膜中的奈米碳管之間具有一交叉角度α，α大於等於〇度 且小於等於90度。所述奈米碳管層包括多個奈米碳管，且 奈米碳管之間通過凡德瓦爾力緊密結合形成一自支撑結 構。 另外’當所製備的奈米碳管層的面積較大時，或當需 要製備多個薄膜電晶體1〇時，可將所形成的奈米碳管層蝕 刻成多個具有所需形狀和尺寸的奈米碳管層，該奈米碳管 層用作半導體層14〇。所述蝕刻方法不限，可爲先前技術 中任何蝕刻方法。 17 200952086 一汲極152，並使該 140中的部分奈米碳 步驟三：間隔形成一源極11及 源極151及沒極152與上述半導體層 管的兩端電連接。 ❹The carrier mobility (usually about lOcn^V^s·1), so the response speed is also faster. However, the low-temperature manufacturing cost of the polycrystalline germanium thin film transistor is relatively complicated, the method is difficult to manufacture in a large area, and the off-state current of the polycrystalline germanium thin film transistor is large. Compared with the above-mentioned conventional inorganic thin film transistor, the organic thin film transistor using the organic semiconductor polymer as the semiconductor layer has the advantages of low cost and low manufacturing temperature, and the organic thin film transistor has high flexibility. However, since organic semiconductors are mostly skip-type materials at normal temperature, they exhibit higher resistivity and lower carrier mobility, making organic thin tantalum electricity slower. "Sources of carbon nanotubes have excellent mechanical and electrical properties. Moreover, the change of the carbon tube spiral mode, the carbon nanotubes can exhibit the metal body =. Semiconducting carbon nanotubes have a high carrier mobility. General: Datum ~ Measure (10) (10) is called crystal preparation. The prior art has reported the use of a semiconducting carbon nanotube to form a semiconductor layer of a thin film transistor. The anatomy method mainly includes the following (4) The preparation method of the 疋溽犋 transistor is mainly. The following steps are included: the method of inkjet printing in the carbon nanotube powder will be too much in the organic agent, and the mixture of the carbon and the organic solvent will be printed on the insulating substrate. Thereafter, a carbon nanotube layer is formed on the pre-twisted position of the insulating substrate; a source and a finite electrode are formed on the carbon nanotube layer by deposition and etching of the metal thin film; sinking on the carbon nanotube layer The product-layer nitride (four) is formed into an insulating layer; and deposited on the insulating layer - a gold film forms a gate. However, in the above method, the carbon nanotubes need to be dispersed by an organic solvent, and the carbon nanotubes are easily condensed and cannot be uniformly distributed in the semiconductor layer. Moreover, the organic solvent used for dispersing the carbon nanotubes tends to remain in the carbon nanotube layer, affecting the performance of the thin film transistor. Further, in the above carbon nanotube layer, the carbon nanotubes are randomly distributed. The carrier has a long conduction path in the disordered carbon nanotube layer. Therefore, the arrangement of the carbon nanotubes in the carbon nanotube layer cannot effectively utilize the high carrier mobility of the carbon nanotube. It is not conducive to obtaining a thin film transistor with a high carrier mobility. In addition, the organic solvent-bonded carbon nanotube layer has a loose structure and poor flexibility, which is disadvantageous for the preparation of a flexible thin film transistor. In view of the above, it is necessary to provide a method for preparing a thin film transistor which is simple in method and suitable for mass production of germanium at a low cost, and the prepared thin film transistor has high carrier mobility, high response speed, and Better flexibility. SUMMARY OF THE INVENTION A method for preparing a thin film transistor includes the steps of: providing an insulating substrate' forming a carbon nanotube layer on a surface of the insulating substrate, the carbon nanotube layer comprising a plurality of carbon nanotubes Forming a semiconductor layer; forming a source and a drain on the surface of the semiconductor layer, and electrically connecting the source and the drain to both ends of the carbon nanotube in the semiconductor layer; 8 200952086 An insulating layer is formed on the surface of the semiconductor layer on which the source and the gate are formed, and a gate is formed on the surface of the insulating layer to obtain a thin film transistor. A method of preparing a thin film transistor, comprising the steps of: providing a growth substrate; forming a carbon nanotube layer on the surface of the growth substrate, the carbon nanotube layer comprising a plurality of carbon nanotubes; providing a An insulating substrate; forming a gate on the surface of the insulating substrate; forming an insulating layer covering the gate; transferring the carbon nanotube layer to the surface of the insulating layer to form a semiconductor layer; and forming a source by spacing And a drain electrode, and the source and the drain are electrically connected to both ends of a part of the carbon nanotubes in the semiconductor layer to form a thin film transistor. The method for preparing a thin film transistor comprises the steps of: providing an insulating substrate; uniformly forming a plurality of carbon nanotube layers on the surface of the insulating substrate, wherein the carbon nanotube layer comprises a plurality of carbon nanotubes, thereby forming a plurality of semiconductor layers; a plurality of sources and a plurality of drains are formed at intervals, and are formed in each of the semiconductor layers. Both ends of the carbon nanotubes are electrically connected to a source and a gate; an insulating layer is formed on the surface of each of the semiconductor layers; and a gate is formed on the surface of each of the insulating layers to obtain a plurality of thin film transistors. Compared with the prior art, the method for preparing a thin film transistor provided by the embodiments of the present technical solution has the following advantages: first, since the semiconductor layer can be directly formed on the insulating substrate, or formed by the pair on the growth substrate The carbon nanotube array is prepared by reverse folding treatment, and the method is relatively simple. The carbon nanotubes of the carbon nanotube layer prepared by the second two are arranged in parallel in a certain direction. Therefore, when the carbon nanotube layer is used as a semiconductor layer, the direction of the arrangement of the nanocarbon layer can be controlled by t shift. To control the direction of the source-to-bunga nano 9 200952086 anti-5, so that the thin film transistor obtains a large carrier mobility, which in turn helps to improve the response speed of the thin film transistor. '[Embodiment] & The method for preparing a thin film transistor according to an embodiment of the present technical solution will be described in detail below with reference to the accompanying drawings. Referring to FIG. 1 and FIG. 2, the first embodiment of the present invention provides a method for preparing a top gate type thin film transistor 10, which specifically includes the following steps: Step 1: An insulating substrate 11 is provided.绝缘 The insulating substrate 110 is a high temperature resistant substrate, and the material thereof is not limited, as long as the melting point thereof is higher than the growth temperature of the carbon nanotubes. The shape of the insulating substrate 110 is not limited and may be any shape such as a square shape, a circular shape, or the like. The size of the insulating substrate 110 is not limited, and may be determined according to actual conditions. In addition, the insulating substrate 110 may also be a substrate in a large scale integrated circuit. In the embodiment of the technical solution, the insulating substrate 110 is a square 矽 substrate. The length and width of the slab substrate are both 3 cm. Step 2: forming a carbon nanotube layer on the surface of the insulating substrate, wherein the carbon nanotube layer comprises a plurality of carbon nanotubes, thereby forming a half conductor layer 140. The carbon nanotube layer can be formed by the following two methods: First, forming a carbon nanotube array on the insulating substrate 110, and processing the carbon nanotube array to form a carbon nanotube layer . Second, a carbon nanotube layer is formed directly on the surface of the substrate 110. Forming a carbon nanotube array on the insulating substrate 110, and processing the carbon nanotube array of 200952086, forming a carbon nanotube layer comprises the following steps: forming a surface on the surface of the insulating substrate a strip catalyst film having a width of i μm to 2 μm; a chemical vapor deposition method for growing a ribbon carbon nanotube array; and processing the ribbon carbon nanotube array to The ribbon-shaped carbon nanotube array is poured in a direction perpendicular to its length to form a carbon nanotube layer on the surface of the insulating substrate 110. The strip catalyst film is used to grow a carbon nanotube. The material of the strip-shaped catalytic ❹f film may be one of iron ((4), Ming (C〇)i (Ni) or any of its alloys. In this embodiment, the strip catalyst film of the strip catalyst film may pass A thermal deposition method or an electron beam deposition method is formed on the surface of the insulating substrate 110. The strip catalyst f is 1 μm to 2 μm. The thickness of the strip catalyst film is 0.1 nm~; [〇奈米. The method for growing a ribbon-shaped carbon nanotube array by chemical vapor deposition comprises the following steps: inserting the insulating substrate 110 having the strip-shaped catalyst film formed thereon into a reaction chamber; Protect the gas, discharge the air in the reaction chamber; keep the reaction chamber heated to 6〇〇t~9_ in the atmosphere of the gas, and pass the carbon source gas and carrier gas of B~1:3 in minutes, the reaction is 5~ Growing carbon nanotubes; and stopping the introduction of carbon source gas, the carbon nanotubes stop growing, and stop heating, 11 200952086 and cooling, after cooling to room temperature, the edge of the Jiang margin m) from the reaction chamber Yin = Yes The ribbon-shaped carbon nanotube array is absolutely necessary to save money or residual gas. . The carbon source gas may be selected from the chemically active hydrocarbons such as toluene E and ethylene. The carrier gas is an atmosphere. Passing into the source of Ruiyuan 齑.., Λ, ηη and / original Gong flow is 2〇~20〇Sccm, the flow of the carrier gas 佯n rem. After the carbon source gas is stopped, the heating is continued until the temperature of the reaction chamber is lowered to room temperature, so as to prevent the growth of the protective gas of nano and Mocha from being argon, and the carbon source gas is fast. For 峨, the growth time of the carbon nanotubes is 60 minutes. In addition, the amount of carbon source gas and the amount of minus (four) can be adjusted; the properties such as pipe diameter, transparency, and electrical resistance. = In the yoke example of the treatment plan, when the carbon source gas is loaded to 10:100, the county can be used to produce the Taiji*咕里吣舄himj μ tube. When you continue to increase the carbon source gas, you can grow double-walled carbon nanotubes. Therefore, the formed ribbon tube can be a single-walled carbon nanotube or a double-walled carbon nanotube. The diameter of the early wall is not 0.5 〇 〇 , , , , , , , , , , , , , For U Nano ~ 5. Nano. Preferably, the diameter of the carbon tube is less than 1 nanometer. The growth height of the ribbon-shaped carbon nanotube array increases with the length of the tube under the condition of no sufficiency. The ribbon-shaped carbon nanotube array has a high growth and a truncated " In the embodiment of the technical solution, the carbon source is reacted for 60 minutes, and the growth of the ribbon-shaped carbon nanotube array is 1 mm to 2 mm. 12 200952086 Formation ==: = tube array is composed of a plurality of long carbon nanotube temperatures, ": array. Through the above control growth conditions" such as growth of anti-heart, oxygen and carrier gas flow ratio, etc. Pipes are too special for people like wood and anaerobic metal particles in the array? 3 There are impurities, such as amorphous carbon or residual catalyzing agent: the treatment of ribbon-shaped carbon nanotube arrays, forming nanometer ^ through the following three ways : ―, the strip-shaped carbon nanotube array is taken to form a carbon nanotube layer η machine, and the strip-shaped carbon nanotube array is processed by an external force treatment method to form a naphthalene layer. 'Using a gas flow treatment method to treat the ribbon-shaped nanocarbon array to form a carbon nanotube layer. Lu, the method for treating the carbon nanotube array by an organic solvent treatment method to form a nano-carbon layer The method comprises the steps of: providing an organic/valley-containing device, inserting an insulating substrate U0 formed with a ribbon-shaped carbon nanotube array into a container containing an organic solvent; and vertically locating the insulating substrate U0 ^ From the length direction of the strip of carbon nanotube array The solvent is taken out, and the carbon nanotube array is poured under the surface tension of the organic solvent to adhere to the surface of the insulating substrate 110; the organic solvent is volatilized to form a carbon nanotube layer. The organic solvent may be volatilized. An organic solvent, such as ethanol, methanol, acetone, dichloroethane or gas, in the present embodiment, ethanol is used. The formed carbon nanotube layer can be attached to the surface tension of the volatile organic solvent. The surface of the substrate has a reduced surface to volume ratio, reduced dot properties, and good mechanical strength and toughness. The mechanically external force treatment process is used to treat the strip-shaped nano-barrel array 13 200952086 column to form a nano carbon. The method of the tube layer specifically includes the following steps: providing an indenter; and rolling the strip of carbon nanotube arrays in a direction perpendicular to the length of the strip of carbon nanotube arrays, The carbon nanotubes are poured along a length # perpendicular to the length of the strip-shaped carbon nanotube array to form a carbon nanotube layer. The indenter is a roller-shaped indenter. The mechanical external force application device is not limited Above head It can also be a device having a certain flat surface, as long as the carbon nanotubes in the array of the carbon nanotubes are tilted in a direction perpendicular to the length of the array of the carbon nanotubes. Under the action of pressure, the array of ribbon-shaped carbon nanotubes can be separated from the grown substrate to form a carbon nanotube layer having a self-supporting structure composed of a plurality of carbon nanotubes. The method for forming a carbon nanotube layer of the strip-shaped carbon nanotube array comprises the following steps: providing a fan, the fan generating a rolling flow, and directing the fan along the strip-shaped carbon nanocarbon A flow of gas is applied to the array of strip-shaped carbon nanotubes in the longitudinal direction of the tube array, and the carbon nanotubes are poured down along the length direction perpendicular to the array of the strip-shaped carbon nanotube tubes to form a carbon nanotube layer. The application device for the air flow is not limited to the above-described fan, and may be any device that can generate an air flow. In this embodiment, the density of the carbon nanotube layer is related to the width of the strip catalyst film. The greater the width of the strip catalyst film, the greater the density of the prepared carbon nanotube layer; conversely, the smaller the width of the strip catalyst film, the higher the density of the prepared carbon nanotube layer. small. It can be understood that by controlling the width of the strip catalyst film, the density of the prepared carbon nanotube layer can be controlled. It can be understood that due to the high growth temperature of the above carbon nanotubes, the material of 200952086 = must use a hard material with high temperature resistance, so that it is widely used: the choice of hemp pure. In order to enable the thin germanium transistor 10 to adopt a more base material, especially a flexible base material, thereby forming a soft ❹ = film transistor Η) ' after the growth of the carbon nanotube layer can be advanced through a step: 'Transfer the carbon nanotube layer on other substrates. Specifically, the step of printing includes the following steps: first, providing a transfer substrate; secondly, insulating the substrate 110 having a layer of carbon nanotubes on the transfer substrate t' such that the surface of the carbon nanotube layer is The surface of the transfer substrate is in contact with each other to form an insulating substrate 110, a carbon nanotube layer and a transfer substrate: a layer: a structure, which is again 'hot pressed against the three-layer structure; finally, the insulating group-10 is removed to thereby make the above A carbon nanotube layer adheres to the surface of the transfer substrate. "The material of the transfer substrate is - a flexible material such as a plastic or a resin material. In the present embodiment, the transfer substrate is a PET film. The temperature and time of hot pressing depend on the material type of the transfer substrate. When the material of the transfer substrate is - plastic or resin, the hot pressing temperature is 50 to 200 oc, and the hot pressing time is 5 to 30 minutes. By the hot pressing step, the junction of the carbon nanotube and the surface of the transfer substrate is closer: 'Therefore, it can be easily separated from the insulating substrate (10). The carbon nanotube layer prepared in accordance with Figure 3 includes a plurality of carbon nanotubes arranged in a preferred orientation. A plurality of carbon nanotubes in the carbon nanotube layer Preferably, the plurality of carbon nanotubes in the latent carbon nanotubes are parallel to each other. The step of forming the carbon nanotube layer directly on the surface of the insulating substrate 11G specifically includes the following steps. Providing a growth substrate having a monodisperse catalyst layer formed on the surface of the growth substrate; placing the growth substrate and the insulating substrate 15 200952086 110 in a reaction chamber, and spacing the growth substrate and the insulating substrate 11 , Heating in a protective gas atmosphere to the growth temperature of the carbon nanotubes, introducing a carbon source gas to grow a carbon nanotube along the direction of the gas flow, forming a carbon nanotube film on the surface of the insulating substrate 110, and further A carbon nanotube layer is formed. The material of the catalyst may be an alloy material of iron, cobalt, nickel or any combination thereof, or a monodisperse solution of a metal salt or a monodisperse solution of a metal. When a single-part bismuth catalyst layer is prepared by using an alloy material of iron, cobalt, nickel or any combination thereof, a deposition method may be used to deposit the catalyst material onto the surface of the growth substrate; when a monodisperse solution of a metal salt or a metal single is selected Dispersion Solution A monodisperse catalyst layer is prepared, and a monodispersity solution of a metal salt or a metal can be applied to a growth substrate, and the catalyst layer is formed after drying. The growth substrate is a high temperature resistant substrate, and the material thereof is not limited as long as the melting point is higher than the growth temperature of the carbon nanotubes. The base shape is not limited and may be any shape such as a square shape or a circular shape. Embodiments of the Technical Solution The growth substrate is made of the same material and the same size as the insulating substrate 110. The growth temperature of the carbon nanotubes is 8 〇〇〇 c 〜 1 〇〇〇 ° C. After the carbon source gas is introduced, the carbon nanotubes are grown under the action of the catalyst particles on the surface of the growth substrate. The carbon nanotube is fixed at one end to the growth substrate and the other end is continuously grown. Since the catalyst layer includes a plurality of monodisperse catalyst particles, the growth of the carbon nanotubes is not so dense that a part of the carbon nanotubes can be grown into a longer length of carbon nanotubes. The carbon source gas is introduced from near the growth substrate 200952086. Therefore, as the carbon source gas continues to pass, the growing carbon nanotubes float with the carbon source gas over the insulating substrate 110. This growth mechanism is called the “wind ‘single mechanism”. The growth time of the carbon nanotubes is related to the length of the carbon nanotubes to be prepared. In the present embodiment, the length of the carbon nanotubes grown by the growth time of 30 minutes was as long as 8 cm. When the introduction of the carbon source gas is stopped, the carbon nanotubes are stopped and grown in parallel and spaced apart on the insulating substrate 11 to form a carbon nanotube film. The distance between two adjacent carbon nanotubes in the carbon nanotube film is greater than 20 microns. ^ Step, in order to increase the density of nanocarbon in the grown carbon nanotube film, nanocarbon can be realized by replacing the new growth substrate or removing the original growth substrate and depositing a new catalyst film after cleaning. The plurality Y of the tube is undergrown to form a plurality of carbon nanotube films, thereby increasing the density of the grown carbon nanotube film, and the plurality of carbon nanotube films form a nano-carbon layer. In the multiple growth of the carbon nanotubes, the insulating substrate 110 can also be rotated by a certain angle, so that the carbon nanotubes in the adjacent two layers of carbon nanotubes have an angle of intersection α, α. It is greater than or equal to the twist and less than or equal to 90 degrees. The carbon nanotube layer comprises a plurality of carbon nanotubes, and the carbon nanotubes are tightly coupled by a van der Waals force to form a self-supporting structure. In addition, when the area of the prepared carbon nanotube layer is large, or when it is required to prepare a plurality of thin film transistors, the formed carbon nanotube layer can be etched into a plurality of shapes and sizes having a desired shape. The carbon nanotube layer is used as the semiconductor layer 14〇. The etching method is not limited and may be any etching method in the prior art. 17 200952086 A drain 152 and a portion of the nanocarbon in the 140 step three: a source 11 and a source 151 and a gate 152 are electrically connected to both ends of the semiconductor layer. ❹
該源極m及沒極152的材料應具有較好的導電性。 具體地’該源極151及汲極152的材料可以爲金屬、合金、 銦錫氧化物（刚、銻錫氧化物（AT〇)、導電銀膠、導電 聚合物及奈米碳㈣膜等導電材料。根據形成源極151及 沒極152的材料種類的不同，可則㈣不时法形成該源 極151及没極152。具體地，當該源極i5i及没極152的 材料爲金屬、合金、IT0或AT0時，可以通過減鍵、減射、 沈積、掩模及蝕刻等方法形成所述源極151及汲極152。 當該源極151及汲極152的材料爲導電銀膠、導電聚合物 或奈米碳管薄料’彳以通過直接黏附或印刷塗敷的方 法將該導電銀膠或奈米碳管薄膜塗敷或黏附於絕緣基底 110或半導體層140表面，形成源極151及汲極152。一般 地，該源極151及汲極152的厚度爲〇5奈米〜1〇〇微米， 源極151至汲極152之間的距離爲jqoo微米。 本實施例中，該源極151及汲極152的材料爲金屬。 上述步驟—具體可通過下述兩種方式進行。第一種方式具 體包括以下步驟：首先，在上述半導體層140表面均勻塗 敷覆一層光刻膠；其次，通過曝光及顯影等光刻方法在光 刻勝上形成源極151及汲極152區域，在該源極151及汲 極152區域露出該半導體層140 ;再次，通過真空濺鍍、 磁控濺射或電子束蒸發沈積等沈積方法在上述光刻膠、源 18 200952086 極151及沒極152區域表面沈積一金制，優選爲鈀、欽 .或鎳金屬層，·最後，通過丙酮等有機溶劑去除光刻膠及其 .‘上的金屬層，即得到形成在所述半導體層140上的源極151 .及汲極152。第二種方式具體包括以下步驟：首先，在半 導體層140表面沈積一金屬層；其次，在該金屬層表面塗 敷-層光刻膠；再次，通過曝光及顯影等光刻方法去除源 極151區域及汲極152區域外的光刻膠；最後，通過電漿 蝕刻等方法去除源極151區域及汲極152區域外的金屬 ❹層，並以丙酮等有機溶劑去除源極151區域及汲極152區 域上的光刻膠，即得到形成在半導體層14〇上的源極151 及汲極152。本實施例中，該源極ι51及汲極152的厚度 爲1微米，源極151至汲極152之間的距離爲5〇微米。 可以理解，爲了得到具有更好的半導體性的半導體層 140，在形成源極151及汲極152之後，可以進一步包括一 去除半導體層140中的導體性奈米碳管的步驟。具體包括 ❾以下步驟：首先，提供一外部電源，其次，將外部電源的 正負兩極連接至源極151及汲極152 ;最後，通過外部電 源在源極151及汲極152兩端施加一較大電邀，使導體性 的奈米碳管發熱並燒蝕，獲得一半導體性的半導體層 140。該電壓在1〜1〇〇〇伏範圍内。 另外’上述去除半導體層140中導體性奈米碳管的方 法也可以使用氫電漿、微波、太赫茲（THz ) '紅外線（ir )、 紫外線（UV)或可見光（Vis )照射該半導體層ι4〇，使導 體性奈米碳管發熱並燒蝕，獲得一半導體性的半導體層 19 200952086 140。 步驟四：在上述半導體層14〇上形成_絕緣層DO。 ❹ 、該絕㈣130的材料可以爲氮切、氧切等硬性材 料或苯並環T烯（BCB)、聚喊丙烯酸樹脂等柔性材料。 根據絕緣層13G的材料種類的不同，可以採用不同方法形 成該絕緣層謂。具體地，當該絕緣層13G的材料爲氮^ 石夕或氧化㈣’可以通過沈積的方法形成絕緣I 13〇。當 該絕緣層謂的材料爲笨並環丁烯(BCB)、聚醋或丙烯： 樹脂時，可以通過印刷塗敷的方法形成絕緣層13〇。一般 地，該絕緣層130的厚度爲〇 5奈米〜1〇〇微米。 本實施方式中採用電製化學氣相沈積等沈積方法形成 一氮化矽絕緣層130覆蓋於半導體層140及形成在半導體 層140上的源極151及汲極152表面。所述絕緣層13〇的 厚度約爲1微米。 可以理解，根據薄膜電晶體1〇的不同應用，可以採用 ❹與形成源極151及汲極152相似的光刻或蝕刻的方法將所 述源極151及汲極152的一部分暴露在絕緣層13()外。 步驟五：形成一閘極120於所述絕緣層13〇表面，得 到一薄膜電晶體1〇。 該問極120的材料應具有較好的導電性。具體地，該 閘極120的材料可以爲金屬、合金、ΙΤ〇、Ατ〇、導電銀膠、 導電聚合物及奈米碳管薄膜等導電材料。該金屬或合金材 料可以爲紹、銅、鎢、鉬、金或其合金。具體地，當該閘 極120的材料爲金屬、合金、ΙΤΟ或ΑΤΟ時，可以通過濺 200952086 鍍、濺射、沈積、掩模及餘刻等方法形成間極i2〇。當該 .閘極ί20的材料爲導電銀膠、導電聚合物或奈米碳管薄膜 時可以通過直接黏附或印刷塗敷的方法形成閑極H .一般地，該閘極120的厚度爲0.5奈米〜1〇〇微米。 本技術方案實施例中通過與形成源極151及汲極152 相似的方法在絕緣層130表面且與半導體層14〇相對的位 置形成-導電薄膜作爲閘極12〇。該閘極12〇通過絕緣層 130與半導體層14〇電絕緣。本技術方案實施例中，所述 ❹閘極120的材料爲鈀’閘極12〇的厚度約爲丄微米。 請參閱圖4及圖5,本技術方案第二實施例提供一種 底開型薄臈電晶H 20的製備方法，其與第一實施例中薄膜 電晶體10的製備方法基本相同。主要區別在於，本實施例 中形成的薄膜電晶體20爲一底閘型結構。本技術方案第二 實施例薄臈電晶體2 0的製備方法包括以下步驟： 步驟一：提供一生長基底。 φ 步驟一·形成一奈米碳管層於所述生長基底表面，所 述奈米碳管層包括多個奈米碳管。 步驟三：提供一絕緣基底21〇。 步驟四：形成一閘極22〇於所述絕緣基底21〇表面。 步驟五：形成一絕緣層230覆蓋所述閘極220。 步驟六：轉印該奈米碳管層至所述絕緣層23〇表面， 形成一半導體層240。 該轉印步驟具體包括以下步驟：首先，將該形成有奈 米碳管層的生長基底倒扣在絕緣基底21〇上使奈米碳管層 21 200952086 表面與絕緣層230表面接觸’從而形成一從上到下依次包 •括生長基底、奈米碳管層及絕緣基底210的三層結構；再 •次，熱壓該三層、结構；最後，移去生長基底，從而使上述 •奈米碳管層黏附於所述絕緣層23〇表面，形成一半導 240 ° 當將該形成有奈米碳管層的生長基底倒扣在絕緣基底 210上時，應確保該奈米碳管層表面與絕緣層23()表面相 ❹貼合，從而使奈米碳管層黏附在絕緣層23〇上。 步驟七·間隔形成一源極251及一汲極252，並使該 源極251 &汲極252與上述半導體f 24〇中的部分奈米碳 管的兩端電連接。 所述源極251、汲極252、閘極220及絕緣層23〇均可 採用與第一實施例相同的方法形成。 請參閱圖6,本技術方案第三實施例提供一種薄臈電 晶體的製備方法，其與第一實施例薄膜電晶體1〇的製備方 ❹去基本相同。主要區別在於，本實施例在同一絕緣基底上 形成多個薄臈電晶體，從而形成一薄膜電晶體陣列。本實 施例薄膜電晶體的製備方法具體包括以下步驟： 步驟一：提供一絕緣基底。 步驟一.在絕緣基底表面均勻形成多個奈米碳管層， 所述奈米碳管層包括多個奈求碳管，進而形成多個半導體 層。 上述步驟二可通過兩種方式進行。第一種方式具體包 括以下步驟：在絕緣基底表面形成一大面積的奈米碳管 22 200952086 層，及採用掩模及钱刻等方法圖案化該奈米碳管層，從而 .在而要形成薄膜電晶體的不同位置形成多個奈米碳管層。 ·*·第，種方式具體包括以下步驟：在預形成薄膜電晶體的位 置升7成夕個帶狀催化劑薄膜；採用化學氣相沈積法生長多 帶狀不米石炭管陣列，及對多個帶狀奈米碳管陣列進行處 理’形成多個奈米碳管層。 所述多個帶狀催化劑薄膜可通過熱沈積法、電子束沈 積法或減射法多次沈積而形成，也可通過光刻法或掩模法 來實現。所述帶狀催化劑薄膜之間的間距優選爲1〇微米 〜15毫米。所述帶狀催化劑薄膜的寬度爲丄微米〜2〇微米。 所述帶狀催化劑薄膜的厚度爲〇Λ奈米〜1〇奈米。 步驟四：@隔形舒個源極及多個汲極，並使上述每 一半導體層中的部分奈米碳管的兩端均與—源極及一汲極 電連接。 與本技術方案第一實施例中的源極151及汲極152的 ❹形成方法相似，可以先在形成有多個半導體層的整個絕緣 基底表面沈積-金屬薄膜，再通過蚀刻等方法圖案化該金 屬薄膜’從而在預定位置上-次形成多個源極及多個沒 極。上述源極及汲極的材料也可爲ΙΤ〇、ατ〇、導電聚合 物、導電銀膠或奈米碳管。 ° 步驟五·形成一絕緣層於每一半導體声表面。 上述絕緣層的形成方法與本技術方案第一實施例 薄膜電晶體10中的絕緣層130的製備方法相似，可以先在 整個絕緣基底的表面沈積-氮切薄m，再通軸刻等方 200952086 法圖案化s亥氮化梦薄膜’從而在預定位置上一次形成多個 絕緣層。上述絕緣層的材料也可爲氧化梦等硬性材料或苯 ‘並環丁烯（BCB)、聚酯或丙烯酸樹脂等柔性材料。 •步驟六：形成一閘極於每一絕緣層表面，得到多個薄 膜電晶體。 可以理解，通過與第二實施例相似的方法，也可以形 成多個薄膜電晶體，進而形成一薄膜電晶體陣列，其具體 包括以下步驟： ❹The material of the source m and the electrodeless 152 should have good electrical conductivity. Specifically, the material of the source electrode 151 and the drain electrode 152 may be a conductive material such as a metal, an alloy, or an indium tin oxide (such as a tantalum, a tantalum oxide (AT〇), a conductive silver paste, a conductive polymer, or a nano carbon (tetra) film. The material 151 and the gate 152 may be formed from time to time depending on the type of material forming the source 151 and the gate 152. Specifically, when the source i5i and the electrode 152 are made of metal or alloy The source 151 and the drain 152 may be formed by subtractive bonding, subtractive sputtering, deposition, masking, etching, etc. When the source 151 and the drain 152 are made of conductive silver paste and conductive. The polymer or carbon nanotube thin material is coated or adhered to the surface of the insulating substrate 110 or the semiconductor layer 140 by direct adhesion or printing coating to form a source 151. And the drain 152. Generally, the source 151 and the drain 152 have a thickness of 〇5 nm to 1 〇〇m, and the distance between the source 151 and the drain 152 is jqoo micron. In this embodiment, The material of the source 151 and the drain 152 is metal. The above steps - specifically by the following two The first method specifically includes the following steps: first, uniformly coating a surface of the semiconductor layer 140 with a layer of photoresist; secondly, forming a source 151 and a germanium by photolithography through exposure and development. In the region of the pole 152, the semiconductor layer 140 is exposed in the source 151 and the drain 152 region; again, by a deposition method such as vacuum sputtering, magnetron sputtering or electron beam evaporation deposition on the above photoresist, source 18 200952086 pole 151 And the surface of the immersed 152 region is deposited with a gold layer, preferably a palladium, chin or nickel metal layer. Finally, the photoresist and its metal layer are removed by an organic solvent such as acetone to form a semiconductor. The source 151 and the drain 152 on the layer 140. The second method specifically includes the following steps: first, depositing a metal layer on the surface of the semiconductor layer 140; secondly, applying a layer of photoresist on the surface of the metal layer; The photoresist outside the source 151 region and the drain 152 region is removed by photolithography such as exposure and development; finally, the metal ruthenium layer outside the source 151 region and the drain 152 region is removed by plasma etching or the like. The photoresist on the source 151 region and the drain 152 region is removed by an organic solvent such as acetone to obtain the source 151 and the drain 152 formed on the semiconductor layer 14A. In this embodiment, the source is ι51 and 汲. The thickness of the pole 152 is 1 μm, and the distance between the source 151 and the drain 152 is 5 μm. It can be understood that in order to obtain the semiconductor layer 140 having better semiconductivity, after forming the source 151 and the drain 152 The method further includes the step of removing the conductive carbon nanotubes in the semiconductor layer 140. Specifically, the method includes the following steps: first, providing an external power source, and secondly, connecting the positive and negative poles of the external power source to the source 151 and the drain 152. Finally, a large electric power is applied to the source 151 and the drain 152 through an external power source to heat and ablate the conductive carbon nanotube to obtain a semiconducting semiconductor layer 140. This voltage is in the range of 1 to 1 〇〇〇. Further, the above method of removing the conductive carbon nanotubes in the semiconductor layer 140 may also irradiate the semiconductor layer ι4 using hydrogen plasma, microwave, terahertz (THz), infrared (ir), ultraviolet (UV) or visible light (Vis). Thereafter, the conductive carbon nanotube is heated and ablated to obtain a semiconducting semiconductor layer 19 200952086 140. Step 4: Forming an insulating layer DO on the semiconductor layer 14A.材料 The material of the (four) 130 may be a hard material such as nitrogen cutting or oxygen cutting, or a flexible material such as benzocyclobutene (BCB) or polyacrylic resin. Depending on the type of material of the insulating layer 13G, the insulating layer can be formed by different methods. Specifically, when the material of the insulating layer 13G is nitrogen or oxidized, the insulating layer 13 can be formed by a deposition method. When the insulating layer is a material of a stupid and cyclobutene (BCB), polyester or propylene: resin, the insulating layer 13 can be formed by a printing coating method. Generally, the thickness of the insulating layer 130 is 〇 5 nm to 1 μm. In the present embodiment, a tantalum nitride insulating layer 130 is formed by a deposition method such as electroless chemical vapor deposition to cover the surface of the semiconductor layer 140 and the source electrode 151 and the drain electrode 152 formed on the semiconductor layer 140. The insulating layer 13 has a thickness of about 1 μm. It can be understood that, depending on the different applications of the thin film transistor, a portion of the source 151 and the drain 152 may be exposed to the insulating layer 13 by photolithography or etching similar to the formation of the source 151 and the drain 152. ()outer. Step 5: forming a gate 120 on the surface of the insulating layer 13 to obtain a thin film transistor. The material of the pole 120 should have good electrical conductivity. Specifically, the material of the gate 120 may be a conductive material such as a metal, an alloy, a tantalum, a Ατ〇, a conductive silver paste, a conductive polymer, or a carbon nanotube film. The metal or alloy material may be sinter, copper, tungsten, molybdenum, gold or alloys thereof. Specifically, when the material of the gate 120 is metal, alloy, tantalum or niobium, the interpole i2〇 can be formed by sputtering, sputtering, deposition, masking, and residual etching. When the material of the gate ί20 is a conductive silver paste, a conductive polymer or a carbon nanotube film, the idle electrode H can be formed by direct adhesion or printing coating. Generally, the thickness of the gate 120 is 0.5 nm. Meters ~ 1 〇〇 micron. In the embodiment of the present invention, a conductive film is formed as a gate electrode 12 at a position on the surface of the insulating layer 130 and opposite to the semiconductor layer 14A by a method similar to the formation of the source electrode 151 and the drain electrode 152. The gate 12 is electrically insulated from the semiconductor layer 14 by an insulating layer 130. In the embodiment of the technical solution, the material of the germanium gate 120 is palladium and the thickness of the gate 12 is about 丄 micron. Referring to FIG. 4 and FIG. 5, the second embodiment of the present invention provides a method for preparing a bottom-open type thin germanium electro-crystal H 20, which is basically the same as the method for preparing the thin film transistor 10 in the first embodiment. The main difference is that the thin film transistor 20 formed in this embodiment is a bottom gate type structure. The second embodiment of the present invention provides a method for preparing a thin germanium transistor 20 comprising the following steps: Step 1: providing a growth substrate. φ Step 1. Form a carbon nanotube layer on the surface of the growth substrate, the carbon nanotube layer comprising a plurality of carbon nanotubes. Step 3: Provide an insulating substrate 21〇. Step 4: Form a gate 22 on the surface of the insulating substrate 21. Step 5: Form an insulating layer 230 to cover the gate 220. Step 6: Transfer the carbon nanotube layer to the surface of the insulating layer 23 to form a semiconductor layer 240. The transfer step specifically includes the following steps: first, the growth substrate on which the carbon nanotube layer is formed is inverted on the insulating substrate 21, so that the surface of the carbon nanotube layer 21 200952086 is in contact with the surface of the insulating layer 230 to form a From top to bottom, the three-layer structure including the growth substrate, the carbon nanotube layer and the insulating substrate 210 is sequentially arranged; the third layer and the structure are heat-pressed again; finally, the growth substrate is removed, thereby making the above-mentioned nanometer The carbon tube layer is adhered to the surface of the insulating layer 23 to form a half-conducting 240 °. When the growth substrate on which the carbon nanotube layer is formed is inverted on the insulating substrate 210, the surface of the carbon nanotube layer should be ensured. The surface of the insulating layer 23() is adhered to each other so that the carbon nanotube layer adheres to the insulating layer 23'. Step 7. A source 251 and a drain 252 are formed at intervals, and the source 251 & drain 252 is electrically connected to both ends of a portion of the semiconductor f 24 . The source 251, the drain 252, the gate 220, and the insulating layer 23 can be formed in the same manner as in the first embodiment. Referring to FIG. 6, a third embodiment of the present technical solution provides a method for preparing a thin tantalum transistor, which is substantially the same as the preparation method of the thin film transistor 1 of the first embodiment. The main difference is that this embodiment forms a plurality of thin germanium transistors on the same insulating substrate to form a thin film transistor array. The method for preparing the thin film transistor of the embodiment specifically comprises the following steps: Step 1: providing an insulating substrate. Step 1. A plurality of carbon nanotube layers are uniformly formed on the surface of the insulating substrate, and the carbon nanotube layer includes a plurality of carbon nanotubes to form a plurality of semiconductor layers. Step 2 above can be performed in two ways. The first method specifically includes the steps of: forming a large area of the carbon nanotube 22 layer 200952086 on the surface of the insulating substrate, and patterning the carbon nanotube layer by using a mask and a vacuum engraving method, thereby forming A plurality of carbon nanotube layers are formed at different positions of the thin film transistor. ··· The first method comprises the following steps: increasing the size of the strip-shaped catalyst film at a position where the thin film transistor is pre-formed; growing the multi-band non-meter carbon tube array by chemical vapor deposition, and The ribbon-shaped carbon nanotube array is processed to form a plurality of carbon nanotube layers. The plurality of strip catalyst films may be formed by multiple deposition by a thermal deposition method, an electron beam deposition method, or a subtractive method, or may be realized by photolithography or a mask method. The spacing between the strip catalyst films is preferably from 1 μm to 15 mm. The strip catalyst film has a width of 丄 micrometers to 2 〇 micrometers. The thickness of the strip catalyst film is from 〇Λ nanometer to 1 〇 nanometer. Step 4: @隔形 a source and a plurality of drain electrodes, and connect both ends of each of the carbon nanotubes in each of the semiconductor layers to the source and the drain. Similar to the method of forming the source 151 and the drain 152 in the first embodiment of the present technical solution, a metal thin film may be deposited on the entire surface of the insulating substrate on which the plurality of semiconductor layers are formed, and then patterned by etching or the like. The metal thin film' thus forms a plurality of sources and a plurality of gates at a predetermined position. The material of the source and the drain may also be ruthenium, ατ〇, a conductive polymer, a conductive silver paste or a carbon nanotube. ° Step 5. Form an insulating layer on each of the semiconductor acoustic surfaces. The method for forming the above-mentioned insulating layer is similar to the method for preparing the insulating layer 130 in the thin film transistor 10 of the first embodiment of the present invention. It is possible to deposit a nitrogen thinning m on the surface of the entire insulating substrate, and then pass through the axis and the like. 200952086 The pattern is patterned to form a plurality of insulating layers at a predetermined position. The material of the above insulating layer may also be a hard material such as oxidized dream or a flexible material such as benzene 'cyclobutene (BCB), polyester or acrylic resin. • Step 6: Form a gate on the surface of each insulating layer to obtain a plurality of thin film transistors. It will be understood that a plurality of thin film transistors may be formed by a method similar to that of the second embodiment, thereby forming a thin film transistor array, which specifically includes the following steps:
步驟一：提供一生長基底。 步驟二：形成一奈米碳管層於所述生長基底表面，所 述奈米碳管層包括多個奈米碳管。 步驟三：提供一絕緣基底。 步驟四：形成多個閘極於所述絕緣基底表面。 步驟五：形成至少一絕緣層覆蓋所述多個閘極。 ，步驟六：鋪設上述至少一奈米碳管層於所述絕緣層表 =圖案化該奈米碳管層，形成多個半導體層，該多個半 層與上述多個閘極通過絕緣層相對並絕緣設置。 步驟七.間隔形成多個源極及多個没極，並使該源極 =與上述半導體層中的部分奈来碳管的兩端電連接， 形成多個薄臈電晶體。 點：:！衔方案實施例薄膜電晶體的製備方法具有以下優 上n由於所述半導體層可直接形成在所述絕緣基底 轉印—:=成=生長基底上的奈米碳管陣列進行 備’故種半導體層的形成方法比先前技術中 24 200952086 的噴=印法形成薄膜電晶體 經過在有機溶射分散奈米碳管的步驟。:簡^無需 備的奈米碳管層中的奈半破技 其一，由於所製 該奈米碳管層作爲半導體層^疋方向平行排列’故將 :=Γ獲得較大的載子移動率。其三，二 Ο =;=!學性能’則由多個擇優取向排列心 及組成的半導體層具有較好的勒性 及機械强度’從而有利於製備柔性薄膜電晶體。其 積奈米碳管層進行餘刻或製備多個奈 製備多個薄膜電晶體，進而可實現薄膜電晶體 置産’且該方法製備的薄膜電晶體的成本較低。其 五由於本實施例所提供的奈米碳管層可以採用一轉印步 驟將奈来碳管層轉印到其它基底上’該基底的材料可以選 擇不=高溫的柔性材料，有利於製備柔性薄膜電晶體。 曰綜上所it ’本發明確已符合發明專利之要件，遂依法 &出專利申Μ ’以上所述者僅為本發明之較佳實施例， 自不能以此限制本案之申請專利範圍。舉凡習知本案技藝 之人士援依本發明之精神所作之等效修飾或變化，皆應涵 蓋於以下申請專利範圍内。 〜 【圖式簡單說明】 圖1係本技術方案第一實施例薄膜電晶體的製備方法 流程圖。 圖2係本技術方案第一實施例薄膜電晶體的製備工藝 200952086 流程圖。 圖3係本技術方案第一實施例奈米碳管層的掃描電鏡 \照片。 \ 圖4係本技術方案第二實施例薄膜電晶體的製備方法 流程圖。 圖5係本技術方案第二實施例薄膜電晶體的製備工藝 流程圖。 圖6係本技術方案第三實施例薄膜電晶體的製備方法 © 流程圖。 【主要元件符號說明】 薄膜電晶體 10, 20 絕緣基底 110, 210 閘極 120, 220 絕緣層 130, 230 半導體層 140, 240 源極 151，251 汲極 152, 252 26Step 1: Provide a growth substrate. Step 2: forming a carbon nanotube layer on the surface of the growth substrate, the carbon nanotube layer comprising a plurality of carbon nanotubes. Step 3: Provide an insulating substrate. Step 4: forming a plurality of gates on the surface of the insulating substrate. Step 5: forming at least one insulating layer to cover the plurality of gates. Step 6: laying the at least one carbon nanotube layer on the insulating layer table=patterning the carbon nanotube layer to form a plurality of semiconductor layers, wherein the plurality of half layers are opposite to the plurality of gates through the insulating layer And insulated settings. Step 7. Form a plurality of sources and a plurality of gates at intervals, and electrically connect the source electrode to the two ends of the carbon nanotubes in the semiconductor layer to form a plurality of thin germanium transistors. point::! The method for preparing a thin film transistor has the following advantages: since the semiconductor layer can be directly formed on the insulating substrate transfer-:===================================================== The formation method of the layer is formed by a method of forming a thin film transistor by spraying/printing in the prior art 24 200952086 through the step of dispersing the carbon nanotube in the organic solution. : The simple half-breaking technique in the carbon nanotube layer that is not required is one, because the carbon nanotube layer is arranged as a parallel direction of the semiconductor layer, so that: = Γ obtains a large carrier mobility . The third, the second Ο =; = learning performance 'is a plurality of preferred orientations of the semiconductor layer and the composition of the semiconductor layer has a better degree of mechanical and mechanical strength' to facilitate the preparation of flexible thin film transistors. The carbon nanotube layer of the carbon nanotubes is used for the engraving or preparation of a plurality of thin films, thereby preparing a plurality of thin film transistors, thereby realizing the production of thin film transistors, and the cost of the thin film transistors prepared by the method is low. 5. Because the carbon nanotube layer provided in this embodiment can transfer the carbon nanotube layer to other substrates by a transfer step, the material of the substrate can be selected as a flexible material not high temperature, which is favorable for preparing flexibility. Thin film transistor. The invention has indeed met the requirements of the invention patent, and the above-mentioned patent application is only a preferred embodiment of the invention, and it is not possible to limit the scope of the patent application in this case. Equivalent modifications or variations made by those skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a flow chart showing a method of preparing a thin film transistor according to a first embodiment of the present technical solution. 2 is a flow chart of a preparation process of a thin film transistor according to a first embodiment of the present technical solution. Fig. 3 is a scanning electron microscope image of a carbon nanotube layer of the first embodiment of the present technical solution. Fig. 4 is a flow chart showing a method for preparing a thin film transistor according to a second embodiment of the present technical solution. Fig. 5 is a flow chart showing the preparation process of the thin film transistor of the second embodiment of the present technical solution. 6 is a flow chart of a method for preparing a thin film transistor according to a third embodiment of the present technical solution. [Major component symbol description] Thin film transistor 10, 20 Insulation substrate 110, 210 Gate 120, 220 Insulation layer 130, 230 Semiconductor layer 140, 240 Source 151,251 Bungee 152, 252 26