SU598070A1 - Function computing arrangement - Google Patents

Description

The invention relates to the field of computer technology and can be applied in digital computer computers built on integrated circuits.

Devices for calculating functions are known, which are tabular computations built on the basis of a permanent memory (1. However, these devices have limited functionality.

The closest technical solution to this invention is a function calculating device comprising a shift register, an output group of which is connected to a group of inputs of an input register, connected by its outputs to a memory unit and an output register 2.

 The device also has limited functional capabilities. With it, it is not possible to calculate functions in non-autonomous mode when the operand enters the device's input bitwise and (the i-digit of the result is generated before the (i +1) -th operand digit in the device. This does not allow using such a device effectively

2

real-time control processes, when information is fed to the device input in a progressive code from older ones: bits. In addition, this device cannot reduce the number of external leads without significantly reducing its performance. When calculating the function, it is necessary that the operand be represented by n {shocking bits. In this case, the device requires a large number of external leads, which increases with increasing bit of the operand and result representation. This makes it difficult to implement in the form of a large integrated circuit.

The chain of the invention is functionality enhancement.

This is achieved in that the proposed device further comprises a switch, a code comparison unit and an AND element, the first input of which is an input of the device, the output is connected to the control input of the input register, the output group of the shift register is connected to the first group of inputs of the switch, the second group of inputs of which connected to the group of outputs of the block, the group of outputs of the switch is connected to the first group of inputs of the code comparison unit in group 1 of the inputs of the output register, the group of outputs of which is connected to the second group Understanding the inputs of the code comparison unit, the first and second outputs of the code comparison unit at 5pots corresponding to the device outputs, with this input the input of the AND element, controlled by the inputs of the shift register, the output register, and the code & numbered codes are the first, second , third and fourth control inputs of the device. The drawing shows the structural scheme of the proposed device. The device contains the shift register 1, the input register 2, the memory block 3, the switch 4) the output register 3t the code comparison block 6 and the element 7. The registers 1,2,5 contain h bits, where P is the width, representing the operation 1; yes and result. A mutator 4 can be built, for example, in the form of a triangular matrix consisting of n lines of elements I. Each I - row of this matrix contains .g elements I. To one of the inputs of the elementer and the tth matrix column is connected; t - and the output of the memory block 3. To the second inputs of the elements AND of each / g row of the subcontrols - and the output of the shift register 1, To separate the outputs of the AND elements of a single column, it is possible to extract OR elements. Input register 2 can be constructed on the basis of flip-flops. Then, when calculating monotonically increasing options, the outputs of shift register 1 are connected to the R-inputs of the trigger of input register 2, and when calculating monotonically decreasing functions - to the S inputs of the input register 2. The device is pre-assigned for computing in non-autonomous mode continuous monotonically decreasing or increasing functions, the value of which is derived in the range of definition does not exceed one in absolute value. For example, j sin X and g. , with, if (“-) P K 1, V-, and y) are very large. The device operates in the following manner. In the calculation of a monotonically increasing function in the initial state, units are written in all bits of the input register 2, and in the calculation of a monotonically decreasing function, zeros. Regardless of the type of the calculated function, the output register 5 is set to the zero state, and yes, the highest shift register register 1 is stored, memory unit 3 contains a table of functions in a given interval. DP of the function is performed n cycles, consisting of four cycles. At the beginning of each i-th cnc, an inverse value of the 1st bit of the initial operand arrives at the informa- tion input 8 (the operand enters, starting with the highest bits). The control inputs 9-12 in each clock cycle receive control signals successively in time. In the first clock cycle on the control signal that is received by the controller on control, the AND 7 element and the inverse value of the next bit: the operand controls the reception of the input register 2 code. If the next bit of the operand is zero, which corresponds to the single information Signal, then the .1st bit of the input register 2 changes its state to the opposite. A new input word is formed in the input register 2 and the memory block 3 outputs to the inputs of the switch 4 an output word corresponding to this input word. At the same time, at the outputs of switch 4 in each cycle there is a code consisting of (t higher bits of the word generated by memory block 3 and zeros in the remaining bits. In the second clock cycle of the control; neck signal arriving at H, the code on the output of switch 4 is compared with the code in output register 15 and generated in the (i -1) -th cycle. If the code from output 4 is smaller than the cop written in output register 6. 6 generates a VED low signal to output 14, which indicates that the next normal and low cut If this code is greater than the code written in output register 5, then the code comparison block outputs an e-pin signal to output 13, which indicates that the next bit of the result is numerically equal. If these codes are equal, a single signal It does not appear on any of the outputs 13,14, which indicates that the next digit of the result is numerically zero. In the third clock cycle of the control signal received at input 11, the output of the output register 5 is received. switch 4. In the fourth cycle of control The incoming signal at input 12 is shifted to the information in shift register 1. At this end, one cycle of numerals. As a result of the execution and cycles at the outputs of the device, a sequential code of the values of the futures in the redundant binary system with the numbers 1,6, 1 is formed. Thus, the device allows to calculate the functions in the non-autonomous mode, W, B, and to the information input and output, a small amount of external communications, which makes it convenient for integral execution.

Fbrmu invention

A device for calculating functions comprising a shift register, a group of outputs KOTopotO connected to a group of inputs of an input register connected by its outputs to a memory unit, an output register characterized in that, with an extension of functionality, it further comprises a switch, a unit comparing Codes and the element I, the first input of which is the input of the device, the output is connected to the control input of the input register, the group of outputs of the shift register is connected to the first group

the switch inputs, the second group of inputs of which is connected to the group of outputs of the memory block, the group of outputs of the switch is connected to the first group of inputs of the code comparison block and the group of inputs of the output register, the output group of which is connected to the second group of inputs of the code comparison block the codes are the corresponding outputs of the device, while the second input of the element Hi, the control inputs of the shift register, the output register and the code comparison block are the first, second, the third and fourth control unit inputs.

Information sources; taken into account during the examination:

1c USSR Copyright Certificate f 45.3739, cl. Q 11 C 17/00, 1972.

2. Copyright witnesses of the USSR

N5 390524. Cl. Q 06 F 7/38, 197O.

/ J