SU1598142A1 - Asynchronous distributor - Google Patents

Abstract

This invention relates to automation and computing. The purpose of the invention is to increase the speed of the asynchronous distributor. The asynchronous valve consists of memory cells 1, each of which contains the first to third elements AND 2-4 and the elements OR 5-7, the elements OR - NOT 8, the element AND - NOT 9, the first 10 and the second 11 control inputs, the first 12 and second 13 control outputs, the start input 14 and the initial exit 15. By providing additional possibilities for controlling the state of the asynchronous distributor memory cell, an increase in its speed is achieved. The passage time of one firmware is 6 Τ, where Τ is the delay of the AND-OR-NOT element (OR-AND-NOT). 1 il.

Description

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The invention relates to automation and computer engineering.

The purpose of the invention is to increase the speed of the asynchronous distributor.

The drawing shows the functional diagram of the device.

The asynchronous distributor consists of memory cells 1, each of which contains the first through the third elements AND -2-4 and the elements LII 5-7, the element OR-NOT 8, the element AND-HE 9, the first 10 and the second 11 controls The first inputs 12 and second 13 control outputs, start input 14 and setup input 15.

The operation of the asynchronous distributor is as follows.

In the initial state, the memory cell 1 in the R-flip-flop consisting of elements 2-9 is recorded as logical O, i.e. at the output of the element OR-HE 8 there is a single logical level, at the output of AND-NOT 9 - zero. For this purpose, a zero logic signal is set at the initial 10 input, which leads to the appearance of unit levels at the outputs of all the elements OR-HE 8, which in turn establish the unit logic levels at the outputs of the elements AND-HE 9. After the initial setup is completed, a single logic level is maintained at input 10.

In the operating mode in the asynchronous distributor installation (1-1) -th; memory cells 1 are produced by supplying a single logic level to its launch input 14. In this case, an R-trigger will be written 1, .e.e. at the output of the element OR NOT 8 there is zero logical reasoning at the output; and at the output of the element NE 9, the unit one. This trigger state cannot change while the trigger input 14 (1-1) -th memory cell does not again have a zero logic level. Setting the R-trigger (1-1) memory cell to -1 causes the appearance of a single logic level at the second control output 13, which is fed to the start-up input 14 of the ith memory cell. As a result, 1 is written into the R-trigger of the ith memory cell, i.e. at the output of the OR-NOT 8 element, a zero logic level appears, and the output of the AND-II 9 element is a single logical

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cue level. The installation of the R-trigger of the i-th memory cell causes the appearance of a zero logic level at the first control output of the 12th i-th memory cell, which is fed to the first control input of the 10 (i-1) -th memory cell. If by this time at the start input 14 of the (i -) th memory cell there is a zero logic level, then a zero logic level appears at the first control input 10 and a single logic level at the second control input 11 (i-1) - the first memory cell leads to the return of the R-trigger, (i-1) and the memory cell to the zero state, i.e. at the output of the element OR NOT 8, according to Wits, the unit logic level, at the output of the element AND-NOT 9 - zero. At the same time, the installation of (i + 1) -th memory cell 1 will occur, the operation of which is similar to that considered.

As long as the R-flip-flop of the (ii) -and cell-1 of the memory can be recorded 1 in the R-trigger of the. Memory of the first memory 1. Indeed, in the first 12 and second 13 control outputs i -th cell of memory (on the first 10 and second 11 control inputs of the (i-1) -and memory cells) are set, respectively, to a zero and a single logical level that keep the R-trigger of the (i-1) -th memory cell In the O state, the occurrence of a single logic level at the start 14 of the (i-1) -th memory cell does not cause the R-flip-flop to switch.

Thus, re-installing; Ka (i-1) -and memory cell 1 is performed only after the i-cell memory is in the initial state. Consequently, when re-initiating the asynchronous distributor operation before the previous cycle of its operation completes, the next wave of the settings of the memory cells will not reach the previous one, since there will always be at least one memory cell between them. state that ensures the correct functioning of the distributor in multiprogram mode.

In an asynchronous distributor, re-placement can be performed after its second cell

The memory returns to its original state. the transit time of one firmware in it is T / 1

 (-

 Bj

where I. - the delay element AND-OR-NOT (OR-AND-NOT).

Claims (1)

Invention Formula An asynchronous distributor containing memory cells, the first and second control inputs of the ith memory cell are connected respectively to the first and second control outputs (1 + 1) memory cell, the start input of the ith memory cell is connected to the second control output (-1) -th memory cell, characterized in that, in order to improve speed, the memory cell contains the first to the third AND and OR elements, the AND-NOT and OR-NOT elements, as well as the initial setup input , with the first and second inputs respectively first with the first inputs of the first and second OR elements and the first control input of the memory cell, the second, first and third inputs of the first, second and third elements AND, respectively, are connected to the input of the initial installation of the memory cell, the third and second inputs of the first and second respectively elements AND are connected to the start input of the memory cell, the third and first inputs of the second and third elements AND, respectively, are connected to the output of the NAND element and the second control 5 to the output of the memory cell, the outputs of the AND elements are connected to the inputs of the OR-NOT element, the output of which is connected to the second and nepBoi-iy inputs of the second and third OR elements and the first control output of the memory cell, respectively, the second inputs the first and third elements of the IL are connected to the second control input of the memory cell, the outputs of the elements OR first and third elements And connected 25 are connected to the inputs of the element AND-NOT.