SU1179322A1 - Device for multiplying two numbers - Google Patents

Abstract

A DEVICE FOR THE MULTIPLICATION OF TWO NUMBERS, containing the multiplicable register, the multiplier register, the block of formation of partial products, the synchronization block, the registers of the high and low bits of the works, the information inputs of which are connected respectively to the outputs of the high and low bits of the block of formation of partial products, the first and second groups whose inputs are connected respectively to the outputs of the multiplier and multiplier registers, the information inputs of which are connected respectively to the inputs of the multiplicand and multiplier The synchronization block outputs are connected to the synchronous inputs of the multiplicand, multiplier, higher work bits and lower work bits, respectively, characterized in that, in order to expand the functionality by providing multiplication of binary integers modulo 2 -1, the element is NOT, the two groups of elements are And by h are the elements And are in each, the AND is the bit size adder and the result correction block containing the q -input element AND and the P-bit adder, with the outputs of the low-order register n The images are connected to the inputs of the first term of the P-bit adder, the inputs of the second term of which are connected to inputs of elements AND of the first group, the first inputs of which are connected to the output of element NOT, with s whose input is connected to input of setting the operating mode of the device and with the first inputs of elements AND the second group, the second inputs of which are connected to the outputs of the high-order register of the product and the second inputs of the corresponding elements of the first group, and the outputs to the outputs of the higher-order product of the device va, outputs LSBs product of which are connected to the outputs of AND -bit adder Bloch. There is a result correction, the inputs of the first addend of which are connected to a wide zero potential, and the inputs of the second addend are connected to the inputs of the n-input element AND of the result correction block and the outputs of the sum of the n-adder, the transfer output of which is connected r1-bit adder, output of tl-input element And the result correction block are connected to the transfer input of the n-bit adder of the result correction block.

Description

The invention relates to computing and technical cybernetics and can be used in devices for digital signal processing (in particular, for digital image processing), as well as in coding systems whose principle of operation is based on Galois field theory.

The purpose of the invention is to expand the functionality of the device by providing an additional multiplication of n-bit binary modulus, which is different from the power of two.

Fig. 1 schematically shows a device for multiplying two numbers} in Fig. 2 is a diagram of a result correction block.

The device for multiplying two numbers (Fig. 1) contains registers of multiplicative 1 and multiplier .2, block 3 for the formation of partial products, registers of lower 4 and higher 5 bits before the product, element 6, first 7 and second group 8 elements And, and - a bit adder 9, a result correction block 10, and a synchronization block 11.

The result correction block 10 (FIG. 2) contains an h-input element And 12 and a 1-digit adder 13

The device works as follows.

The bits a, ..., a, the multiplicand, and, .., BP | multipliers come to registers 1 and 2, respectively. Then they are transmitted to the inputs of the factors of block 3, the outputs of which form the result of the usual multiplication, which is a number with 2 binary bits. On the reception signal C, the lower bits are recorded in register i, and the older ones - in register 5

If the signal that determines the operation mode of the device corresponds to a logical one, then the logical zero signals appear at the inputs of the AND elements from the first group. Then at the exits E,. , Q-bit of the adder 9 appear younger bits of the product, and on the outputs of the elements And the second group Qti +, ..., C) 2n higher bits. Thus, the usual multiplication of n-bit binary numbers is accomplished.

Since 2 coincides with the unit modulo 2 -1, then 2 coincides on

specified module c, 2, ..., l). This means that the highest bits of the product have the same weight as the corresponding lower bits. Therefore, to bring the product modulo 2 -1, it is necessary to add two numbers formed by the lower and upper digits of the product.

The specified action is performed in the modulo multiply mode. The signal that determines the mode of the device in this mode corresponds to a logical zero. At the outputs of the elements of the first group there appear signals corresponding to the most senior bit of the product, and at the outputs of the elements of the second group there appear signals of a logical zero. Adder 9 produces the addition of the numbers formed by the younger and older bits. After the addition, transfer from the G1-GO discharge of the adder, having a weight of 2, i.e. unit modulo. Therefore, feedback is introduced between the transfer output and the transfer input of the adder 9. During the two additions at the outputs Q,, ..., Q of the adder 9, multiplication bits are generated modulo 2 -1. The result is in binary code.

However, a device for multiplying two numbers in multiplication modulo 2 -1 mode has two representations zero: 00. . .0 and (, J so

L discharge

(1 bit

as the number 11 ... 1 is comparable to digit 11

Lem on the module. Therefore, the final result must be adjusted. Correction of the result, if necessary, is carried out by block 10. The result of multiplication (or a series of multiplications and additions modulo) is fed to an AND input element AND 12 and simultaneously to the inputs of the first term of the c-discharge adder 13 (a logical zero signal is fed to the inputs of the second term ). When all the bits of the result are equal to one, the unit at the output of the n-element element And 12 appears the unit arriving at the transfer input of the h-bit adder 13. Then at its sum outputs zero values are set.

Claims (1)

A device for multiplying two numbers, containing the register of the multiplier, the register of the multiplier, the block for generating partial products, the synchronization block, the registers for the upper and lower bits of the products, the information inputs of which are connected respectively to the outputs of the higher and lower bits of the block for forming the partial products, the first and second groups of inputs of which connected respectively with the outputs of the registers of the multiplier and multiplier, the information inputs of which are connected respectively with the inputs of the multiplier and multiplier two, the outputs of the synchronization block are connected to the synchro inputs of the registers of the multiplier, multiplier, high order of the product, and low order of the product, respectively, characterized in that, in order to expand the functionality by ensuring the multiplication of binary integers modulo 2 -1, it is introduced NOT element, two groups of AND elements with h elements AND in each, AND is a bit adder and a result correction block containing a C-input element I and a U-bit adder, and the outputs of the least significant register of the product with are connected to the inputs of the first term of the i-bit adder, the inputs of the second term of which are connected to the outputs of the elements of the first group, the first inputs of which are connected to the output of the element NOT, the input of which is connected to the input of the installation mode of the device and the first inputs of the elements of the second group, the second the inputs of which are connected to the outputs of the register of the highest bits of the product and the second inputs of the corresponding elements of the first group, and the outputs are the outputs of the highest bits of the product of the device, the outputs of the lower bits whose products are connected to the outputs of the AND-bit adder of the result correction block, the inputs of the first term of which are connected to the zero potential bus, and the inputs of the second term to the inputs of the n-input element AND of the result correction block and the outputs of the sum of the η-bit adder the transfer of which is connected to the transfer input of the same n-bit adder, the output of the h-input element AND of the result correction block is connected to the transfer input of the η-bit adder of the result correction block. SU „„ 1179322> * 1179322 2