RU2754122C1 - High-speed accumulating adder modulo of arbitrary natural number - Google Patents

Abstract

FIELD: computing.

SUBSTANCE: invention relates to computing. A high-speed accumulating adder modulo an arbitrary natural number is characterized by the fact that an additional n-bit adder, as well as the second and third n-bit registers are introduced into it, and the clock inputs of the registers are connected to the clock input of the device, and the register zeroing inputs are connected to the zeroing input of the device, the output of the second n-bit register is connected to the input of the second term of the n-bit adder, and the information input of the second n-bit register is an n-bit information input of the device and is combined with the input of the first term of an additional adder.

EFFECT: performance improvement.

1 cl, 2 dwg

Description

The invention relates to computer technology and can be used in digital signal processing devices, noise-immune codecs and frequency synthesizers.

Known accumulating adders [1], [2], [3], containing binary adders and registers.

The disadvantage of these devices is that they add modulo numbers equal to a natural power of two, whereas many applications require modulo summation of other numbers.

The closest in technical essence to the claimed invention is an accumulating adder modulo [4], the diagram of which is shown in FIG. 1, where it is indicated:

1 - n-bit adder;

2 - (n + 1) -bit adder;

3 - multiplexer;

4 - n-bit register;

5 - n-bit information input of the device;

6 - logical zero input;

7 - input of the bitwise inverted binary code of the module;

8 - logical unit input;

9 - clock input of the device;

10 - device zeroing input;

11 - n-bit information output of the device.

When describing the operation of the prototype device and the claimed device, the abbreviation generally accepted in technical (including patent) documentation will be used, in which a multi-bit input (output) of a block is described as an input (output) of a block without a multi-bit definition.

The prototype device contains an adder 1, the input of the first term of which is connected to the output of register 4 and is the output 11 of the device, and the input of the second term is the information input 5 of the device. A logical zero is fed to the transfer input of the adder 1 from the input 6 of the device, and the output of the sum of the adder 1 is bitwise connected to the second information input of the multiplexer 3 and the n least significant bits of the first addend of the adder 2. The most significant bit of the first addend of the adder 2 is connected to the transfer output of the adder 1, and to the input of the second addend of the adder 2 from the input 7 of the device is fed to the bitwise inverted binary code of the module, over which the summation is carried out. A logical unit is supplied to the transfer input of the adder 2 from the input 8 of the device. The outputs of the n least significant bits of the sum of the adder 2 are bitwise connected to the first information input of the multiplexer 3. The transfer output of the adder 2 is connected to the control input of the multiplexer 3, the output of which is connected to the information input of the register 4. The clock input of the register 4 is the clock input 9 of the device, and its zeroing input is the input for zeroing 10 of the device.

This device sums up the input sequence {A (k); k = 1, 2,…} n-bit numbers modulo an arbitrary natural number P lying in the interval [2, 2 ⁿ - 1]. In this case, the numbers themselves take values from the interval [0, P - 1].

The disadvantage of the device is its low speed in comparison with the accumulating adder [3], which contains only n-bit adder and register. This is because the propagation delay is increased by the amount of delay in the (n + 1) -bit adder and multiplexer.

The objective of the invention is to improve performance.

сумматора, при этом на вход второго слагаемого дополнительного сумматора подается поразрядно проинвертированный двоичный код модуля, по которому осуществляется суммирование, на вход переноса дополнительного сумматора подается логическая единица, а его выход суммы соединен с информационным входом третьего регистра, выход которого поразрядно соединен с n младшими разрядами входа первого слагаемого (n + 1)-разрядного сумматора, младшие n разрядов входа второго слагаемого (n + 1)-разрядного сумматора поразрядно соединены с выходом регистра, при этом на вход переноса (n + 1)-разрядного сумматора, а также на старший разряд входа его второго слагаемого подается логический ноль, на старший разряд входа первого слагаемого

(n + 1)-разрядного сумматора подается логическая единица, а старший разряд его выхода суммы соединен с управляющим входом мультиплексора.To solve the problem, in a high-speed accumulating adder modulo an arbitrary natural number, containing an n-bit adder, a multiplexer and a register, as well as an (n + 1) -bit adder of n least significant bits of the output of the sum of which are bitwise connected to the first information input of the multiplexer, the second information the input of which is connected to the output of the sum of the n-bit adder, and the output of the multiplexer is connected to the information input of the register, the output of which is connected to the input of the first term of the n-bit adder and is the information n-bit output of the device, the clock input of the register is the clock input of the device, and the input register zeroing is the device zeroing input, while a logical zero is applied to the transfer input of the n-bit adder, according to the invention, an additional n-bit adder, as well as the second and third n-bit registers are introduced, and the clock inputs of the registers are connected to the clock input of the device, in inputs about the zeros of the registers are connected to the zeroing input of the device, the output of the second n-bit register is connected to the input of the second term of the n-bit adder, and the information input of the second n-bit register is the n-bit information input of the device and is combined with the input of the first term of the additional

adder, while the bit-inverted binary code of the module is fed to the input of the second adder of the additional adder, the logical unit is fed to the transfer input of the additional adder, and its sum output is connected to the information input of the third register, the output of which is bitwise connected to the n least significant bits the input of the first term of the (n + 1) -bit adder, the least significant n bits of the input of the second term of the (n + 1) -bit adder are bitwise connected to the register output, while the transfer input of the (n + 1) -bit adder, as well as to the highest the bit of the input of its second addend is supplied with a logical zero, the most significant bit of the input of the first addend

The (n + 1) -bit adder is fed with a logical unit, and the most significant bit of its sum output is connected to the control input of the multiplexer.

FIG. 2 shows a diagram of the claimed device, in which the following designations are introduced:

1 - n-bit adder;

(n + 1)-разрядный сумматор;2 -

(n + 1) -bit adder;

3 - multiplexer;

4 - n-bit register;

5 - n-bit information input of the device;

6 - logical zero input;

7 - input of the bitwise inverted binary code of the module;

8 - logical unit input;

9 - clock input of the device;

10 - device zeroing input;

11 - n-bit information output of the device;

12 - additional n-bit adder;

13 - the second n-bit register;

14 - the third n-bit register.

At the input 5 sequentially, synchronously with the clock pulses supplied to the input 9, a sequence of numbers {A (k); k = 1, 2,…} to be accumulated. Then it goes to the information input of the register 13 and the input of the first addend of the adder 12. At the input of the second addend of the adder 12, a bitwise inverted binary code of the module is supplied, over which the summation is carried out. A logical unit is fed to the transfer input of the adder 12 from the input 8 of the device, the output of the sum of the adder 12 is connected to the information input of the register 14, the output of which is connected to the n least significant bits of the input of the first addend of the adder 2. The lower n bits of the input of the second addend of the adder 2 are connected to the output of the register 4 , to the transfer input of the adder 2, as well as to the most significant bit of the input of its second addend, a logical zero is supplied from the input 6 of the device. The output of the register 13 is connected to the input of the second addend of the adder 1, the input of the first addend of which is connected to the output of the register 4 and the output 11 of the device. A logical zero from input 6 of the device is fed to the transfer input of the adder 1. The output of the sum of the adder 1 is connected to the second information input of the multiplexer 3, the first information input of which is connected to the n least significant bits of the output of the sum of the adder 2. The output of the multiplexer 3 is connected to the information input of the register 4, and its control input is connected to the output of the most significant bit of the sum of the adder 2. On the input of the most significant bit of the first term of the adder 2 is fed by a logical unit from the input 8 of the device. Clock inputs of registers 4, 13, 14 are connected to clock input 9 of the device, and zeroing inputs of registers 4, 13, 14 are connected to input 10 of device zeroing.

The device works as follows.

Before starting work, a pulse is sent to the input 10 of the device, which zeroes the contents of registers 4, 13, 14. Clock pulses are sent to the input 9 of the device, which synchronize the operation of the device. With each clock pulse, input 5 receives the code of the next n-bit number A (k) satisfying the condition 0 ≤ A (k) <P. It arrives at the input (D ₁ ... D _n ) of register 13 and the input (A ₁ ... A _n ) adder 12. At the input (B ₁ ... B _n ) of the adder 12 bitwise inverted code of the module P is fed, and at the transfer input - a logical unit. At the output of the sum (S ₁ ... S _n ) of the adder 12, a binary complementary code of the difference A (k) - P without a sign digit is formed. Since A (k) <P, the difference A (k) - P is always negative, therefore its sign bit is equal to one. Upon arrival of the next clock pulse, the code of the number A (k) is written into register 13, and the code of the number A (k) - P without a sign bit is written into register 14. At the output of the sum (S ₁ ... S _n ) of the adder 1, the code of the number A (k) + S (k) is generated, where S (k) is the number written in register 4. At the output of the sum (S ₁ ... S _{n + 1} ) adder 2 forms a binary complementary code of the number A (k) + S (k) - P, and the bit S _{n + 1} determines the sign of the number. If A (k) + S (k) <P, then the difference A (k) + S (k) - P is negative and _{a logical unit is formed at the output of the most significant bit S n + 1 of the} sum of adder 2, under the influence of which on the output of multiplexer 3 the second input (Y ₁ ... Y _n ) is commuted, and the code of the number A (k) + S (k) arrives at the information input of register 4, which is written into register 4 by the next clock pulse.

If A (k) + S (k) ≥ P, then the difference A (k) + S (k) - P is greater than or equal to zero, therefore, at the output of the most significant bit S _{n + 1 of the} sum of adder 2, a logical zero is formed, and at the output the multiplexer is switched to its first input (X ₁ ... X _n ).

The information input of register 4 receives the code of a non-negative number A (k) + S (k) - P, which is written into register 4 with the next clock pulse.

Thus, at the output of the register 4 and, accordingly, the output 11 of the device, the code of the next element of the output sequence {S (k); k = 1, 2, ...}

(1)

(1)

Let us show that the values of the elements of the sequence {A (k); k = 1, 2, ...} is less than P.

After the arrival of the zeroing pulse, the codes of zero numbers are set at the outputs of registers 4, 13, 14. At the inputs and outputs of multiplexer 3, codes of zero numbers are also set, therefore, upon arrival of the first clock pulse, the number S (1) = 0 is written to register 4.

If we assume that S (k) <P, then, taking into account that A (k) <P, the inequality A (k) + S (k) - P <P is true. Therefore, in accordance with formula (1), S ( k + 1) <P. According to the method of mathematical induction, all elements of the sequence {S (k); k = 1, 2, ...} is less than P.

According to the definition of the sum modulo P

This means that the claimed device implements the function of an accumulating adder modulo P, where P is an arbitrary natural number from the interval [2, 2 ⁿ - 1].

The increase in performance is carried out due to the simultaneous calculation of the numbers A (k) + S (k) and A (k) + S (k) - P, while in the prototype device, the number A (k) + S (k) is first calculated and then the number A (k) + S (k) - P.

REALIZATION

To evaluate in practice the gain in speed, simulation was carried out in the Quartus II automatic design system using the EP2C8F256I8 programmable logic integrated circuit (FPGA) of the Altera Cyclon II family (analogue of the domestic FPGA 5578TC024).

The number P = 30,000 was chosen as the module over which the summation is carried out, which corresponds to n = 15.

The simulation result showed that the maximum possible clock frequency of the prototype device is 135 MHz, and the claimed device is 190 MHz. Thus, the performance gain is 1.4 times.

SOURCES OF INFORMATION

1. Reference book on integrated circuits / n B.V. Tarabrin, S.V. Yakubovsky, N.A. Barkanov and others; Ed. B.V. Tarabrina. - 2nd ed., Rev. and add. - M: Energy, 1981. - 816 p., Ill., Fig. 5-250, p. 741.

2. Puhalskiy G.I., Novoseltseva T.Ya. Design of discrete devices on integrated circuits: Handbook. - M .: Radio and communication, 1990. - 304 p .: ill., Fig. 4.80, p. 268.

3. Naumkina L.G. Digital circuitry. Lecture notes on the discipline "Circuitry" - M .: "Gornaya Kniga". Publishing house of the Moscow State Mining University, 2008, Fig. 6.9, p. 228.

4. Patent RU 2 500 017 C1. Accumulator modulo. Published on November 17, 2013. Bul. No. 33.

Claims (1)

A high-speed accumulating adder modulo an arbitrary natural number, containing an n-bit adder, a multiplexer and a register, as well as an (n + 1) -bit adder, the n least significant bits of the sum output of which are bitwise connected to the first information input of the multiplexer, the second information input of which is connected to the output of the sum of the n-bit adder, and the multiplexer output is connected to the information input of the register, the output of which is connected to the input of the first addend of the n-bit adder and is the information n-bit output of the device, the clock input of the register is the clock input of the device, and the register zeroing input is the input zeroing the device, while a logical zero is fed to the transfer input of the n-bit adder, characterized in that an additional n-bit adder, as well as the second and third n-bit registers are introduced into it, and the clock inputs of the registers are connected to the clock input of the device, and register reset inputs are connected s with the device zeroing input, the output of the second n-bit register is connected to the input of the second term of the n-bit adder, and the information input of the second n-bit register is the n-bit information input of the device and is combined with the input of the first term of the additional adder, while the input of the second term of the additional adder, the bitwise inverted binary code of the module over which the summation is carried out is fed, a logical unit is fed to the transfer input of the additional adder, and its output of the sum is connected to the information input of the third register, the output of which is bitwise connected to the n least significant bits of the first term (n + 1 ) -bit adder, the lower n bits of the input of the second addend of the (n + 1) -bit adder are bitwise connected to the register output, while a logical zero, on the most significant bit of the input of the first the summand of the (n + 1) -bit adder is supplied with a logical unit, and the most significant bit of its output of the sum is connected to the control input of the multiplexer.

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