RU2170490C1 - Pulse generator with digital tuning of period - Google Patents

Abstract

FIELD: pulse generation. SUBSTANCE: pulse generator that may be used for digital phase synchronization has inverter, sectionalized delay line, multiplexer, and period digital code converter. EFFECT: enlarged frequency tuning range. 2 cl, 1 dwg

Description

 The invention relates to techniques for generating electrical pulses, in particular to pulse generators with electronic period control.

 To generate pulses with standard logical voltage levels, devices based on an inverter with feedback through a delay line are widely used [1, 2]. However, the known pulse generators do not provide for the possibility of frequency control electronically. A pulse generator [3] is also known, which contains an inverter, capacitors and NAND elements with an open collector, in which the inverter feedback circuit in the form of a corresponding capacitor and an NAND element is assigned by supplying a logical unit to the second input of the selected NAND gate. Due to this, in this analogue, digital control of the pulse period is provided. The disadvantages of this analogue are the low stability of the period, which is determined by the capacitance of the capacitor and the input currents of the logic elements, as well as the fact that the control digital code should not be an ordinary binary code, but a unitary code "1 of N".

 Of the known analogues, the pulse generator [4] is closest in technical essence to the present invention, it contains a series-connected inverter and a partitioned delay line, connected to the inverter output by the output, and many delay line taps directly and through additional inverters connected to the corresponding information inputs of the multiplexer.

 In the prototype device, frequency tuning is performed by monotonously changing the address code of the multiplexer, while the multiplexer goes through the delay line taps that are switched to its output. Changing the address code is achieved by turning on the accumulating adder (digital integrator) at the input of the device. Due to this, the period and, therefore, the frequency of the pulses at the output of the multiplexer are variable and depend on the rate of change of the address code. Thus, in the prototype device, period restructuring is achieved in an indirect way by affecting the phase of the pulses. Associated with this is its drawback, which lies in the relatively narrow range of period adjustment.

 The purpose of the present invention is the expansion of the frequency tuning range.

 As in the prototype device, the generation of pulses in the device according to the present invention is provided due to the feedback of the inverter through the partitioned delay line. Unlike the prototype, the delay time in the feedback circuit is controlled by a controlled selection of the tap of the partitioned delay line, the signal from which is used as the feedback signal.

 To achieve this goal, an additional block for converting a digital period code is introduced into a pulse generator with digital period adjustment, containing a series-connected inverter and a partitioned delay line, the taps of which are connected to the corresponding information inputs of the multiplexer. The specified unit is connected by outputs to the corresponding address inputs of the multiplexer, the first input to the first tap of the partitioned delay line, and the remaining inputs to the corresponding input terminals of the digital period code. In this case, the multiplexer output is connected to the inverter input.

 The period digital code conversion unit is made in the form of a subtractor, the input of a one-bit subtracted AND-NOT element connected to the output, in which one input is the first input of the period digital code conversion unit. The other input of the AND-NOT element and the inputs of the multi-bit reducible subtractor constitute the group of the remaining inputs of the block for converting the digital period code.

 As a partitioned delay line, both an electromagnetic delay line and a delay line operating on other physical principles can be used, for example, a plurality of electronic delay elements connected in series.

 The drawing shows an electrical functional diagram of a pulse generator with digitally adjustable period according to the present invention.

 The pulse generator circuit with digital period adjustment shown in the drawing includes a series-connected inverter 1 and a group of delay elements 3 forming a sectioned delay line 2, as well as a multiplexer 4 connected by its information inputs to the corresponding taps of the partitioned delay line 2. Additionally introduced block 5 conversion of the digital code of the period is connected by its outputs to the address inputs of the multiplexer 4, the first input of this block is connected to the first tap of the partitioned delay line 2, and the rest of the inputs to the input terminals 8 of the digital period code.

 Block 5 conversion of the digital code of the period is made in the form of a subtractor 6, the input of a single-bit subtracted connected to the output of the element type 7 AND-NOT, in which one input is the first input of the conversion unit of the digital code of the period. The other input of the AND element and the inputs of the multi-bit reducible subtractor 6 comprise a group of the remaining inputs of the digital period code conversion unit 5.

 The output terminal 9 of the device is connected to the output of the multiplexer 4, the outputs of the sectioned delay line 2 can also serve.

If the partitioned delay line 2 consists of 2 ⁿ sections, i.e. contains 2 ⁿ delay elements 3 and has 2 ⁿ taps, the device must have (n + 1) input terminals 8 of the digital period code. Subtractor 6 is n-bit. In a preferred embodiment, the subtractor 6 is made in the form of n semi-subtractors connected in series along the signal propagation chain of the loan [5].

 For definiteness, let n = 3. Then eight taps of the partitioned delay line 2 are connected to the information inputs of the multiplexer in the order of increasing the serial numbers of taps so that, for example, the first tap is connected to the input of multiplexer 4 with number 0, and its eighth tap is to the input with number 7.

The binary number B = b _n b _n-1 ... b _{0 the} digital code of the period, taking values from 2 to (2 ^{n + 1} -1), is fed to the input terminals 8-4, 8-3, 8-2, 8 -1, and on clip 8-1 comes its least significant bit. For any value of B, the multiplexer 4 connects to the input of the inverter 1 one of the taps of the partitioned delay line 2, which provides a pulse generation mode at the output terminal 9 and at all taps of the delay line 2.

/ В течение отрицательного полупериода импульса на первом отводе линии 2 задержки на выходе элемента 7 И-НЕ образуется уровень логической "1" вне зависимости от значения b₀ на зажиме 8-1. За счет этого в течение формирования положительного полупериода импульса выходное число вычитателя 6, оно же адрес мультиплексора 4, равно

где b_nb_n-1...b₁ - значения старших разрядов цифрового кода B периода на входных зажимах 8-4, 8-3, 8-2, а

- инверсия его младшего разряда на входном зажиме 8-1. В течение формирования отрицательного полупериода импульса адрес мультиплексора 4, образуемый вычитателем 6, равен
A^- = b_nb_n-1...b₁-1. (2)
Число A⁺ определяет длительность положительного полупериода, так как сигнал с информационного входа именно с адресом A⁺ поступает на вход инвертора 1 в процессе формирования этого полупериода. Аналогично число A^- определяет длительность отрицательного полупериода генерируемых импульсов. С учетом описанного выше порядка соединения отводов секционированной линии 2 задержки с информационными входами мультиплексора 4 полный период генерируемых импульсов оказывается равным
T = T⁺+T^- = (A⁺+1)Δt+(A^-+1)Δt = (A⁺+A^-+2)Δt.(3)
где Δt - время задержки одной секции линии 2 задержки.During the positive half-cycle of the pulse at the first tap of the delay line 2, the element 7 AND-NOT forms at its output a logic level “1” if the value of the least significant bit b _{0 of the} digital code B of the period at input terminal 8-1 is zero and the logic level is “0 "if b ₀ = one, i.e. value is formed

/ During the negative half-cycle of the pulse at the first tap of the delay line 2 at the output of the element 7 AND-NOT, a logical level of "1" is formed regardless of the value of b ₀ at terminal 8-1. Due to this, during the formation of a positive half-cycle of the pulse, the output number of the subtractor 6, which is the same address of the multiplexer 4, is

where b _n b _n-1 ... b ₁ are the high-order values of the digital code B of the period at the input terminals 8-4, 8-3, 8-2, and

- inversion of its least significant bit at the input terminal 8-1. During the formation of the negative half-cycle of the pulse, the address of the multiplexer 4 formed by the subtractor 6 is
A ^- = b _n b _n-1 ... b ₁ -1. (2)
The number A ⁺ determines the duration of the positive half-cycle, since the signal from the information input with the address A ^{+ is} fed to the input of the inverter 1 during the formation of this half-cycle. Similarly, the number A ^- determines the duration of the negative half-cycle of the generated pulses. Taking into account the above-described order of connecting the taps of a partitioned delay line 2 with the information inputs of multiplexer 4, the total period of the generated pulses is equal to
T = T ⁺ + T ^- = (A ⁺ +1) Δt + (A ^- +1) Δt = (A ⁺ + A ^- +2) Δt. (3)
where Δt is the delay time of one section of the delay line 2.

Подставив это значение в (3), получим
T = BΔt. (5)
Таким образом, период T генерируемых импульсов пропорционален значению цифрового кода периода на зажимах 8 и период может перестраиваться электронным способом в пределах от 2Δt до (2ⁿ⁺¹-1)Δt.However, according to (1) and (2)

Substituting this value in (3), we obtain
T = BΔt. (5)
Thus, the period T of the generated pulses is proportional to the value of the digital period code at terminals 8 and the period can be electronically tuned in the range from 2Δt to (2 ^{n + 1} -1) Δt.

 The variable frequency pulse generator can be used in digital phase synchronization devices.

Literature
1. Dolgiy B.Yu., Eliseev A.B., Zagidulin R.Sh. Stable digital delay line. - Instruments and experimental equipment, 1987, N 1, p. 95, fig. 1.

 2. The device synchronization channel playback data. Auth. testimonial. N 1674245, CL G 11 B 27/00, H 03 L 7/00, BI 1991, N 32.

 3. The pulse generator. Auth. testimonial. USSR N 1267588, class H 03 K 3/027, BI 1986, N 40.

 4. A voltage controlled pulse generator. RF patent N 2103816, cl. H 03 L 7/00, 7/099, BI 1998, N 3.

 5. Tokheim R. Fundamentals of Digital Electronics. - M .: Mir, 1988, p. 219, fig. 9.9.

Claims (2)

 1. A pulse generator with digital period adjustment, comprising a series-connected inverter and a sectioned delay line, the taps of which are connected to the corresponding information inputs of the multiplexer, characterized in that a periodical digital code conversion unit is connected to it, connected by the outputs to the corresponding address inputs of the multiplexer, the first input - with the first tap of the partitioned delay line, and the rest of the inputs with the corresponding input terminals of the digital period code, while od multiplexer is connected to the input of the inverter.  2. The pulse generator with digital adjustment of the period according to claim 1, characterized in that the digital period code conversion unit is made in the form of a subtractor, the input of a one-bit subtracted AND-NOT element connected to the output, in which one input is the first input of the period digital code conversion unit moreover, the other input of the AND gate and the inputs of the multi-bit decreasing subtractor constitute the group of the remaining inputs of the block for converting the digital period code.