NL2022950B1

NL2022950B1 - Electrical Converter

Info

Publication number: NL2022950B1
Application number: NL2022950A
Authority: NL
Inventors: Everts Jordi; Valentijn Gerrits Thomas
Original assignee: Prodrive Tech Bv
Priority date: 2019-04-15
Filing date: 2019-04-15
Publication date: 2020-10-22
Also published as: US20220190744A1; EP3956972A1; US11881792B2; CN113812078A; TW202046622A; WO2020212278A1

Abstract

Electrical converter (10) for conversion between a three-phase AC signal and a DC signal, comprising three phase terminals (A, B, C), a ﬁrst and second DC terminal (P, N), a phase selector 5 (l l) for connecting the three phase terminals to a ﬁrst, a second and a third intermediate node (X, y, z), a ﬁrst buck circuit comprising a ﬁrst switch-node terminal (p) connected to the ﬁrst DC terminal and a second buck circuit comprising a second switch-node terminal (11) connected to the second DC terminal, said ﬁrst and second buck circuits converting a voltage at the ﬁrst, second and third intermediate node to a voltage between the ﬁrst and second DC terminal, said ﬁrst and second 10 buck circuits being connected in series between the ﬁrst and second intermediate node and comprising at least one actively switchable device connected between the common node (m) and the third intermediate node.

Description

Electrical Converter Technical field The invention relates to the field of electrical power conversion. In particular, the invention relates to an electrical converter and a method for converting electrical power.

Background art For example, when the battery of an electric vehicle is charged, the AC voltage from an electrical grid is converted by an electrical converter into a DC voltage which is then provided to the battery that is being charged. For example, an electrical converter may convert a three-phase AC voltage into a DC voltage between the terminals of a DC bus to which the high-voltage (e.g. 200-400 V) battery of the vehicle may be connected. Also wireless charging systems for electric cars, electric motor drives, or gradient amplifiers for Magnetic Resonance Imaging (MRI) scanners typically need such three-phase AC-to-DC conversion to create a high-voltage DC bus from which power can be drawn.

Usually the current that is drawn by the electrical converter from each phase of the three-phase grid, for example when a load draws power from the DC output of the electrical converter, needs to be substantially sinusoidal and substantially in phase with the sinusoidal voltage of that particular phase, resulting in a power factor that is substantially equal to one. Therefore, the three-phase AC- to-DC conversion advantageously requires a three-phase Power Factor Correcting (PFC) electrical AC-to-DC converter. Also low distortion, for example a low Total Harmonic Distortion (THD), of the current drawn from the grid is typically required for such PFC converters. Conventionally, when the voltage between the DC bus terminals is lower than the full-wave rectified AC voltage, electrical converters are used that comprise a boost-type PFC stage with, e.g, a 700 — 900 V DC output, which is connected in series with a DC-DC buck converter to generate the desired DC bus voltage. ¢.g., in the range of 200 — 400 V. Alternatively, buck-type PFC converters based on the 3“ harmonic active filter principle have been introduced as a single-stage alternative to these conventional two stage converters, reducing the number of conversion stages in order to achieve a higher overall energy conversion efficiency and a higher power-to-volume ratio (i.e. a higher power density).

For example, reference T.

Soeiro, T.

Friedli, J.

W.

Kolar, “SWISS Rectifier — A Novel Three- Phase Buck-Type PFC Topology for Electric Vehicle Battery Charging”. Proceedings of the 27th Applied Power Electronics Conference and Exposition (APEC 2012), Orlando Florida, USA, February 5-9, 2012, further referred to as [REFERENCE 1] introduces an electrical converter that uses the 3" harmonic active filter principle and that is adapted for single-stage buck-tvpe three- phase PFC AC-to-DC conversion with DC-bus voltage levels that are lower than the full-wave rectified AC voltage, e.g., in the range of 200 — 400 V.

The electrical converter comprises a phase selector for converting a three-phase AC input voltage into intermediate voltages at an upper intermediate node, a lower intermediate node and a middle intermediate node.

An output stage with two DC-DC buck circuits converts the intermediate voltages into a DC output voltage.

In such existing embodiments the middle intermediate node is connected to the common node of the two DC-DC buck circuits.

A disadvantage of the single-stage buck-type PFC converter based on the 3% harmonic active filter principle as presented in Fig. 1 of [REFERENCE 1] is that the DC output terminals (p and n in Fig. 1 of [REFERENCE 1]) show a high-frequency common-mode voltage pulsation on top of low-frequency common-mode voltage pulsation.

Particularly the high-frequency common-mode output voltage pulsation may cause problems in the form of resulting high-frequency common- mode currents flowing to the load and, subsequently, to the protective earth (PE) connection of the electrical grid.

Therefore, an additional common-mode output filter is required to reduce these currents, which goes at the cost of converter volume, efficiency, and cost.

Another disadvantage of the single-stage buck-type PFC converter based on the 3 harmonic active filter principle as presented in Fig. 1 of [REFERENCE 1] is that interleaving of the output power stages, for example by paralleling two output stages having common connections (p, n and Y in Fig. 1 of [REFERENCE 1]), is impractical as there exists cross-coupling between the different stages.

This makes the design process, and possibly also the hardware implementation for an interleaved variant undesirably complex.

Summary of the invention It is an objective of embodiments of the present invention to provide an improved electrical converter and method for conversion between a three-phase AC signal and a DC signal, and in particular for converting a three-phase AC input into a DC output and/or for converting a DC input into a three-phase AC output, and more in particular a low cost electrical converter for three-phase buck-type PFC AC-to-DC conversion.

Preferably, embodiments of the electrical converter have one or more of the following advantages: the converter does not generate a high-frequency common-mode voltage pulsation in its DC signal and therefore does not require a large common- mode filter; the converter provides the possibility to operate the switching devices under zero- voltage-switching (ZVS) conditions in order to reduce switching losses and increase the efficiency and power density of the converter; the converter is simple to design; it is simple to extend the hardware design to an arbitrary number of interleaved stages; the converter has a high power-to- volume ratio (power density) which is enabled by little magnetic energy storage in the electrical converter; the converter generates low current distortions at the three phase terminals; the converter is able to draw substantially sinusoidal currents at the three phase terminals, at a power factor that is substantially equal to one.

According to a first aspect of the invention, there is therefore provided an electrical converter comprising three phase terminals, a first DC terminal and a second DC terminal, a phase selector, a first buck circuit and a second buck circuit. The phase selector is configured for connecting the three phase terminals to a first intermediate node, a second intermediate node and a third intermediate node of the electrical converter. The first buck circuit comprises a first switch-node terminal that is operably connected to the first DC terminal and a second buck circuit comprising a second switch-node terminal that is operably connected to the second DC terminal. The first and the second buck circuits are connected for converting a voltage at the first intermediate node, the second intermediate node and the third intermediate node to a voltage between the first and second DC terminal. The first and the second buck circuits are connected in series between the first intermediate node and the second intermediate node such that there is a common node of the first and second buck circuit. The first and second buck circuit comprise at least one actively switchable device connected between the common node and the third intermediate node.

Electrical converters feature a phase selector for converting a three-phase AC signal with three AC voltages provided at the three phase terminals of the electrical converter into an intermediate signal with three DC voltages provided between the first intermediate node, typically an upper intermediate node, the second intermediate node, typically a lower intermediate node, and the third intermediate node, typically a middle intermediate node. when the conversion is from AC to DC, or vice versa when the conversion if from DC to AC. The electrical converter further comprises a power stage comprising the first and second buck circuit. By having the first and second buck circuit connected in series with at least one actively switchable device connected between the common node and the third mtermediate node, as defined above, it becomes possible to have a third intermediate node, typically a middle intermediate node, which is not directly connected to the common node of the first and second buck circuit. In that manner, HF common-mode output signals may be reduced or avoided, such that a large common-mode output filter is not required.

Indeed, instead of being present at the common node, the HF signals will be “virtually blocked” by the at least one actively switchable device connected between the common node and the third intermediate node. Because a large common-mode output filter is not required, little magnetic energy is stored and a higher power-to-volume ratio (power density) may be obtained than in prior art solutions where a high amount of magnetic energy is stored in the output filter. In an exemplary embodiment, the electrical converter may be configured for AC-to-DC conversion, and the three-phase AC signal may be a three-phase AC mput voltage and the DC signal may be a DC output voltage having a voltage level that is lower than the full-wave rectified AC input voltage, e.g.. in the range of 200 — 400 V.

Preferably, the first buck circuit comprises a first device connected for interrupting a current flow between the first switch-node terminal and the third intermediate node, a second device connected for interrupting a current flow between the first switch-node terminal and the first intermediate node, and a third device connected for interrupting a current flow between the first switch-node terminal and the common node, wherein at least two of said first, second and third devices of the first buck circuit are actively switchable. Also, preferably, the second buck circuit comprises a fourth device connected for interrupting a current flow between the second switch-node terminal and the third intermediate node, a fifth device connected for interrupting a current flow between the second switch-node terminal and the second intermediate node, and a sixth device connected for interrupting a current flow between the second switch-node terminal and the common node, wherein at least two of said fourth, fifth and sixth devices of the second buck circuit are actively switchable.

More preferably, the first and fourth devices are actively switchable, and the above mentioned at least one actively switchable device connected between the common node and the third intermediate node comprises the first and the fourth devices. When the converter is used to convert a three-phase AC input into a DC output, preferably, at least the second and fifth devices are actively switchable. When the converter is used to convert a DC input into a three-phase AC output, preferably, at least the third and sixth devices are actively switchable. In that case, the above mentioned at least one actively switchable device connected between the common node and the third intermediate node comprises the third and the sixth devices. When it is desirable to do conversion in two directions, preferably the first, second, third, fourth, fifth and sixth devices are actively switchable, and the devices of the phase selector are also actively switchable, see further.

In that case, the above mentioned at least one actively switchable device connected between the common node and the third intermediate node comprises the first, third. fourth and the sixth devices. Further, by using devices that are actively switchable, a quasi-lossless zero-voltage switching is possible. This allows for power conversion at lower switching losses, and thus higher energy efficiency. Also, higher switching frequencies may be used in order to increase the power density (reduced size) and reduce the cost of the electrical converter. 5 Preferably, the first buck circuit is configured for allowing connecting the first switch-node terminal to any one of the first intermediate node, the third intermediate node, and the common node: and the second buck circuit is configured for allowing connecting the second switch-node terminal to any one of the second intermediate node, the third intermediate node, and the common node. This may be achieved using suitable control signals, typically pulse width modulation signals, for controlling the actively switchable devices of the first and second buck circuit. In other words, depending on the control signals, the first switch-node terminal will either be connected to the first intermediate node, or the third intermediate node, or the common node; and the second switch-node terminal will either be connected to the second intermediate node, or the third intermediate node. or the common node.

Preferably, the phase selector comprises devices, typically semiconductor devices, which are actively switchable for selectively connecting the third intermediate node to the three phase terminals. More in particular, the phase selector may be configured to connect the first intermediate node with the phase terminal having the highest voltage of the three-phase AC voltage, the second intermediate node with the phase terminal having the lowest voltage of the three-phase AC voltage, and the third intermediate node with the phase terminal having a voltage between said highest voltage and said lowest voltage.

According to an exemplary embodiment, the electrical converter comprises a controller configured to control at least one of the phase selector and the first and second buck converter. Preferably, the phase selector and the controller are configured such that switching of the devices of the phase selector is controlled according to a switching pattern in which: the phase terminal having a highest voltage is connected to the first intermediate node, the phase terminal having a lowest voltage is connected to the second intermediate node, and the phase terminal having an intermediate voltage between the highest voltage and the lowest voltage is connected to the third intermediate node. Preferably, the controller is configured to control the first buck circuit and the second buck circuit, such that a desired DC output is obtained between the first and the second DC terminal. More in particular, the controller may be configured to control a duty cycle and/or a switching frequency and/or a conduction sequence of control signals used to control the first buck circuit and the second buck circuit. The switching frequency is typically at least 10 times higher than the frequency of the three-phase AC signal. Preferably, the controller is configured to vary the duty cycle of a control signal for controlling the first actively switchable device substantially synchronously with the voltage of the third intermediate node. when the voltage between the third intermediate node and the midpoint of the three-phase AC voltage is positive, and to vary the duty cycle of a control signal for controlling the fourth actively switchable device substantially synchronously with the voltage of the third intermediate node, when the voltage between the third intermediate node and the midpoint of the three-phase AC voltage is negative; and/or to vary, e.g. increase or decrease, the duty cycle of a control signal for controlling the second and fifth actively switchable device substantially synchronously with the voltage of the first and second intermediate node, respectively. The switchable devices mentioned above are preferably semiconductor devices. It is noted that the term “semiconductor device” may refer to a single semiconductor component or a multiple semiconductor components connected in (anti-)parallel and/or in (anti-)series. For example, a semiconductor device which is actively switchable may comprise a transistor connected in anti- parallel with a diode. In a preferred embodiment, the first and second buck circuit further comprises a first filter inductor connected between the first switch-node terminal and the first DC terminal and a second filter inductor connected between the second switch-node terminal and the second DC terminal, respectively. Further, at least one filter capacitor may be provided, preferably a series connection of at least two filter capacitors, connected between the first and second DC terminals. The first and second filter inductor and/or the one or more filter capacitors may form a filter with a midpoint. In that case, the common node may be connected to the midpoint.

In a preferred embodiment, the electrical converter comprises a filter comprising capacitors which interconnect the intermediate first, second and third nodes, preferably in the form of a star or delta connection. When the capacitors are interconnected in a star connection, the common node may be connected to a star point of the star connection. In addition or alternatively, a filter comprising capacitors which interconnect the phase terminals may be provided, preferably in the form of a star or delta connection. In a preferred embodiment, the electrical converter comprises measurement means for measuring at least one of the DC signal, an electrical signal influencing the DC signal, an electrical signal influenced by the DC signal. The electrical signal may be a current or a voltage. The controller comprises a control loop configured to adapt at least one of a duty cycle, a switchmg frequency,

and a conduction sequence of control signals for controlling at least one of the first and second buck circuit based on the measurements performed by the measurement means.

Typically, the controller comprises a control loop configured to adapt at least one pulse width modulation control signal for controlling at least one of the first and second buck circuit based on the measurements performed by the measurement means.

Preferably, the measurement means comprises one or more of the following: a current measurement means for measuring at least one of a current between the first switch-node terminal and the first DC terminal and a current between the second switch-node terminal and the second DC terminal, a voltage measurement means for measuring voltages at the three phase terminals, a voltage measurement means for measuring a voltage between the second and first DC terminal, a current measurement means for measuring a current between the phase selector and one or each of the first, the third and the second intermediate node, a voltage measurement means for measuring a voltage of the common node.

Preferably, the control loop is configured to adapt a first pulse width modulation control signal for controlling the first buck circuit and a second pulse width modulation control signal for controlling the second buck circuit.

In an advantageous embodiment the controller may be configured to interleave the first and second pulse width modulation control signals.

According to a preferred embodiment, the phase selector comprises three selector legs for connecting one of the three phase terminals to the first intermediate node, the second intermediate node and the third intermediate node, wherein each of the three selector legs comprises a half bridge comprising semiconductor switches.

The phase selector may comprise a half-bridge configuration with diodes, typically six diodes.

Optionally, the diodes may be replaced with controllable semiconductor devices having bidirectional current flow capabilities.

This will allow using the electrical converter both for converting a three-phase AC input into a DC output and for converting a DC output into a three-phase AC input.

In other words, such embodiments allow for a bidirectional power flow through the converter.

According to a preferred embodiment, the first and second buck circuits may be scaled, e.g. when more power is needed.

This can be easily done by providing a number of first buck circuit legs or a number of first buck circuits connected in parallel, and by providing a number of second buck circuit legs or a number of second buck circuits connected in parallel.

When multiple first buck circuits are connected in parallel, such first buck circuits may be controlled in an interleaved way.

The same applies for multiple second buck circuits connected in parallel.

According to a further aspect of the invention, there is provided a battery charging system, in particular for charging a battery of an electric vehicle, comprising a power supply unit, the power supply unit comprising an electrical converter according to any one of the embodiments described above.

According to a further aspect of the invention, there is provided a wireless charging system, in particular for charging a battery of an electric vehicle, comprising a power supply unit, the power supply unit comprising an electrical converter according to any one of the embodiments described above.

According to a further aspect of the invention, there is provided an electric motor drive system, comprising a power supply unit, the power supply unit comprising an electrical converter according to any one of the embodiments described above.

According to a further aspect of the invention, there is provided a gradient amplifier comprising an electrical converter according to any one of the embodiments described above.

Also, there is provided a magnetic resonance imaging apparatus comprising the gradient amplifier.

According to yet another aspect, there is provided a method of converting between a three phase AC signal and a DC signal.

The method comprises the following steps: a step of converting between the three phase AC signal and an intermediate signal. wherein the intermediate signal is applied between a first intermediate node, a second intermediate node and a third intermediate node, wherein a voltage of the three phase AC signal is applied selectively to the first intermediate node, the second intermediate node and the third intermediate node; a step of converting between the intermediate signal and the DC signal using a first and a second buck circuit, wherein the first and the second buck circuits are connected in series between the first intermediate node and the second intermediate node such that there is a common node of the first and second buck circuit, wherein said converting comprises connecting the third intermediate node to a first switch-node terminal of the first buck circuit during a first time interval and to a second switch-node terminal of the second buck circuit during a second time interval, using at least one actively switchable device between the common node and the third intermediate node.

Preferably, the at least one actively switchable device of the first and second buck circuit between the common node and the third intermediate node is controlled using at least one pulse width modulation signal during said first and second time interval.

According to a preferred embodiment, a voltage of the three phase AC signal having a highest voltage is applied to the first intermediate node, a voltage of the three phase AC signal having a lowest voltage is applied to the second intermediate node, and a voltage of the three phase AC signal having an intermediate voltage between the highest voltage and the lowest voltage is applied to the third intermediate node.

According to a preferred embodiment, the converting between the intermediate signal and the DC signal using a first and a second buck circuit comprises: actively controlling a first switchable device connected between the third intermediate node and the first switch-node terminal and a fourth switchable device between the third intermediate node and the second switch-node terminal; actively controlling at least one of a second switchable device connected between the first intermediate node and the first switch-node terminal and a third switchable device connected between the common node and the first switch-node terminal; actively controlling at least one of a fifth switchable divide between the second intermediate node and the second switch-node terminal and a sixth switchable device between the common node and the second switch-node terminal.

Preferably, the converting between the intermediate signals and the DC signal using a first and a second buck circuit comprises controlling at least one of a duty cycle, a switching frequency, a conduction sequence of control signals to control the first and second buck circuit.

More preferably, the first switchable device is controlled with a pulse width modulation signal having a duty cycle which varies substantially synchronously with a voltage of the third intermediate node, during the first time interval, and the fourth switchable device is controlled with a pulse width modulation signal having a duty cycle which varies substantially synchronously with the voltage of the third intermediate node, during the second time interval; and/or the second and fifth switchable device are controlled with a pulse width modulation signal having a duty cycle which varies substantially synchronously with a voltage of the first and second intermediate node, respectively.

Preferably, the converting between the intermediate signals and the DC signal using a first and a second buck circuit comprises connecting the first switch-node terminal to any one of the first intermediate node, the third intermediate node, and the common node; and connecting the second switch-node terminal to any one of the second intermediate node, the third intermediate node, and the common node.

More preferably, the first buck circuit may be controlled for connecting the first switch-node terminal alternately to the first intermediate node, the third intermediate node, and the common node, during the first time interval, and for connecting the first switch-node terminal alternately to the first intermediate node and the common node, during the second time interval; and the second buck circuit may be controlled for connecting the second switch-node terminal alternately to the second intermediate node, the third intermediate node, and the common node, during the second time interval, and for connecting the second switch-node terminal alternately to the second intermediate node and the common node during the first time interval.

Preferably, the converting between the intermediate signals and the DC signal using a first and a second buck circuit comprises using a first filter inductor connected between the first switch-node terminal and a first DC terminal and a second filter inductor connected between the second switch- node terminal and a second DC terminal, respectively; and/or using at least one filter capacitor, preferably a series connection of at least two filter capacitors, connected between the first and second DC terminals.

Preferably, the converting between the intermediate signals and the DC signal is controlled by measuring at least one of the DC signal, an electrical signal influencing the DC signal. an electrical signal influenced by the DC signal, and by adapting at least one pulse width modulation control signal for controlling the first and/or second buck circuit based on the measured signals.

The measuring may comprise measuring one or more of the following: a current between the first switch-node terminal and a first DC terminal and/or between the second switch-node terminal and a second DC terminal (N), the three phase AC signal, a voltage between a first and second DC terminal, a current between one or each of the first, the third and the second intermediate node and the common node.

The adapting may comprise adapting a first pulse width modulation control signal for controlling the first buck circuit and a second pulse width modulation control signal for controlling the second buck circuit, and optionally interleaving the first and second pulse width modulation control signals.

Preferred features and technical advantages of the embodiments of the electrical converter apply mutatis mutandis for the embodiments of the method.

Brief description of the figures The accompanying drawings are used to illustrate presently preferred non-limiting exemplary embodiments of devices of the present invention.

The above and other advantages of the features and objects of the invention will become more apparent and the invention will be better understood from the following detailed description when read in conjunction with the accompanying drawings, in which: FIG. 1 is a circuit diagram of an exemplary embodiment of an electrical converter: FIGS. 2A-2K illustrate various charts plotting various voltages, currents and control signals in function of ot (°) for the exemplary embodiment of FIG. 1;

FIG. 3 illustrates various charts plotting various control signals, voltages, currents and control signals in function of time (microseconds), when ot = 40°, see reference numeral IIT in FIGS. 2A- 2K: FIG. 4 illustrates various charts plotting various control signals, voltages, currents and control signals in function of time (microseconds), when ot = 60°, see reference numeral IV in FIGS. 2A- 2K; FIG. 5 illustrates various charts plotting various control signals, voltages, currents and control signals in function of time (microseconds), when ot = 80°, see reference numeral V in FIGS. 2A- 2K; FIG. 6 illustrates various charts plotting various currents in function of ot (°) for the exemplary embodiment of FIG. 1; FIG. 7 is a circuit diagram of another exemplary embodiment of an electrical converter; FIG. 8 illustrates various charts plotting the same currents in function of ot (°) as in FIG. 6 but for the exemplary embodiment of FIG. 7; FIGS. 9, 10 and 11 show circuit diagrams of further exemplary embodiments of an electrical converter, FIGS. 12A and 12B show circuit diagrams of variants of the phase selector of FIG. 1; FIG. 13 illustrates schematically an exemplary embodiment of a control unit; FIG. 14 is a circuit diagram of vet another exemplary embodiment of an output stage of an electrical converter with two upper buck circuits connected in parallel and two lower buck circuits connected is parallel.

Description of embodiments FIG. 1 shows an electrical converter 10, referred to as the ‘PRODRIVE-SELECT RECTIFIER’, comprising two power stages 11, 12 in the form of a three-phase active phase selector 11 and an output power stage 12. Electrical converter 10 further comprises an input filter 13 placed between the phase selector 11 and the output power stage 12, and an output filter 14. Alternatively or additionally, an input filter (not shown) may be arranged upstream of the phase selector.

The electrical converter 10 is an AC-to-DC converter that has three phase terminals A, B, C which are connected to a three-phase voltage of a three-phase AC grid 20, and a first and second output DC terminal P, N, here an upper output terminal P and a lower output terminal N, which for example may be connected to a DC load 21 such as, for example, a high voltage (e.g. 200 — 400 V) battery of an electric car.

The phase selector 11 comprises three phase connections a, b, c that are connected to the three phase inputs A.

B, C, and three outputs x, y, z.

These outputs may be seen as a first intermediate node x, here an upper intermediate voltage node x, a second intermediate node y, here a lower intermediate voltage node y, and a third intermediate node z, here a middle intermediate voltage node z.

The phase selector 11 comprises, or consists of, three bridge legs 15, 16, 17 which each comprise two passive semiconductor devices (diodes Dg, and Dy, for leg 15, Dy, and Dy, for leg 16, Dex and Dy: for leg 17) connected in the form of a half bridge configuration, and three actively switchable semiconductor devices , here called selector switches Sg, . Spzp. and Scze. In the illustrated embodiment each selector switch comprises two anti-series connected actively switchable semiconductor components. Advantageously, each such switchable semiconductor component includes or is complemented by an anti-parallel diode. In this example, Metal Oxide Field Effect Transistors (MOSFETs) are used for the actively switchable semiconductor components, each including an internal anti-parallel body diode. In other embodiments an external anti-parallel diode may be provided.

The output power stage 12 comprises, or consists of, two stacked (i.e. series connected) buck bridge legs 18, 19 of first and second stacked buck circuits. The first upper buck bridge leg 18 comprises a first semiconductor device lp, a second semiconductor device 2p and a third semiconductor device 3p. The second lower buck bridge leg 19 comprises a fourth semiconductor device In, a fifth semiconductor device 2n and a sixth semiconductor device 3n. The second and fifth semiconductor device 2p, 2n is a buck switch (S;p for the upper buck bridge leg 18 and Sn, for the lower buck bridge leg 19). The switches Sy, and Sy of the buck bridge legs 18, 19 are actively switchable semiconductor devices. for example MOSFETs. The third and sixth semiconductor device 3p, 3n is a buck diode (Dy, for the upper buck bridge leg 18 and Dam for the lower buck bridge leg 19). The second and third semiconductor devices 2p, 3p and the fifth and sixth semiconductor devices 2n, 3n are connected in a half-bridge configuration. The switched middle node of the upper buck bridge leg 18 forms an upper switch-node terminal p which is connected to output P via a first buck inductor, here an upper buck inductor Ly, and the switched middle node of the lower buck bridge leg 19 forms a lower switch-node terminal n which is connected to output N via a second buck inductor, here a lower buck inductor L,,. The common node m of both, stacked, buck bridge legs 18, 19 is connected to the midpoint of the output filter 14 which comprises two output filter capacitors Cp Cmy that are connected in series between the upper output terminal P and the lower output terminal N.

The first and fourth semiconductor device Ip, In of the first and second buck bridge leg 18, 19 is an interconnection switch Sz; Dz and Dy, Sy. with bi-directional voltage blocking capability, that allows for connecting the switched middle node of the respective bridge, i.e. the upper switch- node terminal p for the upper buck bridge leg 18 and the lower switch-node terminal n for the lower buck bridge leg 19, with the middle intermediate voltage node z. The interconnection switch SzpDzp of the upper buck bridge leg 18 comprises an actively switchable semiconductor component Sy, €.g. a MOSFET, connected in anti-series with a diode Dz. creating a voltage bi- directional interconnection switch. The interconnection switch D,,,S,,, of the lower buck bridge leg 19 comprises an actively switchable semiconductor component Sz. e.2. a MOSFET, connected in anti-series with a diode D,,,, creating a voltage bi-directional interconnection switch.

The upper buck bridge leg 18 is connected between the upper intermediate voltage node x and the common node m, and is arranged in a way that current can flow from the upper intermediate voltage node x to the upper output terminal P via the switch Sp when the switch Sy, is closed (conducting, on state), current can flow from the middle intermediate voltage node z to the upper output terminal P via interconnection switch S;, D,,, when the switch Sy is closed (conducting, on state) and the switch Sy, is open (not conducting. off state), and current can flow from the common node m to the upper output terminal P via the diode Dy, when the switches Sx and S;; are open (not conducting, off state).

The lower buck bridge leg 19 is connected between the common node m and the lower intermediate voltage node y, and is arranged m a way that current can flow from the lower output terminal N to the lower intermediate voltage node y via the switch Sy, when the switch Sy), is closed (conducting, on state), current can flow from the lower output terminal N to the middle intermediate voltage node z via interconnection switch D,,,S,, when the switch Sz is closed (conducting, on state) and the switch S,,,, is open (not conducting, off state), and current can flow from the lower output terminal N to the common node m via the diode Dam when the switches Sy, and §,,, are open (not conducting, off state).

Advantageously, three high-frequency (HF) filter capacitors Cy, €, C,, which are part of the input filter 13, are interconnecting the intermediate voltage nodes x, y, z in the form of a star-connection. Generally, it is advantageous that the three capacitors Cy, Cy, Cz have substantially equal value in order to symmetrically load the AC grid. Advantageously, the star point of the three high- frequency (HF) filter capacitors Cy, Cy, € is connected to the common node m of both buck bridge legs 18, 19, and to the midpoint of the output filter 14.

The bridge leg of the phase selector 11 that is connected with the phase input terminal A, B, or C that has the highest voltage of the three-phase AC input voltage is switched in a way that the corresponding phase input terminal A, B, or C is connected to the upper intermediate voltage node x. To achieve this, the bridge leg connects the corresponding phase connection a, b, or ¢ with the node x via the upper diode Dax, Dp, Dex of the bridge leg, while the corresponding selector switch Sazar Shab, Scze Of the bridge leg is open (not conducting, off state). The bridge leg of the phase selector 11 that is connected with the phase input terminal A, B, or C that has the lowest voltage of the three-phase AC input voltage is switched in a way that the corresponding phase input terminal A, B, or C is connected to the lower intermediate voltage node y. To achieve this, the bridge leg connects the corresponding phase connection a, b, or ¢ with the node y via the lower diode Dya, Dy, Dy of the bridge leg, while the corresponding selector switch Sgza; Spzp, Scze of the bridge leg is open (not conducting, off state). The bridge leg of the phase selector 11 that is connected with the phase input terminal A, B, or C that has a voltage between the highest voltage and the lowest voltage of the three-phase AC input voltage is switched in a way that the corresponding phase input terminal A, B, or C is connected to the middle intermediate voltage node z. To achieve this, the bridge leg connects the corresponding phase connection a, b, or c with the node z via the selector switch S4z4, Spzp; Scze which is closed (conducting, on state).

In a three-phase AC grid with substantially balanced phase voltages v,, Vp, Vr, for example as shown in FIG. 2A, the three-phase AC input voltage (mains voltage) is converted into three intermediate DC voltages vy, zy, Vy which are shown in FIG. 2B and which are provided between the upper intermediate voltage node x, the lower intermediate voltage node y and the middle intermediate voltage node z. These DC voltages thus show piece-wise sinusoidal shapes.

The conversion of the three-phase AC input voltage into three intermediate DC voltages is the result of the operation of the phase selector 11, as explained above. The switching states (switch on 35 =1, switch off = § = 0) of the selector switches S4za. Spzp. Scze are shown in FIG. 2C. It can be seen that the switches are ‘on’ or ‘off’ continuously during whole particular 60° sectors (e.g. from 30° to 90°, from 90° to 150°, etc.) within the period of the AC mains voltage (360°; corresponds with a time period of 20ms for a 50 Hz grid frequency; also called a line cycle). Also the diodes of the phase selector are ‘conducting’ or ‘not conducting’ during whole particular sectors within the period (360°) of the AC mains voltage. Referring to FIG. 2A: - diode D,, conducts within 30° < wt < 150°, - diode Dy, conducts within 150° < wt < 270°, - diode Dx conducts within 270° < wt < 360° and 0° < wt < 30°,

- diode Dy4 conducts within 210° < wt < 330°, - diode Dyp conducts within 330° < wt < 360° and 0° < wt < 90°, - diode Dye conducts within 90° < wt < 210°, - switch S,,, conducts within 0° < wt < 30° and 150° < wt < 210° and 330° < wt < 360°, - switch Sp; conducts within 90° < wt < 150° and 270° < wt < 330°, - switch S;,. conducts within 30° < wt < 90° and 210° < wt < 270°. The combination of states (conducting / not conducting) of the switches and diodes is unique for every 60° sector of the three-phase AC input voltage and depends on the voltage value of the phase inputs A, B, C.

The sequence of the 6 unique states of the switches and diodes repeats itself every period (360°) of the AC mains voltage.

Seen from the viewpoint of the intermediate voltage nodes x, v, z towards the output terminals P, N. a DC-DC buck circuit (upper buck circuit) can be identified, having three input ports x, z, m and two output ports P, m. and comprising the upper buck bridge leg 18, the upper buck inductor L,. and the upper output capacitor Cp.

The voltage between input ports x and m of this upper buck circuit is the voltage Ver = Vr — Vm (% and v,, are shown in FIG. 2D) across capacitor Cy, the voltage between input ports z and m of this upper buck circuit is the voltage ve, = Vz — Vm (Vz and v,, are shown in FIG. 2D) across capacitor C,. and the voltage between output ports P and m of this upper buck circuit is the voltage Vom = vp — Vm (vp and v‚ are shown in FIG. 2D) across the upper output capacitor Cpm.

Vpm has a voltage value that is substantially equal to half the total DC bus voltage (Vom = Vpc/2). Seen from the viewpoint of the intermediate voltage nodes x, y. z towards the output terminals P, N, an ‘inversed’ (negative input voltage and negative output voltage) DC-DC buck circuit (lower buck circuit) can be identified, having three input ports v, z, m and two output ports N, m, and comprising the lower buck bridge leg 19, the lower buck inductor L,, and the lower output capacitor Cy.

The voltage between input ports v and m of this lower buck circuit is the voltage Vey = Vy — Vm (vy and vy, are shown in FIG. 2D) across capacitor €, the voltage between input ports z and m of this lower buck circuit is the voltage ve, = Vz — Vy (v, and v,, are shown in FIG. 2D) across capacitor €. and the voltage between output ports N and m of this lower buck circuit is the voltage Vym = vn — Vm (vy and v, are shown in FIG. 2D) across the lower output capacitor Cp, . Vym has a voltage value that is substantially equal to minus half the total DC bus voltage Vym = —Vpc/2).

By PWM modulation (pulse-width-modulation) of the control signals of switches Sy, and Szp of the upper buck circuit at a specified, possibly variable, switching frequency fs, the upper switch- node terminal p of the upper buck bridge leg 18 can be alternately connected to the upper intermediate voltage node x, the middle intermediate voltage z, or the common node m.

This results in a switched voltage v‚m between nodes p and m. the switched voltage vy, which may thus have three voltage levels.

The duty-ratios (i.e. the relative on-time within a switching period Ts = 1/fs) of the PWM-modulated control signals of the switches Sy, and S, define the average value (tpm) of voltage tpm within a switching period.

Control of these duty-ratios, and thus also control of the switching-cycle-averaged value (vy). allows to control the switching-cycle- averaged value (ij) of the current iz, in the upper buck inductor Ly. e.g. using a closed-loop PI (Proportional-Integrating) control structure.

Additionally, control of these duty-ratios allows to control the switching-cycle-averaged values (i,) and/or (i) of input currents i, and i,, of the upper buck bridge leg 18 by directing the inductor current í; to flow through Sy, (= ix) for a certain amount of time (i.e. during the on-interval of Sy), and through SzpDzp (= izp) for a certain amount of time (i.e. during the on-interval of 5,},). By PWM modulation (pulse-width-modulation) of the control signals of switches Sy, and Sy, of the lower buck circuit at a specified, possibly variable, switching frequency fs, the lower switch- node terminal n of the lower buck bridge leg 19 can be alternately connected to the lower intermediate voltage node y, the middle intermediate voltage z, or the common node m.

This results in a switched voltage v,,, between nodes m and n, the switched voltage Vn which may thus have three voltage levels.

The duty-ratios (i.e. the relative on-time within a switching period Ts = 1/5) of the PWM-modulated control signals of the switches S,,, and Sz define the average value (Vm) of voltage Vm within a switching period.

Control of these duty-ratios, and thus also control of the switching-cvcle-averaged value (vm). allows to control the switching-cycle- averaged value (i;,) of the current iz» in the lower buck inductor Ly, e.g. using a closed-loop PI (Proportional-Integrating) control structure.

Additionally, control of these duty-ratios allows to control the switching-cycle-averaged values {iy} and/or {i,,) of input currents i, and i, of the lower buck bridge leg 19 by directing the inductor current iy, to flow through Sy (= iy) for a certain amount of time (i.e. during the on-interval of Sy). and through D,,,S,,, (= izn) for a certain amount of time (i.¢. during the on-interval of Sz).

The current i, is equal to the sum of the input current i,, of the upper buck circuit and the input current i,, of the lower buck circuit (i, = izp + izn), which is also true for the switching-cycle- averaged values of these currents ({i,) = {izp) + (zn).

Generally, it can be said that the HF components of currents iy, iy, i, at the input of the output power stage 12 are largely filtered by HF filter capacitors Cy, Cy, Cz. As a result, the currents I'v, 1'y,i', at the output of the phase selector 11 are largely equal to the switching-cycle-averaged values (iy), { iy), { iz) of currents iy, iy, iz ie. i’, = (iy), I'y = (iy), i’; = biz).

The duty cycle ratios of the PWM control signals of the switches Sy, and Sz, are such that the switching-cycle-averaged value (%,m) is substantially equal to half the total DC bus voltage ((Vpm) = Vpm = Vpe/2; see FIG. 2D), while the duty cycle ratios of the PWM control signals of the switches Sy, and S,,, are such that the switching-cycle-averaged value (Vp) is substantially equal to minus half the total DC bus voltage (vm) = Vm = —Vpe/2: see FIG. 2D). This means that the switching-cycle-averaged voltages (i.e. the volt-seconds products) of both the upper buck inductor Lj and the lower buck inductor L,, are substantially equal to zero.

An example of the switching-cycle-averaged values (iy). (in) of currents ify, i}, in the inductors Ly, Ly, 1s shown in FIG. 2E. As can be seen. current iy, may be controlled to have a switching- cycle-averaged value equal to a requested DC output current ({i,,) = Ipc) while current iz, may be controlled to have a switching-cvele-averaged value equal to minus the requested DC output current ({iz) = —Ip¢).

Also shown in FIG. 2E is an example of the switching-cycle-averaged values (iy). (iy). (iz) of currents iy, iy, iz. As can be seen, these currents may be controlled to have piece-wise sinusoidal shapes. The currents i’, = (iy). i'y = (iy). i’, = (iz) at the output of the phase selector 11 are thus having the same piece-wise sinusoidal shapes and are transformed, i.e., as a result of the operation of the phase selector 11, into three sinusoidal AC phase currents i,, ip, ie which are shown in FIG. 2F, realizing Power Factor Correction (PFC) operation of the electrical converter 10.

FIG. 2G shows examples of the duty-cycles (with duty-cycle ut: 0 < Dut < 1, where Dut = 0 means continuously ‘off’ within a switching period Ts and Dut = 1 means continuously ‘on’ within a switching period Ts) of the switches and diodes (Sp. Szp; Dzp, Dmp) of the upper buck bridge leg 18 and FIG. 2H shows the duty-cycles of the switches and diodes (Spy. Snz, Daz; Dram)

of the lower buck bridge leg 19. These duty-cycles correspond with the examples of FIGS. 2A — 2F.

As can be seen from FIG. 2H, the duty-ratio of the control signal of switch Sz equals zero during certain intervals within the line cycle of the mains voltage, i... in these intervals the switch Sz is continuously open (not conducting). Conform FIG. 2B this is the case for the intervals where Vzy > Vrz.

This means that the current i;n (and its switching-cycle-averaged value (iz,)) is zero during these intervals, resulting in i’, = (iz) = {ip} (> 0) during these intervals, as can also be seen from FIGS. 21 and 2E.

Similarly, and as can be seen from FIG. 2G, the duty-ratio of the control signal of switch Sz, equals zero during certain intervals within the line cycle of the mains voltage, i.e. in these intervals the switch Sz is continuously open (not conducting). Conform FIG. 2B this is the case for the intervals where vz, < vz.

This means that the current iz, (and its switching-cycle-averaged value (izp)) is zero during these intervals, resulting in i’, = (i,) = (in) (< 0) during these intervals. as can also be seen from FIGS. 21, 2E.

As shown in FIG. 2G and 2H. the stepping down step performed by the upper and lower buck circuit comprises alternately (i.e. using a PWM signal) connecting the middle intermediate node z to an upper switch-node terminal p of the upper buck circuit during a first time interval T1 (where v,, > Vxz) and to a lower switch-node terminal n of the lower buck circuit during a second time interval T2 (where Vzy < Vz ). During the first time interval T1, the switch S,,, is continuously switched on and off with a switching frequency and a first varying duty cycle and the switch Sz is off.

During the second time interval T2, the switch Sp is off, and the switch Sz is continuously switched on and off with a switching frequency and a second varying duty cycle.

FIG. 2J shows the states of the switches Sy, and Sz of the upper buck bridge leg 18. and FIG. 2K shows the states of the switches 5,4 and Sz of the lower buck bridge leg 19. within a line cycle of the mains voltage.

The switches Syp, Szp, Spy, Snz are all PWM modulated at a frequency (i.e. the switching frequency fs; e.g. 100 kHz) that is substantially higher than the mains frequency (e.g. 50 Hz), as can be seen from the black-colored bars, indicating PWM modulation of the corresponding switch.

As mentioned above, switch Sz is continuously open (not conducting) during the intervals within the line cycle of the mains voltage where vz, > Vyz. while switch S,), is continuously open (not conducting) during the intervals within the line cycle of the mains voltage where v,, < vy.

FIGS. 3-5 show diagrams of currents, voltages, and switching signals on a milliseconds time axis, 1e. regarding three consecutive switching cycles of the bridge legs of the output power stage 12 of the electrical converter 10. Each switching cycle has a switching period 7: equal to 1/7. with fs the switching frequency. FIG. 3 corresponds with a time interval around wt = 40° within the line cycle of the mains voltage (see reference numeral III in FIGS. 2A-2K), FIG. 4 corresponds with a time interval around wt = 60° within the line cycle of the mains voltage (see reference numeral IV in FIGS. 2A-2K). and FIG. 5 corresponds with a time interval around wt = 80° within the line cycle of the mains voltage (see reference numeral V in FIGS. 2A-2K). For all FIGS. 3-5, the selector switches and diodes of the phase selector 11 are in the following switching states, see also FIG. 2C: - Switch Saza = 0 (off). diode Dy = 1 (conducting), diode D,, = 0 (blocking); phase connection a is connected with node x; - Switch Sp, = 0 (off), diode Dy = 0 (blocking), diode Dy, = 1 (conducting). phase connection b is connected with node y; - Switch Sg; = 1 (on), diode De, = 0 (blocking), diode Dye =0 (blocking). phase connection c is connected with node z.

The left columns (‘upper buck circuit’) of FIGS. 3-5 correspond with the operation of the upper buck circuit, while the right columns (‘lower buck circuit’) of FIGS. 3-5 correspond with the operation of the lower buck circuit. Each of FIGS. 3-5 shows: - the control signals of the switches and diodes Syp, Szp, Dzp, Dmp of the PWM-modulated upper buck bridge leg 18, and the control signals of the switches and diodes Spy, Sanz, Dz Dam of the PWM-modulated lower buck bridge leg 19: °1° means ‘on’ and conducting, and ‘0° means ‘off’ and not conducting; see first rows of FIGS. 3-5, - the voltage vy, across the upper buck inductor L, and the voltage v,, across the lower buck inductor L,,; see second rows of FIGS. 3-5, - the current i,p in the upper buck inductor L, (and the switching-cycle-averaged value, (ip) = Ipc. of this current), and the current iy, in the lower buck inductor L,, (and the switching-cycle-averaged value, {i;,) = —Ip¢, of this current); see third rows of FIGS. 3- 5, - the input current i, of the upper buck bridge leg 18 (and the switchmg-cycle-averaged value (i) of this current) and the input current i, of the lower buck bridge leg 19 (and the switching-cycle-averaged value (iy) of this current); see fourth rows of FIGS. 3-5, - the input current iz of the upper buck bridge leg 18 (and the switching-cycle-averaged value (ip) of this current) and the input current i,,, of the lower buck bridge leg 19 (and the switching-cycle-averaged value (i,,,) of this current): see fifth rows of FIGS. 3-5.

In the regarded time interval of FIG. 3. i.e, around wt = 40° within the line cycle of the mains voltage (see reference numeral II in FIGS. 2A-2K), vy, > vy, I’, = (iz) = (iy), and (izn) = 0,

1.e., the duty-ratio of the control signal of switch S,,, equals zero (switch Sz is continuously open; not conducting).

In the regarded time interval of FIG. 4. i.e, around wt = 60° within the line cycle of the mains voltage (see reference numeral IV in FIGS. 2A-2K), U; = vy, (iz) = 0, (izn) = 0, and i’, = (iz) = (zp) + (inz) = 0, ie, the duty-ratio of the control signals of switches S,,, and Sy, equals zero (switches S,,, and Sz are continuously open; not conducting).

In the regarded time interval of FIG. 5. i.e, around wt = 80° within the line cycle of the mains voltage (see reference numeral V in FIGS. 2A-2K), v,), < Verz. (iz) = 0, and i’, = (iz) = (inz). Le., the duty-ratio of the control signal of switch Sz equals zero (switch S,), is continuously open; not conducting).

In FIGS. 3-5, the semiconductor devices (switches and diodes) of the buck bridge legs 18, 19 of the output power stage 12 are sequentially conducting. For example, in FIG. 3 the conduction sequence of the switches and diodes of the PWM-modulated upper buck bridge leg 18 within a switching period Ts (= 1/fs) is as follows: - Interval I (iz: see left upper figure inset of FIG. 3): Sy, conducts while Sz, Dzp and Dp, do not conduct; - Interval 2 (int2; see left upper figure inset of FIG. 3). Szp Dzp conducts while Sy, and Dp, do not conduct, - Interval 3 (int3; see left upper figure inset of FIG. 3): Dp), conducts while Sxp and Szp Dzp do not conduct. During intervals 1, 2 and 3. S,,, is switched such that it is on when 57, Dzp or Dip conducts (i.e. whilst Dmp is off) and hence Dy, switches simultaneously with Dy, (see right upper figure inset of FIG. 3). This sequence repeats itself in the following switching period. It is noted that this is merely an example, and that the upper and lower buck circuits may operate independently of each other. For example, the operation of the first and second buck circuit may be interleaved, resulting in an overlap of the on-time of Din, and Dam. Different conduction sequences, possibly including more intervals, may also be used for the buck bridge legs. For example, in FIG. 3 a fourth conduction interval may be added to the conduction sequence of the switches and diodes of the PWM-modulated upper buck bridge leg 18 within a switching period Ty (= 1/fs}), which may resultin:

- Interval 1 (int! 7): Syp conducts while Sy, Dy, and Dm do not conduct, - Interval 2 (int2 '): Szp Dzp conducts while Sy, and Dm do not conduct. - Interval 3 (int3 '): Dpm conducts while Sp and Sy, Dzp do not conduct, - Interval 4 (ini4’): S,, Dzp conducts while Sp and Dm do not conduct.

As can be seen in FIG. 2G and 2H, the duty cycle of Syp (Dutssp) may be increased and decreased synchronously with the voltage vy, the duty cycle (Dutsy) of Sp, may be increased and decreased synchronously with the voltage —v,, the duty cycle of S,,, (Duts;p) may be increased and decreased synchronously with the voltage v, when v,, > Vz. and the duty cycle of Sz (Duts,,) may be increased and decreased synchronously with the voltage v, when v,, < Vyz.

FIG. 6 shows the currents iy. in. ix, iy. iz within a whole line cycle (360°) of the mains voltage. Also shown are the switching-cycle-averaged values (ir). (in), (ix). (iy). (iz) of these currents which correspond with the currents shown in FIG. 2E.

An advantage of the electrical converter 10 is that the DC output terminals (P and N) do not show a high-frequency common-mode voltage pulsation but only a low-frequency (e.g. 150 Hz) common- mode voltage pulsation as can be seen from FIG. 2D. Le. instead of being present at the output terminals, a high-frequency voltage pulsation manifests itself across the interconnection switches SzpDzp. DnzSnz of the respective buck bridge legs 18, 19, which act as very effective high- frequency voltage rejection elements (contrary to a passive filter element such as an inductor). This significantly reduces the amount of high-frequency common-mode currents flowing to the load. As a result, bulky common-mode output filters may be omitted and realization of a highly efficient, compact, and low-cost single-stage three-phase buck-type electrical power converter is made possible.

In order to minimize the Total Harmonic Distortion (THD) of the AC input current of the electrical converter, the high-frequency ripple of phase currents i,, i. i, is advantageously minimized, which is taken care of by the input filter 13.

Compared to embodiments where the first and second buck circuit are connected in parallel between the upper and lower intermediate node, embodiments of the invention have the advantage that the currents can be lower. Indeed, when two buck circuits are connected in parallel between the upper and lower intermediate node, wherein one buck circuit is connected to the positive node and the other one to the negative node, one buck circuit sees the reverse current of the other buck circuit, resulting in higher currents. This disadvantage is not present when two buck circuits are connected in series between the upper and lower intermediate node as in embodiments of the invention.

In FIG. 7, an electrical converter 200 is shown which differs from converter 10 in that the third and sixth semiconductor devices 3p, 3n are different: diodes Dy, Dam of the output power stage 12 of the converter shown in FIG. 1 have been replaced with controllable semiconductor switches Som, Smn.

In this case MOSFETs, in the output power stage 212. This allows for the inductor current {i;,) to also become negative within the conduction interval of Sp and for the inductor current {i;,) to also become positive within the conduction interval of S,,,,, which was not possible for the implementation of the output power stage 12 with diodes (Dy, Dam). As a result, quasi- lossless zero-voltage switching (ZVS) of all the semiconductor switches (Sxp- Szp: Spm Sny- Snz‚Smn) of the output power stage 212 is possible.

This allows for power conversion at lower switching losses and thus higher energy efficiency.

Also, higher switching frequencies may be used in order to increase the power density (reduced size) and reduce the cost of the electrical converter 200. FIG. 8 shows the currents i,7. in. tx. iy. iz within a whole line cycle (360°) of the mains voltage in case of ZVS operation of output power stage 212. Also shown are the switching-cycle-averaged values (ip). kim). (ix). (iy), (iz) of these currents which correspond with the currents shown in FIG. 2E.

The electrical converters 10 (shown in FIG. 1) and 200 (shown in FIG. 7) are unidirectional since the phase selector 11 and the output power stages 12, 212 contain diodes, only allowing power to be drawn from the electrical AC grid 20 and provide this power at the output to a load 21. FIG. 9, on the other hand, shows an electrical converter 300 that is bidirectional.

Electrical converter 300 differs from converters 10, 200 in that the diodes Das.

Dpx.

Dex.

Dya.

Dyp, Dye of the phase selector 11 and the diodes D,y.

Dmp.

Dnz.

Dam of the output power stages 12, 212 have been replaced with controllable semiconductor switches Sxa.

Sxp.

Sxc: Say: Spy.

Scy In the phase selector 311 and Spz.

Spm‚Szn,Smn In the output power stage 312. respectively.

It is noted that the electrical converter 300 may be used as a DC-to-AC converter with A, B, C being the output terminals and P, N the input terminals, as will be clear to a person skilled in the art.

This may be useful e.g. in applications using solar cells.

In FIG. 10 another electrical converter 400 is shown which differs from converter 10 in that the stacked buck bridge legs 18, 19 of the output power stage 412 are implemented using a different configuration of the first, second, third, fourth, fifth, and sixth semiconductor devices Ip, 2p. 3p. ln, 2n, 3n, providing the same functionality.

Also, in the electrical converter 400, the HF capacitors Cy, Cz, Czy which interconnect the intermediate voltage nodes x, y, z are connected in a delta configuration instead of a star configuration. In either electrical converters 10, 200, and 400, diodes may be replaced by actively switchable semiconductor devices to allow for bidirectional power flow of the electrical converter (as in the embodiment of FIG. 9). In either electrical converters 10, 200. 300, and 400, the HF capacitors Cy, Cy, Cz, Cx, Cz: Czy may be placed between the phase mput terminals A, B, C and the phase selector 11, 311, and interconnect the phase input terminals A, B, C in the form of a star or delta configuration. A combination of a set of HF capacitors which interconnect the intermediate voltage nodes x, v, z (as in electrical converters 10, 200, 300, 400) and a set of HF capacitors which interconnect the phase input terminals A, B, C, either in the form of a star or delta configuration, or a combination, may also be used.

In either electrical converters 10, 200, and 300, the HF capacitors Cy, Cy, Cz are connected in a star configuration. Alternatively, a delta configuration of these capacitors may be used in either of these electrical converters. In electrical converter 400, the HF capacitors Cyy, Cz, zy are connected in a delta configuration. Alternatively, a star configuration of these capacitors may be used. In FIG. 11 another electrical converter 500 is shown which differs from converter 200 in that the output filter 14 is replaced by an active output filter 514 that includes a boost stage. An active output filter may be used in the electrical converters of either FIG. 1, FIG. 7, FIG. 9, FIG. 10. FIG. 12A, 12B show different variants of the three-phase phase selector 11, which may be used in the electrical converters of either FIG. 1, FIG. 7, FIG. 9, FIG. 10, FIG. 11. In the exemplary embodiment of FIG. 12A, each actively switchable semiconductor device Sgza. Span, and Seq. comprises four diodes and a transistor with an anti-parallel diode. In the exemplary embodiment of FIG. 12B, each actively switchable semiconductor device Sgza. Spzp. and Seze comprises four diodes and a transistor with an anti-parallel diode, and the semiconductor device Sgza. Spzp. and Scze are included in the legs 15, 16, 17, respectively. It is noted that when the transistor of the semiconductor device Sgza. Spzp. and Sq, is off (i.e. does not conduct) current in the legs 15, 16, 17 can still flow through the diodes of the semiconductor device Sgza. Spzp- and Stze.

As shown in FIG. 1, in order to accomplish the piece-wise sinusoidal shapes of intermediate currents ix, iy, Íz, which results in three sinusoidal AC phase currents ig, i. ic. a central control unit 40 may be used which controls all the controllable semiconductor devices (switches) of the electrical converter 10, sending control signals to each switch via a communication interface 50. In particular, semiconductor devices Sgza: Spzp: Sezer Sxps Sny» Szp: Snz are controlled by controller

40. Furthermore, the control unit has measurement input ports 42, 43, 44, 45, 46, for receiving measurements of: e 42: the AC-grid phase voltages vg, Vp, Ve; e 43: the intermediate currents ix, iy, Íz: e 44: the inductor currents iy, zn; e 45: the DC bus voltage Vc; e 46: the DC bus mid-point voltage Vn: and an input port 41 to receive a set-value, which may be a requested DC output voltage Vp.

FIG. 13 shows a block diagram of an advantageous implementation of the central control unit 40 which is shown in a schematically way in FIG. 1. The electrical converter 10 is represented in FIG. 13 as a ‘single-wire’ equivalent circuit, wherein the annotations of the elements correspond with those given in FIG. 1. Three slashes in a signal line indicate the bundling of multiple signals, and may represent the transition to a vector representation. The goal of the control unit 40 is to control the output voltage Vpc to a requested set-value Vi, that is received from an external unit via input port 41, and to balance the voltage across the two output capacitors Cp, and Cy, for example by controlling the voltage across the lower output capacitor Cy to be substantially equal to half the DC bus voltage. Additionally, the current drawn from the phase inputs (a, b. c) needs to be shaped substantially sinusoidal and controlled substantially in phase with the corresponding phase voltage. As explained previously, this can also be achieved by controlling the intermediate currents ix, iy, iz. ie. instead of directly controlling the phase currents ig, ip, ic. to have piece-wise sinusoidal shapes.

The control of the output voltage Vpe is advantageously done using a cascaded control structure, comprising an outer voltage control loop 60 and inner current control loop 70. The set-value of the output voltage 1s input to a comparator 61 via input port 41, and is compared with the measured output voltage obtained from a measurement means 95 (for example comprising a low-pass filter). The output of comparator 61 is the control-error signal of the output voltage. which is further input to a control element 62 (for example comprising a proportional-integral control block) that outputs instantaneous set-values related to the phase currents and/or set-values related to the DC component of the inductor currents. These set-values are input to multiplier 63, and multiplied with signals that are obtained from calculation element 64 that outputs normalized instantaneous values of the phase voltages. The inputs of calculation element 64 are the measured phase voltages va, Vo. ve obtained from a measurement means 93 (for example comprising a low-pass filter). The output of the multiplier 63 are set-values ig, ip, iz, ip, ijn for the instantancous, for example low-pass filtered, phase currents i,, i, I., and the instantaneous, for example low-pass filtered, DC component of inductor currents iy, i. Set-values ig, ip, ic are shaped substantially sinusoidal and positioned substantially in phase with the corresponding phase voltages. Set-values ify, ijn are substantially constant and, as explained above, may represent the DC output current to a load 21 as itp = (ip) = Ipc and ijn = (in) = —Ipc. The set-values iz, tp, it, it, if, are input to the current controller 70 after passing an addition element 67 and a selection element 81 whose functions are further detailed in the following text.

The current controller 70 is split into five individual current controllers 71. 72, 73, 74, 75, wherein: e Individual current controller 71 is used for controlling the middle intermediate current iz. This control is done by PWM modulation of the controllable switches of output power stage 12. As a result of the operation of the phase selector 11, therewith, controller 71 controls the current of the phase input A, B, C, that has a voltage between the highest voltage and the lowest voltage of the three-phase AC voltage; e Individual current controller 72 is used for controlling the upper intermediate current í{. This control is done by PWM modulation of the controllable switches of output power stage 12. Typically, only the duty cycles of the PWM control signals are varied in a controlled manner, but optionally also the switching frequency and/or the conduction sequence of the switches may be varied. For example, the conductions sequence may be selected from a list of possible conduction sequences based on a measurement of the operation of the converter. Also, for example, the switching frequency may be chosen to improve or optimize the operation of the converter, and more in particular to guarantee zero voltage switching. As a result of the operation of the phase selector 11, therewith, controller 72 controls the current of the phase input A, B, C that has the highest voltage of the three-phase AC voltage: e Individual current controller 73 is used for controlling the lower intermediate current iy. This control is done by PWM modulation of the controllable switches of output power stage 12. As a result of the operation of the phase selector 11, therewith, controller 73 controls the current of the phase input A, B, C, that has the lowest voltage of the three- phase AC voltage.

e Individual current controller 74 is used for controlling the current in the upper inductor L, of output filter 14, connected to upper buck bridge leg 18. This control is done by PWM modulation of the controllable switches of output power stage 12.

e Individual current controller 75 is used for controlling the current in the lower inductor 1, of output filter 14, connected to lower buck bridge leg 19. This control is done by PWM modulation of the controllable switches of output power stage 12.

e Current controllers 74 and 75 jointly control the current supplied to a load 21.

Selector element 81 is used to send the set-values ig, iy, ic, iy, if, for the instantancous phase currents and inductor currents to the correct individual current controller 71, 72, 73, 74, 75 depending on the voltage value of the phase inputs A, B, C, resulting in intermediate current set- values ix,iy,iz and inductor current set-values ify, ij, for each individual current controller, wherein: e the set-value of the phase current of the phase input A, B, C. that has the highest voltage of the three-phase AC voltage is sent to individual current controller 72, resulting in set-value ix: e the set-value of the phase current of the phase input A, B, C, that has the lowest voltage of the three-phase AC voltage is sent to individual current controller 73, resulting in set-value iy: e the set-value of the phase current of the phase input A, B, C, that has a voltage between the highest voltage and the lowest voltage of the three-phase AC voltage is sent to individual current controller 71, resulting in set-value iz’.

e the set-value of the inductor current of upper inductor L,, of the output filter 14 is sent to individual current controller 74. resulting in set-value if, e the set-value of the inductor current of lower inductor L,, of the output filter 14 is sent to individual current controller 75, resulting in set-value í7.

In cach individual current controller the received set-value iy’, iy, 7", ify, ijn for the instantaneous current is input to a comparator, for example comparator 76 of individual current controller 71, and compared with the measured current iy measured: ly measured lzmeasurea + Úpmeasureds ijnmeasured Obtained from a measurement means 94 (for example comprising a low-pass filter) and from a measurement means 97. The output of the comparator is the control-error signal of the current, which is further input to a control element, for example control element 77 (for example a proportional-integral controller) of individual current controller 71. The output of current controller 70, which is for example a bundled combination of outputs of individual current controllers 71, 72, 73, 74, 75 is input to a PWM generation clement, for example PWM generation element 54. The PWM generation element generates the PWM-modulated control signals for the controllable semiconductor switches of the PWM-controlled bridge legs, i.e. the upper buck bridge leg 18 of the upper buck circuit and the lower buck bridge leg 19 of the lower buck circuit. These PWM- modulated control signals are sent to the appropriate bridge legs via communication interface 50. The selector switches of the phase selector 11 are either ‘on’ or ‘off during each 60° sector of the three-phase AC input voltage. depending on the voltage value of the phase inputs A, B, C, as explained above in connection with FIG. 2C. The control signals for the selector switches are generated by switch-signal generators 51, 52, 53 based on measured phase voltages obtained from a measurement means 93.

DC bus mid-point balancing is done by adding an offset value, by addition element 67, to the set- values ig, ip, ic, lip, iy for the instantaneous, for example low-pass filtered, phase currents ig, i, ic, and/or instantaneous, for example low-pass filtered, inductor currents iy, ín which are output by multiplier 63. The offset value is obtained by comparing the measured DC bus midpoint voltage obtained from a measurement means 96 (for example comprising a low-pass filter) with a set-value (for example Vp /2) using comparator 65 and feeding the error signal (output of comparator 65) into a control element 66.

The phase currents i, ip, I. shown in FIG. 2F are obtained by controlling the electrical converter 10 using such control unit 40 and control method detailed in the foregoing text. As explained above, the phase currents i,, ip, ie are indirectly controlled, ie., they are the result of the controlling of the intermediate currents iz, iy, iz (shown in FIG. 2E) and/or the inductor currents ip, iin and of the operation of the phase selector 11. The set-points for the intermediate currents ix, 1,1; are derived from set-values ig, iy, ic by selector element 81 based on the measured phase voltages.

In FIG. 14 another output stage 12 is shown in which the stacked series connected buck bridge legs 18, 19 of FIG. 1 are replaced by a first parallel connection of upper bridge legs 718 and a second parallel connection of lower bridge legs 719, wherein the first parallel connection of upper bridge legs 718 is connected in series with the second parallel connection of lower bridge legs 719. The first parallel connection of buck bridge legs 718 comprises two first semiconductor devices, two second semiconductor devices and two third semiconductor devices.

The parallel connection of second buck bridge legs 719 comprises two fourth semiconductor devices, two fifth semiconductor devices and two sixth semiconductor devices.

Each second and fifth semiconductor device is a buck switch (Sy, and Sip, for the upper buck bridge legs 718 and 5,41 and Spy, for the lower buck bridge legs 719). Each third and sixth semiconductor device is a buck diode (Dip: and Dippy» for the upper buck bridge legs 718 and Dam: and Damz2 for the lower buck bridge legs 719). The second and third semiconductor devices of the upper buck legs 718 and the fifth and sixth semiconductor devices of the lower buck legs 719 are connected in a half-bridge configuration.

The switched middle nodes of the upper buck bridge legs 718 form upper switch-node terminals pl, p2 which are connected to output P via respective first buck inductors, here upper buck inductors L;1. Ly, and the switched middle nodes of the lower buck bridge legs 719 form lower switch-node terminals nl, n2 which are connected to output N via respective second buck inductors, here lower buck inductors Ly, 1, 72. As in the embodiment of FIG. 1, the common node m of the stacked buck bridge legs 718, 719 is connected to the midpoint of the output filter 14 which comprises two output filter capacitors Cem, Cmm that are connected in series between the upper output terminal P and the lower output terminal N.

Each first and fourth semiconductor device of the buck bridge legs 718, 719 is an interconnection switch S,51Dzp1. DnziSnz1. Szp2 Dzp2 and D‚z25nz2 with bi-directional voltage blocking capability, that allows for connecting the switched middle node of the respective bridge. i.e., the upper switch-node terminal pl, p2 for the upper buck bridge legs 718 and the lower switch-node terminals nl, n2 for the lower buck bridge legs 719, with the middle intermediate voltage node z.

FIG. 14 illustrates that the output stage may be scaled by providing multiple first upper buck circuits in parallel and by providing multiple second lower buck circuits in parallel.

This may be useful, e.g. when more power 1s needed.

When multiple first and second buck circuits are connected 1n parallel as in FIG. 14, such respective first and second buck circuits may be controlled in an interleaved way.

The functions of the functional block labelled as “controller”. may be provided through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software.

When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which may be shared.

Moreover, explicit use of the term “controller” should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, digital signal processor (DSP) hardware, network processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read only memory (ROM) for storing software, random access memory (RAM), and non volatile storage.

Other hardware, conventional and/or custom, may also be included.

Whilst the principles of the invention have been set out above in connection with specific embodiments, it is to be understood that this description is merely made by way of example and not as a limitation of the scope of protection which is determined by the appended claims.

Claims

CONCLUSIONS

An electrical converter (10) for the conversion between a three-phase AC signal and a direct current (DC) signal, comprising: three phase terminals (A, B, C), a first DC terminal (P) and a second DC signal. terminal (N}, a phase selector switch (11) for connecting the three phase terminals to a first intermediate node (x), a second intermediate node (y) and a third intermediate node (z) of the electrical inverter, a first buck- circuit comprising a first switching node terminal (p) operatively connected to the first DC terminal (P) and a second buck circuit comprising a second switching node terminal (n) operatively connected to the second DC terminal (N), the first and second buck circuits are connected to convert a voltage at the first intermediate node (x), the second intermediate node (y) and the third intermediate node (z) to a voltage between the first and second DC terminals (P, N), characterized in that the honor ste and the second buck circuit are connected in series between the first intermediate node (x) and the second intermediate node (y) such that there is a common node (m) of the first and second buck circuits; wherein the first and second buck circuits include at least one actively switchable device connected between the common node and the third intermediate node.

The electrical converter according to claim 1, wherein the first buck circuit comprises: a first device (1p) connected to interrupt a current between the first switching node terminal (p) and the third intermediate node (z), a second device (2p) ) connected to interrupt a current between the first switching node terminal (p} and the first intermediate node (x); a third device (3p) connected to interrupt a current between the first switching node terminal (p) and the common node; at least two of the first, second, and third devices of the first buck circuit are actively switchable; and wherein the second buck circuit comprises:

a fourth device (1n) connected for interrupting a current between the second switching node terminal (n) and the third intermediate node (z), a fifth device (2n) connected for interrupting a current between the second switching node terminal (n) and the second intermediate node (y), and a sixth device (3n) connected to interrupt a current between the second switch node terminal (n) and the common node (m); wherein at least two of the fourth, fifth and sixth devices of the second buck circuit are actively switchable.

An electrical converter according to the preceding claim, wherein the first device and the fourth device are actively switchable, and the at least one actively switchable device comprises the first device and the fourth device.

Electrical converter according to claim 2 or 3, wherein at least one of the second device and the third device and at least one of the fifth device and the sixth device are actively switchable.

An electrical converter according to any one of the preceding claims, wherein the first buck circuit is configured to allow the connection of the first switching node terminal (p) to any of the first intermediate node (x), the third intermediate node ( z) and the common node (m); and wherein the second buck circuit is configured to allow the second switching node terminal (n} to be connected to any of the second intermediate node (vy), the third intermediate node (z) and the common node (m).

An electrical inverter according to any one of the preceding claims, wherein the phase selector switch comprises devices (Saza, So, Sczc) that are actively switchable for selectively connecting the third intermediate node to the three phase terminals.

An electrical converter according to any of the preceding claims, further comprising a controller (40) arranged to control at least one of the phase selector switch and the first and second buck switches.

An electrical inverter according to the preceding claim, wherein the phase selector switch (11) and the controller (40) are configured such that switching of the devices of the phase selector switch is controlled according to a switching pattern, wherein:

the highest voltage phase terminal is connected to the first intermediate node, the lowest voltage phase terminal is connected to the second intermediate node, and the phase terminal with an intermediate voltage between the highest voltage and the lowest voltage is connected to the third intermediate node.

An electrical converter according to claim 7 or 8, wherein the controller is arranged to control at least one of a duty cycle, a switching frequency and a conduction sequence of control signals used to control the first buck circuit and the second buck circuit. circuit.

An electrical converter according to any one of the preceding claims, wherein the first and second buck circuit further comprises a first filter inductor (Lp) respectively connected between the first switching node terminal (p) and the first DC terminal (P) and a second filter inductor ( Ln) connected between the second switch node terminal (n) and the second DC terminal (N).

Electric converter according to any of the preceding claims, further comprising at least one filter capacitor, preferably a series arrangement of at least two filter capacitors (CPm, CmN), connected between the first and second DC terminals (P, N).

An electrical converter according to the preceding claim, wherein the common node (m) is connected to a center of the series connection of the at least two filter capacitors.

An electrical converter according to any of the preceding claims, comprising a filter (13) comprising capacitors (Cx, Cy, Cz; Cxy, Cxz, Czy) connecting the intermediate nodes (x, y, z), preferably in the shape of a star or triangle connection.

An electrical converter according to the preceding claim, wherein the capacitors (Cx, Cy, Cz) are interconnected in a star connection and wherein the common node (m) is connected to a star point of the star connection.

An electrical converter according to claim 7, optionally in combination with any of the preceding claims, comprising measuring means (93, 94, 95, 96, 97) configured to measure at least one of the DC signal, an electrical signal that affects the DC signal, an electrical signal affected by the DC signal, and wherein the controller (40) includes a control loop (71-75) configured to adjust at least one of a duty cycle, a switching frequency, and a conduction sequence of control signals for controlling at least one of the first and second buck circuits based on measurements from the measuring means.

The electrical converter according to the preceding claim, wherein the measuring means comprises at least one of the following: a current measuring means (97) for measuring at least one of a current between the first switching node (p) and the first DC terminal (P ) and a current between the second switching node terminal (n) and the second DC terminal (N), a voltage measuring means (93) for measuring voltages at the three phase terminals, a voltage measuring means (95) for measuring a voltage between the second and a first DC terminal, a current measuring means (94) for measuring a current between the phase selector and one of the first, third and second intermediate node, a voltage measuring means (96) for measuring a voltage of the common node.

An electrical inverter according to any preceding claim, wherein the phase selector switch comprises three selector legs (16, 17, 18) for connecting one of the three phase terminals to the first intermediate node (x), the second intermediate node {y} and the third intermediate node (z), wherein each of the three selector legs includes a half bridge that includes switches (Dax, Dox, Dex, Dya, Dyb, Dye, Sxa, Sb, Sx, Say, Soy, Sey).

A battery charging system, in particular for charging an electric vehicle battery, comprising a power supply unit, the power supply unit comprising the electrical converter of any one of the preceding claims.

An electric motor drive system comprising a power supply unit, the power supply unit comprising the electrical converter according to any one of claims 1 to 17.

A gradient amplifier comprising the electrical transducer of any one of claims 1 to 17.

21. A method of converting between a three-phase alternating current (AC) signal and a direct current (DC) signal, comprising: converting between the three-phase AC signal and an intermediate signal, wherein the intermediate signal is applied between a first intermediate node (x ), a second intermediate node (y) and a third intermediate node (z), where a voltage of the three-phase AC signal is selectively applied to the first intermediate node (x), the second intermediate node (y) and the third intermediate node (z), converting between the intermediate signals and the DC signal using a first and second buck circuit, the first and second buck circuit being connected in series between the first intermediate node (x) and the second intermediate node (y), such that there is a common node (m) of the first and second buck circuit, said convert connecting the d the intermediate node (z) with a first switching node terminal (p} of the first buck circuit during a first time interval (T1) and with a second switching node terminal (n) of the second buck circuit during a second time interval (T2), using at least one actively switchable device between the common node and the third intermediate node.

The method of the preceding claim, wherein a voltage of the three-phase AC signal with a highest voltage is applied to the first intermediate node (x), wherein a voltage of the three-phase AC signal with a lowest voltage is applied to the second intermediate node (y), and a voltage of the three-phase AC signal with an intermediate voltage between the highest voltage and the lowest voltage is applied to the third intermediate node (z).

The method of the preceding claim, wherein the converting between the intermediate signal and the DC signal using a first and a second buck circuit comprises: actively controlling a first switchable device (1p) connected between the third intermediate node (z ) and the first switching node terminal (p) and a fourth switchable device (1n) between the third intermediate node (z) and the second switching node terminal (n); actively controlling at least one of a second switchable device (2p) connected between the first intermediate node (x) and the first switching node terminal (p) and a third switchable device (3p) connected between the common node (m) and the first switching node terminal (p); actively controlling at least one of a fifth switchable device (2n) between the second intermediate node (y) and the second switching node terminal (n) and a sixth switchable device (3n) between the common node (m) and the second switching node terminal {n ).

The method of any of claims 21 to 23, wherein converting between the intermediate signal and the DC signal using a first and second buck circuit comprises controlling at least one of a duty cycle, a switching frequency, a conduction sequence of control signals to control the first and second buck circuits.

A method according to any of claims 21-24, wherein converting between the intermediate signals and the DC signal using a first and a second buck circuit, connecting the first switching node terminal (p) to any of the first intermediate node (x), the third intermediate node (z) and the common node (m); and connecting the second switching node terminal (n) to any of the second intermediate node (y), comprising the third intermediate node (z) and the common node (m).