KR20140008531A - Self-activated front surface bias for a solar cell - Google Patents

Abstract

A self-activated front bias for photovoltaic cell assemblies was provided. The solar cell assembly includes a front electrical bias that is activated by electrical energy generated by the solar cell assembly. The front bias improves production efficiency for the solar cell assembly.

Description

[0001] SELF-ACTIVATED FRONT SURFACE BIAS FOR A SOLAR CELL FOR SOLAR CELLS [0002]

Cross-Reference of the Related Application

This application claims the benefit of U.S. Provisional Patent Application No. 61 / 488,628, filed May 20, 2011, the entirety of which is incorporated herein by reference.

Field

The present disclosure relates generally to the field of solar photovoltaics, and more particularly to conversion efficiency enhancement and electrical connections for back contact solar cells.

Most of the front surface (FS) - also called the sunny surface or sunnyside - the solar cell side that is exposed to the sun - is either an emitter or base (SC) that is not directly connected to the base. In one known SC design, the SC is referred to as a backside (BS) - also called a shady surface, a non-sunnyside surface - And a contact and wire for the base. In another known solar cell design, the solar cell has an emitter contact ("wraps through") that penetrates the solar cell and a base contact on the backside .

Solar cells often experience wasted energy near the front. For short wavelength light on crystalline silicon solar cells, light absorption and generation of electrons and holes (electron-hole pairs) occur very close to the front surface. In this region, if there are any electrical traps or recombination centers, the energy in the electrons or holes may be absorbed, degraded into heat, and thus wasted. Depending on the details of solar cell fabrication and passivation, it may be difficult to minimize these trap and recombination centers sufficiently.

Solar cells also often experience uneven illumination. Considering the large number of solar cells connected in series, one solar cell is shaded, but the other connected solar cell is brightly illuminated. In this case, the illuminated solar cells will produce more power than the shaded solar cells. Thus, power is generated by the brightly illuminated solar cell and dissipated in the shady solar cell. This may result in the shaded SC becoming hotter and suffering permanent damage. One solution to this problem is to provide a bypass diode in parallel with the solar cell or parallel to the series of solar cells.

A known solution for solar cell front surface degradation is to use a transparent conductive layer (or "gate") on the sunny surface of the solar cell to minimize recombination, Lt; RTI ID = 0.0 > a < / RTI > bias voltage or charge. Another known solution includes a gate on the sunlit surface of the solar cell to minimize recombination.

The known solution to this problem, frontal decomposition and unequal illumination is highly discrete. In other words, the solution to one problem does not provide a solution to the other.

summary

Thus, there has been a need for a solar cell assembly that provides a solution to frontal decomposition. In accordance with the subject matter indicated above, there is provided a solar cell assembly substantially eliminating or reducing disadvantages associated with previously developed solar cell assemblies.

In accordance with one aspect of the subject matter shown above, a self-activated front surface bias for photovoltaic solar cell assemblies is provided. The solar cell assembly includes a front bias that is activated by energy generated by the solar cell assembly. The front bias improves the generation efficiency for the solar cell assembly.

These and other aspects of the above-indicated subject, as well as additional novel features, will be apparent from the description provided herein. The intent of these summaries is not to provide a comprehensive description of the claimed subject matter but to provide a brief overview of the functionality of several subject matter. Other systems, methods, features, and advantages provided herein will be apparent to those skilled in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages included within this description be within the scope of any claims set forth below.

The features, nature, and advantages of the above-indicated subject matter may become more apparent from the following detailed description when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout the drawings:
FIG. 1A is a diagram illustrating an overall solar cell assembly according to the subject matter shown above; FIG.
1B is a diagram highlighting another embodiment of the solar cell front layer and the bias wire connection;
1C is a diagram illustrating a solar cell assembly embodiment of another embodiment according to the subject matter shown above;
Figures 2a to 2c are diagrams showing some embodiments of an integrated circuit according to the subject matter indicated above;
Figure 3a is a diagram illustrating a panel level embodiment of the subject matter shown;
3B is a diagram highlighting the integrated circuit embodiment of FIG. 3A and the solar assembly design.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

The following description is given for the purpose of illustrating the general principle of the present invention, not to be taken in a limiting sense. The scope of the present disclosure should be determined with reference to the claims. And, although described for a back contact back junction solar cell, those skilled in the art can apply the principles described herein for various solar cell designs.

Preferred embodiments of the present invention are illustrated in the drawings, such as numerals used to indicate corresponding parts of the various figures.

In solar cells, if electrons and holes (generated by incident solar photons) recombine on the front of the solar cell, these energies will be wasted. The subject matter presented above is a solution for preventing such waste by utilizing front-surface bias to improve the photo-voltaic conversion efficiency by reducing the effective front surface recombination velocity . On this front face, a bias voltage is applied which produces a front charge having the same polarity as the minority carriers. This reduces the concentration of minority carriers and results in an electric field that leaves the front side, reducing the recombination near the front face, pushing out the minority carriers - thus improving photoconductivity. For example, in a solar cell having n-type doping (or n-type base), holes are the minority carriers and positive bias is a minority carrier Thereby producing front surface positive charges, thereby reducing the effective front surface recombination velocity.

1A is a diagram showing an overall solar cell assembly 1000 including a semiconductor solar cell 1100. FIG. In the present disclosure, when the solar cell assembly operates, the front surface is illuminated by sunlight and the rear surface is shadowed. On the solar cell, the backside is shown as the emitter 1310 and the base 1320 and corresponding contacts and wires 1410 and 1420 (separated lines, but substantially disposed on the back surface of the solar cell deposited wires 1410 and 1420 ). The front side of the solar cell has five layers: a trapped charge layer 1210 (shown as a point dispersed in the cell); A texture layer 1220 ; A passivation layer 1230 ; A transparent conductive layer 1250 ; An outer window layer 1260 .

The transparent conductive layer 1250 may be a completely transparent or semi-transparent conductive layer-embodiments may include thin films of indium tin oxide, or zinc oxide with Al doping, or meshes of carbon nanotubes, or silver And a mesh of silver nanowires. It may also be feasible to use a very thin, transparent, and electro-conductive graphene layer. Additionally, the inner window layer 1250 and / or the outer window layer 1260 may be a transparent dielectric.

1A shows an integrated circuit chip 1500 (IC) that provides a bias circuit embodiment shown additionally in FIGS . 2A-2B . IC 1500 has several connections: emitter wire 1410 ; An emitter output wire 1411 ; A base wire 1420 ; A base output wire 1421 ; And bias wire 1430 . In this embodiment, a bias wire 1430 is connected to the transparent conductive layer 1250 on the front surface of the solar cell. It is surrounded by electrical insulation 1431 . This embodiment provides an ohmic coupling from the transparent conductive layer 1250 to the solar cell 1100 . The transparent conductive layer 1250 may provide an ohmic connection between the bias circuit and the solar cell. In addition, the IC circuit may also include a bypass circuit, indicated as 1520 in Figures 2A-2C . For example, a bypass diode, such as a bypass diode 1521 , may be coupled between the emitter and the base wire. This protects the solar cell against possible resistive overheating in the event that the sequence to which the solar cell is connected is illuminated non-uniformly.

1A and the following figures ( Figs. 1A-3B ) combine several graphical forms. The structure and the thin film of the solar cell 1100 do not show a scale but are exaggerated for the purpose of explanation. The emitter wire 1410 and the base wire 1420 are disposed substantially on the rear surface 1300 of the solar cell 1100 even though they are depicted as discrete lines. Also, the connections between the wires are indicated by dots - thus the wire lines intersected without dots are not connected. And, although not shown, the gate control signals are provided by other circuits.

FIG. 1A shows ohmic coupling between a transparent conductive layer 1250 and a solar cell 1100. FIG. Through bias wire 1430 , it dissipates at the same power as the current times bias voltage. It is preferable that this dissipated power is small as compared with the cell output power of the battery. In contrast, the embodiment shown in FIG . 1B has a capacitive coupling with a tiny current density and a tiny dissipation on average.

The transparent conductive layer 1250 should be sufficiently transparent so as not to sufficiently weaken the light reaching the solar cell. For example, optical attenuation of less than 2% is desirable. In addition, it must have sufficiently flat in-plane electrical conductivity, so that this layer is at approximately uniform voltage. For example, the voltage difference across the plane on the cell area should preferably be less than 0.05 volts. In addition, for embodiments with capacitive coupling (such as FIG. 1B ), the in-plane current and current density are very small, and thus the relatively small in- plane conductivity is sufficient.

1B is a chart highlighting another embodiment of the solar cell front layer and the bias wire connection. In this embodiment, the layer is slightly different: the trap charge layer 1210 ; A texture layer 1220 ; A passivation layer 1230 ; An inner window layer 1240 of dielectric; A transparent conductive layer 1250 ; External window layer 1260 . In contrast to FIG. 1A , this represents a capacitive coupling to the solar cell 1100 in a transparent conductive layer 1250 through a dielectric inner window layer 1240 .

Fig. 1C is a diagram showing a solar cell assembly 1000 including a semiconductor solar cell 1100 , another embodiment of the entire solar cell. Here, the emitter wire 1410 is directly connected to the bias wire 1430 and is connected to the transparent conductive layer 1250 for this reason. The bypass protection circuit 1520 may be a conventional bypass diode 1521 connected between the emitter wire 1410 and the base wire 1420 . The solar cell 1100 of FIG. 1C has a front surface with the layer shown in FIG . 1B , including an inner window layer 1240 .

Such a solar cell assembly of FIG. 1C may have lower costs because it uses lower fabrication costs and conventional assembly processes. In this IC design, the bias wire 1430 may be directly connected from the solar cell electrode (emitter 1310 or base 1320 ) having the same polarity as a minority carrier in the solar cell. This electrode wire may be an emitter wire 1410 or a base wire 1420 depending on the polarity of the minority carrier at the solar electrode and a bias wire is provided directly to the front transparent conductive layer 1250 wire, which may be either emitter wire 1410 or base wire 1420 depending on the polarity of the minority carriers in the solar cell, and bias wire directly on the front surface of the transparent conductive layer 1250) . In FIG. 1C , this is shown as the connection of bias wire 1430 to emitter wire 1410 . The solar cell electrodes are connected to emitter wires 1410 and base wires 1420 , which may be bus bars (e.g., flexible metal ribbons or printed circuits) . The bias wire 1430 may be an extension of a positive bus bar or a distinct wire and the connection may be a solder or an electro- May be used.

In one example, the solar cell semiconductor is n-type silicon and the base, and the emitter contact (electrode) and corresponding semiconductor junctions are all close to the back surface. This structure has sometimes been described as "back contact and back junction" or BCBJ solar cell (or interdigitated back contact or IBC). The emitter is a positive electrode connected to a positive bus bar connected to a separate bias wire connected to the transparent conductive layer (design schematically illustrated in FIG . 1C ). In a slightly different embodiment, the bias wire is a " through silicon via "or TSV. Similar biases are known for the design of semiconductor chips.

2A-2C are charts depicting some embodiments of IC 1500. Fig. Each of the embodiments shown provides a bias circuit 1510 and a bypass circuit 1520 .

2A , IC 1500 , bias circuit 1510 is coupled to two resistors 1511-1 and 1511-2 , connected between emitter wire 1410 and base wire 1420 , Is a voltage divider formed by a resistor. A bias wire 1430 is connected to the transparent conductive layer 1250 of the solar cell, but is insulated from other parts of the cell. The bypass circuit 1520 is a diode 1521 . In the IC design of Figure 2A , the bypass circuit 1520 is a semiconductor diode 1521 designed for a smaller forward voltage drop at a larger forward current.

In the integrated circuit embodiment of FIG. 2B , IC 1500 , bias circuit 1510 is a voltage divider formed by two transistors 1512-1 and 1512-2 . The bypass circuit 1520 is a transistor 1522 . Each transistor 1513-1, 1513-2, 1523 also has gates 1514-1, 1514-2, 1524 (not shown) coupled to separate control signals provided. In this embodiment, the bypass circuit 1520 includes a transistor 1522 designed for a high current with a small voltage drop when its gate 1524 is open. The IC chip 1500 is connected between the emitter 1410 and the base wire 1420 and the bias wire 1430 provides a voltage tap connected to the front transparent conductive layer 1250 . The control is inputted into the transistor gate (1514-1 and 1514-2), the voltage controlling the division ratio, and (The control inputs into the transistor gates, 1514-1 and 1514-2, adjust the voltage division ratio), therefore And the bias voltage connected to the front transparent conductive layer 1250 is adjusted. These control inputs are supplied by a digital input or an analog input via a digital to an analog converter.

The bias semantics and bypass semantics are preferably unified: one very small piece of semiconductor, its electrical "package ", and its assemblies are shared one tiny piece of semiconductor, its electronic "package ", and its assembly into the solar cell assembly). If necessary, it may include an auxiliary component for voltage step up. In mass production, the cost and size are only slightly better than those for bypass protection alone. (In high volume production, the cost and size are only slightly more than those for bypass protection alone.

In the integrated circuit embodiment of FIGS. 2A and 2B , there is a partial unification and a significant synergistic effect between the bias circuit 1510 and the bypass circuit 1520 . Both circuits may be connected to the solar cell emitter wire 1410 and the solar cell base wire 1420 , and one integrated circuit may provide both a bias and a bypass circuit. It is provided by the IC that enables both bias and bypass circuits to utilize electrical devices (wiring, resistors, diodes, transistors, electrical "packaging"), Costs are provided. Depending on the cost, an IC having both circuits may be fabricated directly into the semiconductor of the solar cell ( as shown in Figure 2C ). For example, both of the circuits may be fabricated in a very small area near the corners of the back side 1300 of the crystalline silicon solar cell 1100 .

In yet another embodiment, one bias circuit provides a bias to some solar cells (e.g., a solar panel as shown in Figures 3A-3B ). For example, some solar cells may be approximately equal in terms of optimum bias and operating conditions. The former is mainly changed depending on the manufacture of the battery, and the latter depends on the layout of the solar farm. If the solar cells are connected in series, each solar cell bias has to be canceled by the corresponding voltage. Thus, one bypass circuit can be used to protect the protection of a string of solar cells . ≪ / RTI >

In the integrated circuit embodiment of FIG. 2C , the IC of FIG. 2B is fabricated on the surface of the solar cell having the same front layer structure as shown in FIG . 1A . For example, the IC may be located in a very small area near the corner of the rear surface of the solar cell. A bias wire 1430 is connected from the bias circuit 1510 to the front transparent conductive layer 1250 . In one embodiment, the bias wire 1430 is separate, and in another embodiment, the bias wire 1430 and the bias wire insulation are integrated with the solar cell. This is similar to the "silicon penetration electrode" (TSV) in some IC chips.

This design may be particularly suitable for the fabrication of crystalline silicon solar cells where the bias circuit 1510 may be fabricated as part of the solar cell. Wiring, transistors 1512-1, 1512-2, and 1522 , (and / or resistors), including for example bias wire 1430 , are fabricated on the back side of the solar cell.

The bias circuit 1500 shown above is designed to provide a bias that optimizes the output power of the solar cell. For example, it may vary depending on the solar cell temperature, the output current, and the output voltage. In one embodiment, the bias circuit comprises: a bias current to / from the front coating; Solar cell temperature; Solar cell output current; Solar cell output voltage: < / RTI > Such measurements may be injected into the algorithm to provide the optimal bias voltage and the algorithm may be performed by analog and / or digital averaging.

In one embodiment, the bias circuit provides a negative feedback loop that adjusts the bias to optimize the output power. In yet another embodiment, the bias circuit effectively performs an open-loop algorithm to provide an optimal bias. In yet another embodiment, the bias circuit includes an open-loop algorithm to provide a feedback loop for fine-tuning for a precise optimal bias as well as a near-optimal bias. .

The solar cell design shown above may be self-powered by using the energy generated by the solar cell to operate the bias. When illuminated by sunlight, the solar cell directly generates power, including voltage and current, which may be used to activate the bias circuit shown above. The energy generated by the solar cell activates an electrical bias in the transparent conductive layer on the front surface of the solar cell. In the embodiment shown in FIG . 1A , there is an ohmic contact between the transparent conducting layer and the solar cell - thus, some of the generated energy activates the bias voltage and the bias current. In the embodiment shown in Fig . 1B , there is a dielectric inner window layer between the transparent conducting layer and the solar cell. Between these two layers is a capacitive coupling, but not a sustained current coupling - thus, some of the generated energy activates a bias voltage that includes the applied voltage with zero sustained current (Between these two layers are capacitive coupling but not sustained current coupling - thus, some of the generated energy activates a bias voltage applied to the nil sustained current).

Thus, the bias circuit and its power activation source are both within the solar cell assembly, which may be an external connection or an external power source to activate the bias circuit, There is no need for - the bias is self-activated. The electric energy generated by the solar cell activates a bias voltage. This is applied to the transparent conductive layer on the front side of at least one solar cell. This repels minority carriers, thus reducing surface recombination and thus improving photo-mechanical efficiency. The solar cell assembly shown may have outputs for only two external electrical connections, emitters, and bases (denoted as 1411 and 1421 , respectively). The solar cell assembly shown above is substantially compatible with the structure and assembly process for a typical solar cell panel.

In contrast, a seperately packaged bypass diode and a separately packaged biased circuit may not be compatible with a conventional packaged bypass diode alone. In addition, solar cell assemblies using three external electrical connections may not be compatible with conventional panels and their assembly processes.

In the embodiment shown in FIG . 1B , the bias voltage is applied to a series circuit comprising an inner window layer 1240 of the semiconductor material and dielectric of the solar cell. The inner window layer 1240 of the dielectric will fall into the substantial portion of the bias voltage and this reduced residual voltage will fall across the semiconductor material and contribute to the E-field, will reduce front surface recombination (FSR). Making the FSR sufficiently small will require a sufficiently large electric field in the semiconductor solar cell. A larger bias voltage may be required to compensate for this decrease, and it may be desirable that the bias voltage exceeds the voltage directly generated by the solar cell. For example, the solar cell voltage is in the range of 0.5 volts for a silicon solar cell, typically on the order of a bias voltage equal to or greater than 0.5 volts.

In a corresponding embodiment, the bias circuit may increase the voltage to a higher bias voltage at a voltage directly generated by the solar cell (the bias circuit may step up voltage, from the voltage directly generated by the solar cell, to a larger bias voltage). The meaning of the voltage increase includes DC to the DC-switched capacitor voltage regulator (Means to step up voltage include a DC to DC switched capacitor voltage multiplier). This is quite suitable for deriving a capacitive load formed by the transparent conductive layer, the inner window layer, and the semiconductor solar cell. This step-up circuit may be provided by the IC as well as a small auxiliary component such as a small capacitor.

Figure 3a is a chart showing a panel level embodiment of the subject matter shown; This design enables a larger bias voltage in each solar cell assembly, despite simpler bias circuitry within each integrated circuit. This larger bias voltage facilitates lower recombination and better photo-voltaic efficiency; However, this requires solar panels with less conventional construction and assembly processes.

The solar panel 3000 includes a panel-level power supply 3200 that provides a moderately large panel-level DC voltage, supplying a panel-level converter 3200. The panel- And a plurality of solar cell assemblies 1000 connected in an electrical series series along panel-level power wires 3100 . The panel-level converter 3200 provides a panel-level AC bias that provides a panel-level bias wire 3300 that is connected in electrical parallel to all solar cell assemblies.

Figure 3B is a chart highlighting the solar assembly design and integrated circuit embodiment of Figure 3A . Each of the solar cell assemblies has three external connections: two, emitter and base power outputs, as shown by the wires 1411 and 1421 on the solar cell backside 1300 , And the third is the panel-level bias wire 3300 through which an AC is supplied into the IC 1500 via an input capacitor 1515. [ Here, such as a rectifier 1516 , the bias circuit rectifies AC to pulse DC and arbitrarily regulates its voltage. This pulse DC is supplied to the bias wire 1430 supplied to the transparent conductive layer 1250 on the front surface 1200 of the solar cell 1100. [ The pulse DC is current-integrated by a capacitive load formed by the transparent conductive layer 1250 , the dielectric inner window 1240 , and the semiconductor solar cell 1100 , Smooth (voltage-smoothed).

Because the solar cell assemblies are connected in series, they have unequal DC offsets. The panel bias wire 3300 provides each solar cell assembly 1000 through a coupling capacitor 1515 that provides DC isolation-thus, one AC bias voltage is applied to the non-uniform DC Can provide a DC bias voltage on the offset voltage (one AC bias voltage can provide the DC bias voltages on top of the unequal DC offset voltages).

The panel-level embodiment has several advantages, including the following: the panel-level converter provides many solar cells, and thus a relatively low standardized cost [cost / watts of peak generated power of peak generated power); The panel-level DC provides an intermediate large voltage, thus facilitating the conversion to an AC with a suitable large voltage, thus facilitating a medium voltage DC bias and thus facilitating maximum PV efficiency do ; The panel level embodiment allows, for example, simple coupling capacitors, particularly simple bias circuits for each solar cell assembly.

However, the plate level embodiment has the advantage that fewer conventional panel and assembly processes are required, particularly for each solar cell assembly, the panel bias wire 3300 and the three connections (solar cell emitter wire 1410 , (Panel 1420 , and panel bias 3300 ).

Solar cell fabrication and passivation determine the density and type of the front proximity traps and recombination centers that determine the best bias. (Such as solar flux, battery temperature, and load resistance), as well as other factors such as surface charge, surface effect, various process details, and the average charge density in the traps May also serve to determine the bias. Thus, it may be difficult to accurately predict the average charge density, optimal bias, and battery efficiency improvement.

One theory suggests that the optimal bias should push out the minority carriers weakly. Thus, the optimal bias is close to the emitter voltage in the N-type semiconductor. Another theory suggests that the optimal bias should balance the trap charge to the frontal proximity. Thus, the optimal bias may be approximately intermediate between the emitter and the base. On the other hand, another theory suggests that the optimal bias should be intermediate between some voltage inside the base and some voltage inside the emitter.

In addition, another theory is that the front-side voltage will become more repulsive to the minority carriers, and then the recombination will be reduced. Thus, a sufficiently strong rebound will cause minor recombination. These theories repel and recommend a large bias voltage.

Thus, the optimum bias may be more easily initially determined by experiment. For example, an adjustable bias source (an adjustable voltage source, or a charge source or current source) as well as a corresponding meter and system for applying the specified solar flux, Use a battery. Therefore, the curve of the battery output current and voltage is measured. Set test conditions for solar flux and battery temperature. For example, 1,000 w / m ^ 2 and 25 C are defined standard test conditions, STC. It fixes one output parameter such as load resistance, output voltage, or output current. Then, the bias voltage is scanned, and the corresponding output power and cell efficiency are observed. This directly measures the bias providing the maximum output power, and the corresponding battery efficiency. Then, it measures the optimum bias and cell efficiency for each test condition in the relevant range of solar flux and battery temperature.

This measurement is then summarized by an algorithm that calculates the optimal bias as a function of the test condition. It converts this into an algorithm to calculate the optimal bias as a function of battery action parameters (such as battery voltage, battery current, battery temperature). As may be used to guide the bias circuit, such an algorithm translates as a digital circuit or into an analog circuit together with an analog output.

Another method for measuring the optimum bias is as follows. For each bias level, the curve of the battery voltage and current is measured and the maximum output power is calculated. After this is done for each bias level, the maximum output power vs. bias level is plotted. Therefore, the bias level that achieves the maximum output power is directly measured. By performing this under various test conditions, the optimum condition versus test condition is measured.

The DLTS (Deep Level Transient Spectroscopy) method is often used to measure traps and charges at or near semiconductor junctions between two terminals. This may be applied between the front transparent conductive layer and the emitter or base contact. DLTS is a transient method, and if there is a significant resistance or capacitance, then the resulting slow time constant is hard to see a transient effect (if and only if there is significant resistance or capacitance, the resulting slow time constants would obscure transient effects ). Therefore, use a solar cell with a very small area, a fraction of the ordinary solar cell possible. Direct measurement of the DLTS measurement and optimal bias may be used together to guide the construction of the theory to describe trapped charge and front bias effects.

The front optimal bias allows output power with higher efficiency compared to similar solar cells without front optimal bias. In the latter case, it is assumed that in the vicinity of the front, there are recombination centers, traps, and unbalanced net trapped charges pulling the minority carriers. Thus, some of the E-field lines extend from this unbalanced charge to the electrodes on the backside. Some photo-generated minority carriers will travel along this long-line toward the front unbalanced charge and recombination center, if the carrier energy is to be wasted.

It is assumed that there is a trap in the solar cell near the front where the average charge varies with solar flux and temperature (Suppose there are traps in a solar cell near the front surface with an average charge varies with solar flux and temperature. The bias circuit may be fabricated to balance a charge trap that is variable over the entire range of solar flux and temperature.

Additionally, a battery having an optimized bias with a solar cell, with an additional fixed charge, with an opposite polarity, and a cell without an optimized bias are compared. At certain solar fluxes and temperatures, these variable traps may balance by the fixed charge. However, as the solar flux and temperature change, the variable trapped charge that will result in a corresponding non-balance between the fixed charge and the variable charge trap will change. This provides photo-excited holes and a net charge that will dissolve the power collection from the electrons. Thus, the optimized front bias provided herein is an improvement using a fixed charge to balance the trap with temperature-dependent average charge.

Claims (10)

A photovoltaic solar cell assembly for generating electrical energy from light, the front surface electrical bias activated by the front for receiving light and the electrical energy generated by the solar cell assembly. Wherein the front electrical bias is to improve conversion efficiency for the solar cell assembly.
The method of claim 1,
A front surface receiving light;
A conductive layer positioned proximate to or directly on the front surface; And
A bias wire that is activated by at least one electrode on the solar cell, the electrode providing some of the electrical energy to the bias circuit, the bias wire being used to activate a front electrical bias. A bias wire for transferring energy to the transparent layer;
Further comprising, a photovoltaic solar cell.
The method of claim 1,
Wherein said front bias and said electrode have approximately equal voltages.
The method of claim 1,
Wherein the front bias is directly connected to the electrode, the electrode having the same polarity as minority carriers in the solar cell.
The method of claim 1,
The bias circuit further includes a control, wherein the control is to optimize front bias to reduce concentration of minority carriers near the front of the solar cell.
The method of claim 1,
Wherein said bias circuit further comprises a control, said control reacting to act on a state of said solar cell.
The method of claim 1,
And a bypass protection circuit coupled to the base and emitter electrodes on the solar cell.
The method of claim 1,
And a bias circuit connecting said at least one electrode on said solar cell to said bias wire.
The method of claim 1,
And a bypass protection circuit coupled to the base and emitter electrodes on the solar cell, wherein the bypass circuit is at least partially integrated with the bias circuit.
A solar panel comprising a plurality of photovoltaic solar cell assemblies for generating electrical energy from light, the solar cell assemblies being at least partially connected in series, and the at least one solar cell assembly providing light And a front bias activated by the front side for receiving and electrical energy generated by the at least two solar cell assemblies, wherein the front bias improves conversion efficiency for the solar cell assembly.

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