KR20000027237A - Address generating apparatus for driving data strobe signal in semiconductor memory device - Google Patents

Abstract

PURPOSE: An address generating apparatus for driving a data strobe signal in semiconductor memory device is provided to prevent the collis ion of an address by generating an address for selectively driving a data strobe signal in an appropriate timing. CONSTITUTION: A delay unit(100) responds to a signal(Casa6) and a signal(clkt4_lw) and delays a signal(ADD9) by one clock. A pass gate(101) responds to the signal(Casa6) and switches the delayed address signal(wt_dly) outputted from the delay unit(100). A pass gate(102) responds to a signal(Casa6_rd) and switches the signal(ADD9). A pass gate(103) is connected to the pass gate(101) and the pass gate(102) and responds to the signal(Casa6_rd), and then switches outputs of the pass gate(101) and the pass gate(102). A latch unit(104) latches an output signal of the pass gate(103). A pass gate(105) responds to a signal(Casa6_rw) and switches an output signal of the latch unit(104).

Description

Address generator for driving data strobe signals in semiconductor memory devices

The present invention relates to an apparatus for driving a data strobe signal in a semiconductor memory device, and in particular, an address generator for driving a data strobe signal in a double data rate (DDR) synchronous DRAM (DDR), which is a next-generation design technology. It is about.

As is well known, a synchronous DRAM (hereinafter referred to as SDRAM), which operates in synchronization with an external system clock, is widely used as a DRAM in semiconductor memory devices to improve operation speed. On the other hand, while conventional SDRAM uses only the rising edge of the clock, DDR SDRAM uses both the clock rising and falling edges, so that the faster operation speed can be realized. It is in great spotlight.

When writing to a data width of 4 or 8 in a DDR SDRAM having 16 bits of data input / output (DQ0-DQ15), 16-bit input data (hereinafter, referred to as din) is conventionally used. Is loaded onto all global inout lines (hereafter referred to as gio lines), and optionally written to the bank to load into the actual cell's data line, depending on the option (x4 or x8). . However, this conventional method causes unnecessary power waste because it drives data not actually written to the bank.

In addition, another conventional technique for solving the problems of the prior art receives a 16-bit din and generates only a corresponding data strobe signal (data strobe signal) in response to the addresses 9 and 11 of the 16-bit din Only the data is written to the gio line. However, such another conventional technique requires an address to be input in time according to an operation timing, but it is difficult to adjust the timing, and even if the timing is set, a problem arises that the address of the next operation cannot be caught in time and conflicts.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide an address generating apparatus which prevents address collision by generating an address for driving a data strobe signal selectively according to an option of data width at an appropriate timing. have.

1 is a circuit diagram of an embodiment of an address generator according to the present invention;

2 is a signal timing diagram for the address generation apparatus of FIG. 2 according to an embodiment of the present invention.

* Description of the main parts of the drawing

100: delay unit

101 to 103, 105: pass gate

104: latch portion

According to an aspect of the present invention, there is provided an address generator for driving a data strobe signal in a semiconductor memory device, the data strobe signal being responsive to a first signal and a clock signal enabled when a data read or write command is input. Delay means for receiving an address signal for driving and delaying one clock; Selecting means for selectively outputting the address signal and the one-clock delayed address signal output from the delay means in response to a second signal which is delayed by a predetermined clock than the first signal when the data read command is input; Latch means for latching an address signal output from said first selecting means; And timing adjustment of the address signal output from the latch means to generate a data strobe signal at the time of the data write command in response to a third signal that is delayed by a predetermined clock than the first signal when the data write command is input. And an output means for outputting the read address signal, wherein the timing-adjusted read address signal is outputted to generate a data strobe signal at the time of the data read command from the selection means when the data read command is received. It is done.

The address generating apparatus of the present invention receives and stores the address before the actual write start time, and controls the address path at the read and write time, respectively, in order to solve the problem of conflict with the subsequent operation, In successive writes, the switches are controlled separately to avoid overwriting the addresses.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is an exemplary circuit diagram of an address generation apparatus according to the present invention. In the drawing, the casatv6 signal is a signal enabled when a data read and write command is input, and the clkt4_lw signal receives an external clock clk and receives an internal clock generator. ADD9 represents an address number 9 for generating a data strobe signal. In addition, the casatv6_rd and casatv6_wt signals are enabled signals during read and write, respectively. The output signals gy9_rd and gy9_wt signals are properly timed address signal 9 at read and write and are used for generating the actual data strobe signal.

Referring to FIG. 1, the address generator of the present invention includes a delay unit 100 delaying ADD9 by one clock in response to a casatv6 signal and a clkt4_lw signal, and one clock output from the delay unit 100 in response to a casatv6_rd signal. A pass gate 101 for switching the delayed address signal wt_dly, a pass gate 102 for switching ADD9 in response to the casatv6_rd signal, and a pass gate connected to the pass gates 101 and 102 and in response to the casatv6_rd signal A pass gate 103 for switching the outputs from the gates 101 and 102, a latch portion 104 for latching the output from the pass gate 103, and an output from the latch portion 104 in response to casatv6_wt It consists of a pass gate 105 for switching, gy9_rd and gy9_wt are output from the pass gate (101, 105), respectively.

2 is a signal timing diagram of the address generator of FIG. 2 according to an embodiment of the present invention.

1 and 2, an operation of an embodiment of the present invention will be described.

When the write command is received, the casatv6 signal is enabled, and the ADD9 signal of “low” is input to the delay unit 100 in response to the enabled casatv6 signal (200). The ADD9 signal of " low " is outputted to the write address wt_dly delayed by one clock in synchronization with the next clkt4_lw signal (210). At this time, since the casatv6_rd signal is disabled because the write command is turned off, the path to which the non-delayed ADD9 enters is blocked because the pass gate 102 is turned off. On the other hand, the pass gates 101 and 103 are turned on by the disabled casatv6_rd signal, and the write address wt_dly output from the delay unit 100 is latched in the latch unit 104, and casatv6_wt is enabled in the next clock. When the pass gate 105 is turned on, the address latched by the latch unit 104 is output as gy9_wt (220). At this time, even if a new read command or a write command is continuously input before the latched address is output to gy9_wt, the address may be output to gy9_wt without being damaged through the structure. That is, when a new write command is received, the operation of the write command entered earlier is performed while the corresponding ADD9 is delayed by one clock through the delay unit 100, thereby avoiding address corruption by the continuous write command.

If the read command is continuously input after the write command, the path for the write command is blocked, and a new address by the read command is output to gy9_rd through the pass gate 102. At this time, the address of the previous write command is stored in the latch unit 104, and outputted by the casatv6_wt signal, so that an address conflict due to successive read commands does not occur.

Next, another address 11 for driving the data strobe signal may also be generated at an appropriately adjusted timing without an address collision through the address generator configured as shown in FIG. 1.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention as described above, the address is inputted and delayed by one clock, and the address paths of the read command and the write command are controlled respectively, so that an address for selectively driving the data strobe signal is appropriately selected according to the data width option. There is a distinctive effect that can be generated by timing to prevent address conflicts.

Claims (4)

An address generator for driving a data strobe signal in a semiconductor memory device, Delay means for receiving an address signal for driving the data strobe signal in response to a first signal and a clock signal enabled when a data read or write command is input, and delaying one clock; Selecting means for selectively outputting the address signal and the one-clock delayed address signal output from the delay means in response to a second signal which is delayed by a predetermined clock than the first signal when the data read command is input; Latch means for latching an address signal output from said first selecting means; And When the data write command is received, the timing signal is adjusted to generate a data strobe signal at the time of the data write command in response to the third signal being enabled by a predetermined clock delay than the first signal. An output means for outputting a write address signal, And a read-adjusted read address signal for outputting a data strobe signal during the data read command from the selection means when the data read command comes in. The method of claim 1, wherein said selecting means First transfer means for transferring a delayed address signal output from said delay means in response to said second signal; Second transfer means for transferring the delay-free address signal in response to the second signal; And Third transmission means connected to a common output terminal of said first and second transmission means, for transmitting an address signal from said common output terminal in response to said second signal, And the timing-adjusted read address signal is outputted from an output terminal of the first transfer means. The method of claim 2, wherein the first to third switching means, respectively An address generator, characterized in that the pass gate. The method of claim 1, wherein the output means, An address generator, characterized in that the pass gate.