KR19990061547A - Method and device for signal transmission in synchronization system - Google Patents

Abstract

The present invention relates to a signal transmission method and apparatus of a synchronization system. When adding a separate signal in a synchronization system receiving the same clock pulse, the logic of each system is modified to add a separate signal to an existing signal, By performing the encoding process on the transmitting side and converting the encoded signal into the original signal through the decoding process on the receiving side, it is possible to simply add the added signal without modifying the interface part between the existing systems or adding a new interface device. To send.

The signal transmission method of the synchronization system is the same as the signal to transmit the system clock in a synchronization system receiving the same system clock, when a separate signal is added in addition to a plurality of signals output from one system. An encoding process of distributing to perform an AND operation and selecting and outputting one signal; It is achieved by including a decoding process of sequentially shifting the signals output in the encoding process, and logically calculating each shifted signal to restore the original signal.

Description

Method and apparatus for signal transmission of synchronizer system

The present invention relates to signal transmission control of a synchronization system, and more particularly, in a synchronization system receiving the same clock pulse, a signal is added and transmitted only by modifying a logic of each system without changing an interface between systems when a signal is transmitted. The present invention relates to a signal transmission method and apparatus of a synchronization system.

In general, internal operations in a digital system are synchronized by clock pulses generated by a pulse generator. Clock pulses are applied to all registers in the device, and all data transfers between internal registers occur simultaneously while the clock pulses occur. In other words, if two devices designed independently of each other are provided with a common clock, transmission between the two devices is synchronous.

In addition, a synchronization system may be constructed by adding synchronization circuits to seamlessly transfer data including synchronization between devices that transmit or operate data at different speeds.

As described above, as shown in FIG. 1, the first subsystem 10 and the Nth subsystem 10n receive the same clock pulse. Authorized and for mutual data communication, the first subsystem 10 and the Nth subsystem 10n are interconnected via an interface 12.

In the synchronization system configured as described above, data communication between systems generally performs transmission and reception of data in accordance with a predetermined clock signal, and when starting communication, a synchronization character for identifying a communication speed and a communication method at the beginning of the data. Add to send.

That is, as shown in FIG. 1, the first sub-system 10 performs data communication with the N-th sub-system 10n through an interface unit 12 provided separately.

In this case, data communication in the synchronization system generally performs synchronization between the receiving side and the transmitting side by adding a specific bit called a synchronization character to the front of the transmission data block.

In other words, synchronous transmission refers to a form in which information is transmitted while the clock is kept synchronized between the transmitting and receiving stations regardless of transmission information. If the transceiver uses an independent clock, the clock is guaranteed to ensure transmission quality. The accuracy of the circle is limited within a certain range.

However, the signal transmission in the synchronization system according to the related art has a problem in that an actual physical channel for transmitting data by modifying an interface between systems when a separate signal is required between systems is required. This meant the hassle of modifying both system and interface devices.

In addition, when the interface device connecting each system is a printed circuit board such as a back board, there is a problem in that a lot of cost and time are consumed when the interface device is modified.

Accordingly, an object of the present invention is to add a separate signal to the existing signal by modifying the logic of each system in the case of adding a separate signal in a synchronization system receiving the same clock pulse, the encoding process at the transmitting side And converting the encoded signal into the original signal through the decoding process at the receiving side, thereby transmitting the added signal without modifying the interface part between the existing systems or adding a new interface device. And providing an apparatus.

1 is a schematic block diagram showing a synchronized system according to the prior art,

2 is a block diagram showing a signal transmission apparatus of a synchronization system according to the present invention.

(a) is a block diagram showing an encoder in a signal transmission device,

(b) is a block diagram showing a decoder in the signal transmission apparatus.

Explanation of symbols for the main parts of the drawings

100: frequency divider 110: multiplexer

102, 104, 106, 108, 112, 114, 116, 118: first through eighth logical elements

111: shift register

In order to achieve the above object, a signal transmission method of a synchronization system according to an aspect of the present invention may include a separate signal in addition to a plurality of signals output from one system in a synchronization system receiving the same system clock. In the case of transmission, an encoding process of distributing the system clock in the same way as the signal to be transmitted, performing an AND operation, selecting one signal and outputting the same; And a decoding process of sequentially shifting the signals output in the encoding process, and performing a logical operation on each of the shifted signals to restore an original signal.

Further, in order to achieve the object as described above, in the synchronization system according to another aspect of the present invention, a signal transmission apparatus includes: distribution means for distributing a frequency in proportion to a transmission signal and a clock output from the distribution means; An encoder including a multiplexer performing an AND operation on the signal with the transmission signal, and outputting an output signal of a plurality of AND elements as one signal line; It includes a decoder for recovering the input signal input through the signal line to the original signal by a logic equation.

The decoder may include a shift register configured to sequentially shift a signal output from the multiplexer according to a common clock; And an inverter and an AND product for restoring each output signal output from the shift register to the original signal by a logic expression.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram showing a signal transmission device of the synchronization system according to the present invention, (a) is a block diagram showing the encoder in the signal transmission device, (b) is a block diagram showing a decoder in the signal transmission device. As shown therein, the signal transmission apparatus of the synchronization system is configured to logic the frequency divider 100 and the signals and clocks output from the frequency divider 100 to divide the frequency according to a signal to be transmitted and received the system clock. A multiplexer which selects and outputs a plurality of output signals output from the first to fourth logical product elements 102 to 104 and the first to Nth logical product elements 102 to 104 as multiplied signals ( An encoder including 110; A shift register 111 for shifting a series of bit sequences stored for each input of the signal output from the multiplexer 110 and the system clock signal of the encoder to the next flip-flop, and the signal output from the shift register 111 It is composed of a decoder including a plurality of inverters and the fourth to eighth logical products (112 to 118) for recovering to the original signal by a logical equation.

Referring to the signal transmission process of the synchronization system configured as described above are as follows.

First, the frequency divider 100 receiving the input data and the system clock signal converts the frequency into the number of channels to be transmitted in order to transmit the added signal and the existing input signal when a signal is newly added in addition to the existing data input signal. To distribute.

That is, when there are four signals to be transmitted, one system clock applied to the frequency divider 100 is divided into 1, 1/2, 1/4, and 1/8 division clocks. The AND operation is performed on the divided clock signal and the transmission signal.

In addition, the output signals of the logical AND elements 102 to 108 are input to the multiplexer 110 to be output as one signal line, and are input to the multiplexer 110 and then select only one output signal. An encoding process for transmitting a signal further generated in one subsystem to another synchronized subsystem is realized.

At this time, since a signal line for transmitting a plurality of low-speed data becomes one signal line, the utilization efficiency of the relay line is improved, and thus the cost of each low-speed data line is lowered.

Subsequently, the signal output from the multiplexer 110 is input to the shift register 111 together with the clock signal of the corresponding system for the decoding process for recovering the original signal.

That is, the binary value input to the 8-bit shift register 111 included in the decode section of FIG. 2 is restored to the signal before being encoded by the logical expression.

For example, when the initial value of the 8-bit shift register 111 is Q ₀ Q ₁ Q ₂ Q ₃ Q ₄ Q ₅ Q ₆ Q ₇ = 10101101, first output through the fourth AND product 112 is performed. A signal is generated as Q ₀ Q ₁ Q ₂ = 010, and a signal is output as Q ₀ Q ₁ Q ₂ Q ₃ = 0110 as the second signal output through the fifth AND product 114.

On the other hand, in the 8-bit shift register 111, the contents of the register are all updated with new data by eight clock pulses. That is, when the initial value is Q ₀ Q ₁ Q ₂ Q ₃ Q ₄ Q ₅ Q ₆ Q ₇ = 10101101, when one clock is input, the initial value, Q ₀ Q ₁ Q ₂ Q ₃ Q ₄ Q ₅ Q ₆ Q _The data is changed to ₇ = 01010110.

As such, after the signal output from the multiplexer 110 passes through the shift register 111 and performs a logical operation on the output of each register by a predetermined logical expression, the signal transmitted to the first encoder may be recovered. .

As described in detail above, in the present invention, when a separate signal is added in a synchronization system receiving the same clock pulse, the logic of each system is modified to add a separate signal to an existing signal, and these signals are transmitted. By performing the encoding process and converting the encoded signal to the original signal through the decoding process at the receiving side, it is possible to simply transmit the added signal without modifying the interface part between the existing systems or adding a new interface device. .

Claims (3)

In a synchronization system receiving the same system clock, when a separate signal is added and transmitted in addition to a plurality of signals output from one system, the system clock is distributed in the same manner as the signal to be transmitted, and each logical AND operation is performed. An encoding process of selecting and outputting one signal; And a decoding process of sequentially shifting the signals output in the encoding process, and performing a logical operation on each of the shifted signals to recover an original signal. A distribution means for distributing a frequency in proportion to the transmission signal and a multiplexing operation for performing an AND operation on the clock signal outputted from the distribution means with the transmission signal, and outputting output signals of a plurality of AND elements as one signal line An encoder comprising a group; And a decoder for recovering an input signal input through the signal line to an original signal by a logic expression. 3. The apparatus of claim 2, wherein the decoder comprises: a shift register configured to sequentially shift a signal output from the multiplexer according to a common clock; And an inverter and an AND product for restoring each output signal output from the shift register to the original signal by a logic equation.