KR19980050372A - Clock generator for data transmission synchronization - Google Patents

Abstract

Disclosed is a clock generator for synchronizing data transfer. The apparatus for selecting one of the clocks corresponding to the selection signals for selecting at least two clocks used for controlling the data transfer rate between two systems, and outputting the selected signal as a target clock, has at least two or more clocks. A multiplexer for selecting one of clocks and a predetermined level in response to the control signals, and outputting the selected signal as a target clock, at least two logic conversion means and at least two registers, each logic conversion means Logically combining the selection signal and the control signal, and each register outputs the corresponding logic conversion means as a control signal in synchronization with a clock, and the selection signal is changed by synchronizing the selection signal to a target clock as a register. By adjusting the time, unwanted glitches are eliminated, so the selection signal The system can be designed irrespective of the changing section, and the operation of the system is stabilized.

Description

Clock generator for data transmission synchronization.

The present invention relates to a method for controlling a data transfer rate between two systems, and more particularly, to a clock generator for synchronizing data transfer generating clocks for controlling the transfer rate.

In general, there is a problem of synchronization in transferring data between different systems having different data processing speeds. However, this is a very difficult task and plays an important role for system motivation.

As a conventional method for this, the transmission speed of the data is controlled by providing a buffer of a suitable size between two systems and controlling receiving and sending data from the buffer corresponding to which system should be transferred from which system. It was. Here, the selected clocks are used to control the data input and output of the buffer.

However, using a multiplexer to select the clock between these two systems will inevitably cause unwanted glitches due to different clock durations of the two systems. That is, a signal of a different type from the clock to be selected is generated at the moment when the selection signal transitions, resulting in unstable operation. Therefore, there is a problem that it is difficult to guarantee the clock selection operation.

In order to avoid this, conventionally, a system must be designed to avoid transmission of data in a certain section based on the moment of selecting a clock. That is, there is a problem in that system design is restricted.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a clock generator for synchronizing data transfer with a target clock for controlling a data transfer rate according to a selection signal generated in synchronization with a plurality of clocks.

In order to achieve the above object, one of the clocks is selected according to selection signals for selecting at least two clocks used for controlling the data transfer rate between two systems, and the selected signal is output as a target clock. A clock generator for data transmission synchronization according to the present invention includes a multiplexer for selecting one of the at least two clocks and a predetermined level in response to control signals, and outputting the selected signal as the target clock; Logic conversion means and the at least two registers, each logic conversion means logically combining the corresponding selection signal and the control signal, and each register converts the output of the logic conversion means to the clock. It is preferable to output in synchronization with the control signal as the control signal.

1 is a circuit diagram of a preferred embodiment of a clock generator for data transfer synchronization according to the present invention.

2 (a) to 2 (f) are waveform diagrams of respective parts shown in FIG.

Hereinafter, the configuration and operation of a clock generator for data transmission synchronization according to the present invention will be described with reference to the accompanying drawings.

1 is a circuit diagram of a preferred embodiment of a clock transmission device for data transmission synchronization according to the present invention, including first and second inverted logic sums 10 and 12, first and second registers 20 and 22, and an inverter. 14 and the multiplexer 30.

The multiplexer 30 shown in FIG. 1 selects the first and second clocks CK1 and CK2 and the supply voltage VDD in response to the first and second control signals S1 and S2, and selects the selected signal. It outputs as the target clock CLKO.

Meanwhile, the first inversion logic sum 10 inverts the OR signal output from the selection signal SEL and the second register 22 and outputs the inversion logic sum to the data input terminal D of the first register 20. The OR 12 performs an inverted OR on the inverted selection signal SEL and the output of the first register 20 through the inverter 14 and outputs the inverted OR to the data input terminal D of the second register 22.

The first register 20 outputs the output of the first inverted logic sum 10 as the first control signal S1 in response to the first clock CK1 and is set in response to the reset signal RESET. On the other hand, the second register 22 outputs the output of the second inverted logic sum 12 as the second control signal S2 in response to the second clock CK2 and is reset in response to the selection signal SEL.

That is, the first and second registers 20 and 22 temporarily store the selection signal SEL in synchronization with each clock, and the first and second inverted logic sums 10 and 12 correspond to the selection signal SEL and present. The value of each register determines the input value of the register.

2 (a) to 2 (f) are waveform diagrams of the respective parts shown in FIG. 1, FIG. 2 (a) is a first clock, FIG. 2 (b) is a second clock, FIG. 2 (c) is a selection signal, 2 (d) shows a first control signal, FIG. 2 (e) shows a second control signal, and FIG. 2 (f) shows a waveform diagram of a target clock.

The operation of the apparatus shown in FIG. 1 will be described with reference to FIG. 2. First, when the reset signal is initially activated, the first register 20 is set and the second register 22 is reset to reset the first control signal and the first control signal. The two control signals become '1 (or high logic level) 0 (or low logic level)'. The multiplexer 30 supplies a high level supply voltage VDD when the first and second control signals S1 S2 are '00', and a first clock CK1 when '10', and a second clock CK2 if '01'. ) Is set to '11', and the high-level supply voltage VDD is selected and output as the target clock CLKO.

After the initial reset, in the first section 42 shown in FIG. 2, the first and second control signals S1 and S2 become '10', and thus the multiplexer 30 selects the first clock CK1. Output When the selection signal SEL transitions from the low level to the high level in the first section 42, the output of the first inversion logic sum 10 immediately transitions to '0', and at the next rising edge of the first clock CK1, 1 The control signal S1 becomes '0'. Although the output of the inverter 14 becomes low level, even if the selection signal SEL changes, the first control signal S1 maintains the high level until the rising edge of the next first clock CK1, so that the second inversion logic sum 12 The output remains '0' until the rising edge of the next first clock CK1 after the selection signal SEL changes to a high level, and the output of the second register 22 remains at a low level.

In the second section 44, the first register 20 inputs the output of the first inverted logical sum 10 to a low level. Since the first control signal S1 is low level, the output of the second inverted logical sum 12 is The second control signal S2 is at the high level but the current value is maintained without changing the next second clock CK2 until the rising edge, so in the second section 44, the first and second control signals S1 and S2 are ' 00 ', the output of the multiplexer 30 selects a high level.

The second control signal S2 becomes '1' at the rising edge of the second clock CK2 in response to the output of the second inverted AND 12 in the third period 46, and the first inverted AND 10 is Since the first control signal S1 remains '0', the output of the multiplexer 30 selects the second clock CK2 in the third section 46. Even if the selection signal SEL is changed back to the low level in the third section 46 and the second inversion logic sum 12 is '0', the second register 22 maintains the high level of the rising edge of the next second clock CK2. Therefore, the output of the first inverted logical sum 10 also becomes '0' until then, and there is no change in the output of the first register 20, so that the output of the multiplier 30 is also the second clock CK2. Keep).

At the rising edge of the second clock CK2 in the fourth section 48, the second control signal S2 receives the output of the second inversion logic sum 12 and becomes low level, and thus the first inversion logic sum 10 is also made. Since the output of the first register 20 becomes high at the rising edge of the next first clock CK1, the first and second control signals S1 and S2 are again generated in the fourth section 48. Since both are '0', the multiplexer 30 selects and outputs a high logic level.

In the fifth section 50, since the first and second control signals S1 and S2 are '10', the output of the multiplexer 30 becomes the first clock CK1. That is, when both of the selection signals are disabled so that the first and second control signals S1 and S2 become '00', the time when the clock rises, and after both signals are disabled, the multiplexer 30 Since the output is always selected at a high level, the output of the multiplexer 30 can be electrically shifted from a high level to a high level, thereby preventing the width of the selected signal from changing drastically, thereby eliminating glitches.

As described above, the clock generator for data transmission synchronization according to the present invention eliminates unwanted glitches by adjusting the time at which the selection signal changes by synchronizing the selection signal with a register to the target clock, and thus relate to a section in which the selection signal changes. The system can be designed without, and the operation of the system is stabilized.

Claims (2)

Generation of a clock for data transmission synchronization that selects one of the clocks corresponding to the selection signals for selecting at least two clocks used to control the data transfer rate between two systems and outputs the selected signal as a target clock. In the apparatus, A multiplexer for selecting one of the at least two clocks and a predetermined level in response to control signals, and outputting the selected signal as the target clock; The at least two logic conversion means; And The at least two registers, Wherein each of the logic conversion means logically combines the corresponding selection signal and the control signal, and wherein each register outputs the control signal in synchronization with the clock and outputs the control signal as the control signal. Synchronous clock generator. A data transmission synchronization clock that selects one of the clocks corresponding to a selection signal for selecting first and second clocks used to control the data transfer rate between two systems, and outputs the selected signal as a target clock. In the generator, A multiplexer for selecting the first and second clocks and a predetermined level in response to first and second control signals, and outputting the selected signal as the target clock; A first inverted logical sum for inverting and ORing the selection signal and the second control signal; A second inverted logic sum that inverts and outputs the inverted selection signal and the first control signal; A first register outputting the output of the first inverted logic sum as the first control signal in response to the first clock; And And a second register for outputting the output of the second inverted logic sum as the second control signal in response to the second clock.