KR102499010B1 - Power gating circuit for holding data in logic block - Google Patents

Abstract

The present invention provides a power gating circuit for holding data. The power gating circuit includes a gate circuit and a first switch circuit. In the first mode, the gate circuit outputs a control signal selectively having a first logic value or a second logic value based on a first reference level and a level of a first voltage of a first voltage line connected to the logic block. The first switch circuit, in a first mode, disconnects the first voltage line from the second voltage line based on the first logic value of the control signal and switches the first voltage line to the second voltage line based on the second logic value of the control signal. Connect with voltage line. The first reference level is based on the type of logic gate included in the gate circuit and the level of the second voltage of the second voltage line.

Description

Power gating circuit for holding data of logic block {POWER GATING CIRCUIT FOR HOLDING DATA IN LOGIC BLOCK}

The present invention relates to an electronic circuit, and more particularly, to configurations and operations of a power gating circuit including a power switch.

Recently, miniaturization and portability of electronic devices are being emphasized. At the same time, functions performed in electronic devices are increasing. Most small electronic devices operate based on power from batteries. Therefore, in order to perform many functions in an electronic device, it is important to reduce power consumed by the electronic device.

Power gating technology is used to reduce power consumed by electronic devices. The power gating technology can lower the operating voltage of the logic block when some of the components included in the electronic device do not operate. Accordingly, current leaking from the logic block is reduced, and power consumed by the electronic device is reduced.

An object of the present invention is to maintain data stored in a logic block connected to a power gating circuit while some of the components inside the electronic device are not operating.

The present invention may provide a power gating circuit for holding data. In some embodiments, the power gating circuit may include a gate circuit and a first switch circuit. In the first mode, the gate circuit may output a control signal selectively having a first logic value or a second logic value based on a level of a first voltage of a first voltage line connected to a logic block and a first reference level. there is. The first switch circuit, in a first mode, disconnects the first voltage line from the second voltage line based on the first logic value of the control signal and switches the first voltage line to the second voltage line based on the second logic value of the control signal. It can be connected with a voltage line. The first reference level may be based on the type of a logic gate included in the gate circuit and the level of the second voltage of the second voltage line.

According to an embodiment of the present invention, the power gating circuit may control the level of the operating voltage while some of the internal components of the electronic device are not operating. The power gating circuit may lower the level of the operating voltage to a level at which the logic block can maintain stored data.

1 is a block diagram showing an exemplary configuration related to a power gating circuit according to an embodiment of the present invention.
FIG. 2 is a block diagram showing an exemplary configuration of the power gating circuit of FIG. 1 .
FIG. 3 is a circuit diagram showing an exemplary configuration of the power gating circuit of FIG. 2 .
FIG. 4 is a graph showing waveforms of operating voltages and power signals according to operating states of logic blocks in the power gating circuit of FIG. 3 .
FIG. 5 is a flowchart illustrating the operation of a power gating circuit while the logic block of FIG. 3 is in a holding state.
6 and 7 are graphs showing reference levels for different types of logic gates.
8 is a circuit diagram showing an exemplary configuration of the power gating circuit of FIG. 2;
9 is a circuit diagram showing an exemplary configuration of the power gating circuit of FIG. 2 .
FIG. 10 is a circuit diagram showing an exemplary configuration of the power gating circuit of FIG. 2 .
FIG. 11 is a graph showing operating voltage levels according to operating states of logic blocks in the power gating circuit of FIG. 10 .
FIG. 12 is a flowchart illustrating an operation of a power gating circuit when the level of an operating voltage is reduced while the logic block of FIG. 10 is in a sustain state.
FIG. 13 is a flowchart illustrating an operation of a power gating circuit when the level of an operating voltage is increased while the logic block of FIG. 10 is in a sustain state.
FIG. 14 is a circuit diagram showing an exemplary configuration of the power gating circuit of FIG. 2 .
FIG. 15 is a graph showing operating voltage levels according to operating states of logic blocks in the power gating circuit of FIG. 14 .
16 is a circuit diagram showing an exemplary configuration of the power gating circuit of FIG. 2 .
17 is a circuit diagram showing an exemplary configuration of the control circuit of FIG. 16;

Hereinafter, embodiments of the present invention will be described clearly and in detail to the extent that those skilled in the art can easily practice the present invention.

1 is a block diagram showing an exemplary configuration related to a power gating circuit according to an embodiment of the present invention.

The logic block 1100 may implement some or all of functions that may be implemented by an electronic device including the logic block 1100 . For example, the electronic device may include at least one of a desktop personal computer (PC), a laptop computer, a tablet computer, a smart phone, a wearable device, a server, and an electric vehicle. For example, the logic block 1100 may implement some or all of functions related to a graphic processing unit (GPU), a modulator/demodulator (MOME), a memory device, and the like.

Logic block 1100 may operate to implement functionality. For example, the logic block 1100 may receive data from the outside or output data to the outside. The logic block 1100 may store input data.

The power controller 1150 may receive an operation signal from an external device. For example, the power controller 1150 may include a power management unit (PMU). For example, the external device may include a main processor (eg, a central processing unit (CPU) or an application processor (AP)) or a separate voltage control circuit. When data is input to the logic block 1100 or data is output from the logic block 1100 to an external device, an operation signal may be received from the external device.

An operating state of the logic block 1100 may be determined by the operating signal. For example, the power controller 1150 may generate power signals s1 and s2 related to the operating state of the logic block 1100 based on the operating signal.

Each of the power signals s1 and s2 may selectively have a logic '0' value or a logic '1' value based on the operation signal. The power signals s1 and s2 may selectively have voltage levels corresponding to respective logic values. For example, the power signal s1 having a logic value of '1' may have a first voltage level. The power signal s2 having a logic '0' value may have a second voltage level.

The power gating circuit 1000 may receive power signals s1 and s2. The power gating circuit 1000 may control an operating state of the logic block 1100 based on the power signals s1 and s2 .

For example, when the first operation signal is not received for a first time, the power controller 1150 may generate power signals s1 and s2 each having a logic value of '1'. The power gating circuit 1000 changes the operating state of the logic block 1100 from a first operating state (hereinafter, a full operating state) to a second operating state (hereinafter, a holding state) based on the power signals s1 and s2. The logic block 1100 can be controlled to change. When the first operation signal is not received for the second time period, the power controller 1150 generates a power signal s1 having a logic '1' value and a power signal s2 having a logic '0' value. can The power gating circuit 1000 controls the logic block 1100 so that the operating state of the logic block 1100 is changed from a maintenance state to a third operating state (hereinafter referred to as a non-operating state) based on the power signals s1 and s2. You can control it. As another example, when the second operation signal is received, the power controller 1150 may generate a power signal s1 having a logic '1' value and a power signal s2 having a logic '0' value. there is. The power gating circuit 1000 may control the logic block 1100 to change an operating state of the logic block 1100 from a fully operating state to a non-operating state based on the power signals s1 and s2 .

The logic block 1100 may operate in various operating states under the control of the power gating circuit 1000 . As an example, when logic block 1100 is in a fully operational state, logic block 1100 may operate to implement a function. In a fully operational state, the logic block 1100 may receive data. The logic block 1100 may store input data. Also, in a fully operational state, the logic block 1100 may externally output data received from the outside or data based on an internal operation of the logic block 1100 .

For example, when the logic block 1100 is in the maintenance state, the logic block 1100 may stop some of the operations performed by the logic block 1100 in the fully operating state. In the hold state, the logic block 1100 may retain stored data without receiving data or outputting data.

For example, when the logic block 1100 is in an inactive state, the logic block 1100 may not operate. In an inactive state, the logic block 1100 may lose data stored in a fully operational state.

However, the present invention is not limited thereto, and the power controller 1150 may receive the signal cs0 from the logic block 1100 . The power controller 1150 may generate power signals s1 and s2 based on the signal cs0. However, the operation of the power gating circuit 1000 receiving the power signals s1 and s2 based on the signal cs0 causes the power gating circuit 1000 to receive the power signals s1 and s2 based on the operation signal. ), the case where the power signals s1 and s2 are generated based on the signal cs0 will be omitted in the following descriptions.

FIG. 2 is a block diagram showing an exemplary configuration of the power gating circuit of FIG. 1 .

The power gating circuit 1000 includes a power switch circuit 1200, a dedicated switch circuit 1300, a control circuit 1400, a power supply voltage line 1910, an operating voltage line 1920, and a ground voltage line 1930. can do.

The power voltage line 1910 may receive a voltage supplied from the outside of the electronic device or may receive a voltage supplied from a battery included in the electronic device. The power voltage line 1910 may supply a power voltage VDD to components inside the electronic device.

The operating voltage line 1920 may receive voltage from the power supply voltage line 1910 . The operating voltage line 1920 may supply an operating voltage VVDD to components inside the electronic device. The level of the operating voltage VVDD may be lower than or substantially equal to the level of the power supply voltage VDD.

The ground voltage line 1930 may supply the ground voltage VSS. For example, the ground voltage VSS may provide a reference potential for the levels of the voltages VVDD and VDD. The level of the ground voltage VSS may be lower than or substantially equal to the level of the operating voltage VVDD.

The power switch circuit 1200 may be connected to a power supply voltage line 1910 and an operating voltage line 1920 . The power switch circuit 1200 may receive the power signal s1. The power switch circuit 1200 connects the operating voltage line 1920 to the power voltage line 1910 or disconnects the operating voltage line 1920 from the power voltage line 1910 based on the power signal s1. (Disconnect).

The control circuit 1400 may be connected to a power supply voltage line 1910 , an operating voltage line 1920 , and a ground voltage line 1930 . The control circuit 1400 may operate based on the power voltage VDD supplied from the power voltage line 1910 .

The control circuit 1400 may receive a power supply voltage VDD, an operating voltage VVDD, and a power signal s2. The control circuit 1400 may output the control signal k0 based on the level of the power supply voltage VDD, the level of the operating voltage VVDD, and the power signal s2. The control signal k0 may selectively have a logic '0' value or a logic '1' value based on the level of the power supply voltage VDD, the level of the operating voltage VVDD, and the power signal s2. .

In the descriptions below, the signal may optionally have a value of logic '0' or a value of logic '1'. In this case, the signal may have a voltage level corresponding to the logic value. For example, the control signal k0 having a logic '1' value may have a first voltage level. The control signal k0 having a logic '0' value may have a second voltage level.

The dedicated switch circuit 1300 may be connected to the power supply voltage line 1910 and the operating voltage line 1920 . The dedicated switch 1300 may receive the control signal k0. The dedicated switch 1300 may connect the operating voltage line 1920 to the power voltage line 1910 or disconnect the operating voltage line 1920 from the power voltage line 1910 based on the control signal k0.

Logic block 1100 may be connected to operating voltage line 1920 and ground voltage line 1930 . The logic block 1100 may operate based on the operating voltage VVDD supplied from the operating voltage line 1920 . For example, the logic block 1100 may receive data from the outside or output data to the outside.

The logic block 1100 may store input data. The logic block 1100 may lose stored data when the supplied operating voltage VVDD is lower than the loss voltage level. As an example, the level of the loss voltage corresponds to an operation when a component (eg, a flip-flop, a latch, etc.) included in the logic block 1100 starts to lose data stored in the component. It may be the level of the voltage VVDD. The level of the loss voltage may vary depending on process effects or the temperature of the electronic device including the power gating circuit 1000 .

Leakage current generated in the logic block 1100 may decrease as the level of the operating voltage VVDD decreases. In example embodiments of the present disclosure, the power gating circuit 1000 may reduce leakage current generated in the logic block 1100 by lowering the level of the operating voltage VVDD while the logic block 1100 is in the sustain state. . Also, power consumed by the electronic device may be reduced.

However, the logic block 1100 may lose stored data when the level of the operating voltage VVDD becomes lower than the level of the loss voltage. Accordingly, while the logic block 1100 is in the maintenance state, the power gating circuit 1000 may operate such that the level of the operating voltage VVDD is maintained higher than the level of the loss voltage.

In the following descriptions, the power controller 1150 will be described as generating two power signals s1 and s2, but the present invention is not limited to this example, and the power controller 1150 may generate a plurality of power signals. can In addition, in the following descriptions, one power gating circuit 1000 will be described as receiving the power signals s1 and s2, but the present invention is not limited to this example, and each of the one or more power gating circuits receives the power signals s1 and s2. can receive Power signals received by each of the one or more power gating circuits may be different from each other. Based on the power signals, one or more power gating circuits may each control an operating state of one or more logic blocks. In this case, each of the one or more power gating circuits may include a power supply voltage line, an operating voltage line, and a ground voltage line that are different from each other. Also, the power controller 1150 may be connected to a power voltage line different from the power voltage line 1910 of the power gating circuit 1000 .

An operation of the power gating circuit 1000 that controls the level of the operating voltage VVDD will be described in detail with reference to FIGS. 3 to 17 .

FIG. 3 is a circuit diagram showing an exemplary configuration of the power gating circuit of FIG. 2 . The power gating circuit 1000a of FIG. 3 corresponds to an embodiment of the power gating circuit 1000 of FIG. 2 . For the purpose of understanding the present invention, FIG. 2 is referred to together.

The power switch circuit 1200 may include power switches 1210 and 1220 . As an example, each of the power switches 1210 and 1220 may include a PMOS transistor. When each of the power switches 1210 and 1220 is a PMOS transistor, source terminals of the PMOS transistors and drain terminals of the PMOS transistors may be connected to the power supply voltage line 1910 and the operating voltage line 1920, respectively. Threshold voltages Vth of each of the power switches 1210 and 1220 may be the same as or different from each other. In the following descriptions, the power switch circuit 1200 will be described as including two power switches 1210 and 1220, but the present invention is not limited to this example, and the power switch circuit 1200 includes one or more power switches. can include

The power switch circuit 1200 may receive the power signal s1. The power switches 1210 and 1220 connect the operating voltage line 1920 to the power voltage line 1910 based on the power signal s1, or connect the operating voltage line 1920 from the power voltage line 1910. can be disconnected.

For example, when the power signal s1 has a logic value of '0', the power switches 1210 and 1220 may connect the operating voltage line 1920 to the power voltage line 1910 . When the power voltage line 1910 is connected to the operating voltage line 1920, current may flow from the power voltage line 1910 to the operating voltage line 1920 through the power switches 1210 and 1220.

For example, when the power signal s1 has a logic value of '1', the power switches 1210 and 1220 may disconnect the operating voltage line 1920 from the power voltage line 1910 . When the power voltage line 1910 is disconnected from the operating voltage line 1920, current may not flow from the power voltage line 1910 to the operating voltage line 1920 through the power switches 1210 and 1220.

The control circuit 1400a may be a gate circuit including one or more logic gates. The control circuit 1400a may include a first gate 1410a and a second gate 1420a. For example, the first gate 1410a and the second gate 1420a may be an inverter and a NAND gate, respectively.

A first power terminal of the first gate 1410a may be connected to the power voltage line 1910 , and a second power terminal of the first gate 1410a may be connected to the ground voltage line 1920 . The first gate 1410a may receive the operating voltage VVDD.

The first gate 1410a may generate a signal based on the level of the operating voltage VVDD and the first reference level. The first gate 1410a may selectively generate one of signals having different logic values based on the level of the received operating voltage VVDD. For example, when the level of the operating voltage VVDD is higher than the first reference level, the first gate 1410a may output a signal having a logic '0' value. The first gate 1410a may output a signal having a logic '1' value when the level of the operating voltage VVDD is equal to or less than the first reference level.

The first reference level of the first gate 1410a may be higher than the level of the loss voltage. The first reference level may be a level determined based on the level of the power supply voltage VDD and the type of the first gate 1410a. The first reference level may be a level between the level of the power supply voltage VDD and the level of the ground voltage VSS. The first reference level may be proportional to the level of the power supply voltage VDD.

A ratio of a level difference between the first reference level and the power supply voltage VDD and a level difference between the first reference level and the ground voltage VSS may be determined based on the type of the first gate 1410a. . For example, with respect to the level of the same power voltage VDD, the first reference level when the first gate is a NAND gate may be higher than the first reference level when the first gate 1410a is an inverter. The first reference level according to the type of the first gate will be described in detail with reference to FIGS. 6 and 7 .

The second gate 1420a may output a control signal k1 based on the power signal s2 and the signal output from the first gate 1410a. For example, the control signal k1 may have a logic '0' value when each of the power signal s2 and the signal output from the first gate 1410a has a logic '1' value. As another example, the control signal k1 may have a logic '1' value when at least one of the power signal s2 and the signal output from the first gate 1410a has a logic '0' value. . The control signal k1 may be output to the dedicated switch circuit 1300 .

The dedicated switch circuit 1300 may include a dedicated switch 1310 . As an example, dedicated switch 1310 may include a PMOS transistor. When the dedicated switch 1310 is a PMOS transistor, a source terminal of the PMOS transistor and a drain terminal of the PMOS transistor may be connected to the power voltage line 1910 and the operating voltage line 1920, respectively. In the following descriptions, the dedicated switch circuit 1300 will be described as including one dedicated switch 1310, but the present invention is not limited to this example, and the dedicated switch circuit 1300 may include one or more dedicated switches. there is.

The dedicated switch circuit 1300 may receive the control signal k1. Based on the control signal k1, the dedicated switch 1310 may connect the operating voltage line 1920 to the power voltage line 1910 or disconnect the operating voltage line 1920 from the power voltage line 1910. .

For example, when the control signal k1 has a logic '0' value, the dedicated switch 1310 may connect the operating voltage line 1920 to the power supply voltage line 1910 . When the operating voltage line 1920 is connected to the power voltage line 1910 , current may flow from the power voltage line 1910 to the operating voltage line 1920 through the dedicated switch 1310 .

For example, when the control signal k1 has a logic value of '1', the dedicated switch 1310 may disconnect the operating voltage line 1920 from the power supply voltage line 1910 . When the operating voltage line 1920 is disconnected from the power voltage line 1910 , current may not flow from the power voltage line 1910 to the operating voltage line 1920 through the dedicated switch 1310 .

FIG. 4 is a graph showing waveforms of operating voltages and power signals according to operating states of logic blocks in the power gating circuit of FIG. 3 . To help understand the present invention, FIG. 3 is also referred to.

The power gating circuit 1000 may control an operating state of the logic block 1100 based on the power signals s1 and s2 . The power gating circuit 1000 may operate in different modes according to the power signals s1 and s2.

Between time 't1' and time 't2', the power signals s1 and s2 may each have a value of logic '0'. In this case, the power gating circuit 1000 may operate in the first mode. The power gating circuit 1000a may operate such that the level of the operating voltage VVDD is maintained at the level L2 based on the power signals s1 and s2 and the control signal k1 in the first mode. The power gating circuit 1000 may control the logic block 1100 so that the logic block 1100 is in a fully operational state.

For example, when the power signal s2 has a logic '0' value, the second gate 1420a may output a control signal k1 having a logic '1' value. The dedicated switch 1310 may disconnect the operating voltage line 1920 from the power supply voltage line 1910 based on the control signal k1 having a logic '1' value.

For example, when the power signal s1 has a logic value of '0', the power switches 1210 and 1220 may connect the operating voltage line 1920 to the power voltage line 1910 . The level of the operating voltage VVDD may be pulled up to be close to the level of the power supply voltage VDD. Accordingly, the level L2 of the operating voltage VVDD may approach the level of the power supply voltage VDD. The level L2 of the operating voltage VVDD may be lower than the level of the power supply voltage VDD due to resistance components of the power switches 1210 and 1220 .

Between time 't2' and time 't3', the power signals s1 and s2 may each have a logic value of '1'. In this case, the power gating circuit 1000 may operate in the second mode. The power gating circuit 1000a may operate in the second mode so that the level of the operating voltage VVDD approaches the first reference level L1 based on the power signals s1 and s2 and the control signal k1. there is. The power gating circuit 1000 may control the logic block 1100 so that the logic block 1100 is in a maintained state.

When the logic block 1100 is in the sustain state, the level of the operating voltage VVDD may be lower than the level L2 and higher than the level of the loss voltage V0. The level of the loss voltage V0 may be higher than the level of the ground voltage VSS.

For example, when the power signal s1 has a logic value of '1', the power switches 1210 and 1220 may disconnect the operating voltage line 1920 from the power voltage line 1910 .

For example, when the power signal s2 has a logic value of '1', the logic value of the control signal k1 may be determined based on the logic value of the signal output from the first gate 1410a.

The first gate 1410a may output a signal having a logic '0' value when the level of the operating voltage VVDD is higher than the first reference level L1. When the first gate 1410a outputs a signal having a logic '0' value, the control signal k1 may have a logic '1' value. In this case, the dedicated switch 1310 may disconnect the operating voltage line 1920 from the power supply voltage line 1910 based on the control signal k1 having a logic '1' value.

The first gate 1410a may output a signal having a logic value of '1' when the level of the operating voltage VVDD is equal to or less than the first reference level L1. When the first gate 1410a outputs a signal having a logic '1' value, the control signal k1 may have a logic '0' value. In this case, the dedicated switch 1310 may connect the operating voltage line 1920 to the power voltage line 1910 based on the control signal k1 having a logic '1' value.

The dedicated switch 1310 may connect the operating voltage line 1920 to the power supply voltage line 1910 until the level of the operating voltage VVDD becomes higher than the first reference level L1. The dedicated switch 1310 may disconnect the operating voltage line 1920 from the power supply voltage line 1910 when the level of the operating voltage VVDD becomes higher than the first reference level L1.

The level of the operating voltage (VVDD) is lower than the first reference level (L1) between the time 'ta' and the time 't3' after being reduced to the first reference level (L1) between the time 't2' and the time 'ta'. Repeatedly increasing and decreasing in the range between the low level and the level higher than the first reference level L1 may be maintained. The level of the operating voltage VVDD may approach the first reference level L1. However, for ease of understanding of the present invention, it will be assumed that the level of the operating voltage VVDD is maintained at the first reference level L1 while the logic block 1100 is in a maintained state. Accordingly, the level of the operating voltage VVDD while the logic block 1100 is in the maintenance state may be lower than the level L2 of the operating voltage VVDD while the logic block 1100 is in the fully operating state.

From time 't3' to time 't4', the first operation signal may be received by the power controller 1150 . As the first operating signal is received, the logic block 1100 may operate again in a fully operating state. In this case, the level of the operating voltage VVDD may be pulled up close to the level of the power supply voltage VDD by the power switches 1210 and 1220 . Accordingly, the level of the operating voltage VVDD may rise to the level L2 again.

At time 't4', the second operation signal may be received by the power controller 1150. The power controller 1150 may generate power signals s1 and s2 having a logic '1' value and a logic '0' value, respectively, based on the second operation signal. In this case, the power gating circuit 1000 may operate in the third mode. The power gating circuit 1000a may operate in the third mode so that the level of the operating voltage VVDD is lower than the level of the loss voltage V0 based on the power signals s1 and s2 and the control signal k1. there is. For example, the level of the operating voltage VVDD may be close to the level of the ground voltage VSS. The power gating circuit 1000 may control the logic block 1100 so that the logic block 1100 is in an inactive state.

For example, when the power signal s1 has a logic value of '1', the power switches 1210 and 1220 may disconnect the operating voltage line 1920 from the power voltage line 1910 .

For example, when the power signal s2 has a logic '0' value, the second gate 1420a may output the control signal k1 having a logic '1' value. The dedicated switches 1310 may disconnect the operating voltage line 1920 from the power supply voltage line 1910 based on the control signal k1 having a logic '1' value.

Accordingly, when the logic block 1100 is in an inactive state, the level of the operating voltage VVDD may approach the level of the ground voltage VSS.

According to the above operations, while the logic block 1100 is in the sustain state, the level of the operating voltage VVDD may be controlled to be lower than the level of the power supply voltage VDD and higher than the level of the loss voltage V0. Therefore, in the sustain state, data of the logic block 1100 may not be lost while leakage current generated in the logic block 1100 is reduced.

FIG. 5 is a flowchart illustrating the operation of a power gating circuit while the logic block of FIG. 3 is in a holding state. In order to facilitate understanding of the present invention, FIGS. 3 and 4 are referred to together.

Before the logic block 1100 is in the maintenance state, the level of the operating voltage VVDD may be maintained at the level L2. While the logic block 1100 is in the maintenance state, the power signals s1 and s2 may each have a logic '1' value.

In operation S110, the level of the operating voltage VVDD may be higher than the first reference level L1. Accordingly, the first gate 1410a may output a signal having a logic '0' value.

In operation S120, the power signal s1 may have a value of logic '1'. While the logic block 1100 is in the maintenance state, the power switches 1210 and 1220 may disconnect the operating voltage line 1920 from the power voltage line 1910 based on the power signal s1.

The power signal s2 may have a logic '1' value. The dedicated switch 1310 may disconnect the operating voltage line 1920 from the power voltage line 1910 based on the power signal s2 and the signal output from the first gate 1410a.

In operation S130 , the first gate 1410a may receive the operating voltage VVDD. Accordingly, in operation S140, the first gate 1410a may output a signal based on the level of the operating voltage VVDD and the first reference level L1. A signal output from the first gate 1410a may have a logic '0' value or a logic '1' value based on the level of the operating voltage VVDD and the first reference level L1.

When the level of the operating voltage VVDD is lower than the first reference level L1, the first gate 1410a may output a signal having a logic '1' value in operation S150. In some embodiments, even when the level of the operating voltage VVDD is equal to the first reference level L1, the first gate 1410a may output a signal having a logic '1' value. Then, in operation S160, the dedicated switch 1310 may connect the operating voltage line 1920 to the power voltage line 1910 based on the power signal s2 and the signal output from the first gate 1410a.

On the other hand, when the level of the operating voltage VVDD is higher than the first reference level L1, the power gating circuit 1000a may repeat operations S110 to S140. In this case, the dedicated switch 1310 may disconnect the operating voltage line 1920 from the power supply voltage line 1910 .

6 and 7 are graphs showing reference levels for different types of logic gates.

6 and 7 show reference levels for different types of logic gates (e.g., NAND4 gate, inverter, and NOR4 gate) while the supply voltage VDD is maintained at 1V and 0.6V, respectively.

As will be described later, the first power terminal of each of the logic gates (NAND4 gate, inverter, and NOR4 gate) may be connected to the power supply voltage VDD. A second power supply terminal of each of the logic gates (NAND4 gate, inverter, and NOR4 gate) may be connected to the ground voltage VSS. The logic gates (NAND4 gate, inverter, and NOR4 gate) may receive the operating voltage VVDD.

The logic gates (NAND4 gate, inverter, and NOR4 gate) may output a logic '0' value or a logic '1' value according to the level of the operating voltage VVDD received. As the level of the operating voltage VVDD decreases, logic values output from the logic gates (NAND4 gate, inverter, and NOR4 gate) may be changed. Each of the logic gates (NAND4 gate, inverter, and NOR4 gate) may output a logic '0' value when the level of the operating voltage VVDD is higher than the respective reference level. Each of the logic gates (NAND4 gate, inverter, and NOR4 gate) may output a logic '1' value when the level of the operating voltage VVDD is lower than the respective reference level.

For example, referring to FIG. 6 , the NAND4 gate may output a logic '0' value when the level of the operating voltage VVDD is higher than 0.67V. The NAND4 gate may output a logic '1' value when the level of the operating voltage VVDD is lower than 0.67V. Thus, the reference level for the NAND4 gate may be 0.67.

As described with reference to FIG. 3 , the reference level may be a level determined based on the level of the power supply voltage VDD and the types of logic gates. The reference level may correspond to the first reference level described with reference to FIG. 3 . Referring to FIG. 6 , reference levels of the NAND4 gate, the inverter, and the NOR gate may be 0.67V, 0.51V, and 0.36V, respectively. Referring to FIG. 7 , reference levels of the NAND4 gate, the inverter, and the NOR gate may be 0.37V, 0.275V, and 0.25V, respectively.

The first gate circuit 1410a of FIG. 3 may be implemented as a logic gate whose reference level is higher than the level of the loss voltage. For example, when the loss voltage of the logic block 1100 is 0.35V and the level of the power supply voltage VDD is 1V, the first gate circuit 1410a may be implemented as a NAND4 gate, an inverter, or a NOR4 gate. As another example, when the loss voltage of the logic block 1100 is 0.35V and the level of the power supply voltage VDD is 0.6V, the first gate circuit 1410a may be implemented as a NAND4 gate.

When the first gate circuit 1410a is implemented as a NAND4 gate, an operation of the power gating circuit will be described with reference to FIG. 8 . When the first gate circuit 1410a is implemented as a NOR4 gate, an operation of the power gating circuit will be described with reference to FIG. 9 .

8 is a circuit diagram showing an exemplary configuration of the power gating circuit of FIG. 2 .

Components 1210, 1220, 1310, and 1420b of the power gating circuit 1000b shown in FIG. 8 correspond to components 1210, 1220, 1310, and 1420a of the power gating circuit 1000a of FIG. Configurations and operations may be provided. Therefore, redundant descriptions are omitted below.

The control circuit 1400b may include a first gate 1410b and a second gate 1420b. For example, the first gate 1410b and the second gate 1420b may be a NAND4 gate and a NAND gate, respectively.

As described with reference to FIGS. 6 and 7 , the second reference level of the first gate 1410b may be higher than the first reference level of the first gate 1410a. The second reference level can be understood similarly to the first reference level. The control circuit 1400b operates at a logic '0' level at a level of the operating voltage VVDD higher than the level of the operating voltage VVDD at which the control signal k1 having a logic '0' value is output from the control circuit 1400a. A control signal k2 having a value may be output. Therefore, while the logic block 1100 is in the maintenance state, the level of the operating voltage VVDD based on the first gate 1410a may be lower than the level of the operating voltage VVDD based on the first gate 1410b. .

9 is a circuit diagram showing an exemplary configuration of the power gating circuit of FIG. 2 .

Components 1210, 1220, 1310, and 1420c of the power gating circuit 1000c shown in FIG. 9 correspond to components 1210, 1220, 1310, and 1420a of the power gating circuit 1000a of FIG. Configurations and operations may be provided. Therefore, redundant descriptions are omitted below.

The control circuit 1400c may include a first gate 1410c and a second gate 1420c. For example, the first gate 1410c and the second gate 1420c may be a NOR4 gate and a NAND gate, respectively.

As described with reference to FIGS. 6 and 7 , the first reference level of the first gate 1410c may be lower than the first reference level of the first gate 1410a. The third reference level can be understood similarly to the first reference level. The control circuit 1400c has a logic '0' level at a level of the operating voltage VVDD higher than the level of the operating voltage VVDD at which the control signal k1 having a logic '0' value is output from the control circuit 1400a. A control signal k3 having a value may be output. Accordingly, while the logic block 1100 is in the maintenance state, the level of the operating voltage VVDD based on the first gate 1410a may be higher than the level of the operating voltage VVDD based on the first gate 1410c. .

FIG. 10 is a circuit diagram showing an exemplary configuration of the power gating circuit of FIG. 2 .

Components 1210, 1220, and 1310 of the power gating circuit 1000d shown in FIG. 10 have configurations and operations corresponding to components 1210, 1220, and 1310 of the power gating circuit 1000a of FIG. can provide them. Therefore, redundant descriptions are omitted below.

The power controller 1150a may generate power signals s4 and s5 related to the operating state of the logic block 1100 .

The power switches 1210 and 1220 connect the operating voltage line 1920 to the power voltage line 1910 or disconnect the operating voltage line 1920 from the power voltage line 1910 based on the power signal s4. can do.

The control circuit 1600 includes a first gate 1610, a first auxiliary gate 1620, a second gate 1630, a second auxiliary gate 1640, a third gate 1650, and a fourth gate 1660. can include The first gate 1610, the second gate 1630, the third gate 1650, and the fourth gate 1660 may be a NOR4 gate, a NAND4 gate, a bistable element (c-element), and an OR gate, respectively. . The first gate 1610 and the second gate 1630 may provide configurations and operations corresponding to the first gate 1410c shown in FIG. 9 and the first gate 1410b shown in FIG. 8 , respectively. can Therefore, redundant descriptions are omitted below.

The fourth reference level of the first gate 1610 and the fifth reference level of the second gate 1630 correspond to the third reference level of the first gate 1410c and the second reference level of the first gate 1410b, respectively. can be matched.

The first gate 1610 may compare the level of the operating voltage VVDD and the fourth reference level to selectively output a signal having a logic '0' value or a logic '1' value. The first auxiliary gate 1620 may output a signal a1 having a logic value different from that of the signal output from the first gate 1610 .

The first gate 1630 may compare the level of the operating voltage VVDD and the fifth reference level to selectively output a signal having a logic '0' value or a logic '1' value. The second auxiliary gate 1640 may output a signal a2 having a logic value different from that of the signal output from the second gate 1630 .

The third gate 1650 may receive signals a1 and signals a2. The third gate 1650 may output a signal a3 based on the signals a1 and a2. Signal a3 may have a logic '0' value or a logic '1' value based on the logic value of signal a1 and the logic value of signal a2.

For example, when the third gate 1650 outputs the signal a3 having a logic value of '1', the third gate 1650 outputs the logic value of the signal a1 and the logic value of the signal a2. A signal a3 having a logic '1' value can be output until each logic '0' is reached. When the third gate 1650 outputs the signal a3 having a logic '0' value, the third gate 1650 determines that the logic value of the signal a1 and the logic value of the signal a2 are each a logic value. The signal a3 having a value of logic '0' can be output until it becomes '1'.

The fourth gate 1660 may output the control signal k4 based on the power signal s5 and the signal a3.

For example, while the logic block 1100 is in a fully operating state or in an inoperative state, the power signal s5 may have a logic '1' value. The control signal k4 may have a logic value of '1' regardless of the logic value of the signal a3 when the power signal s5 has a logic value of '1'.

For example, while the logic block 1100 is in the maintenance state, the power signal s5 may have a logic '0' value. The control signal k4 may have the same logic value as that of the signal a3 when the power signal s5 has a logic value of '0'.

The dedicated switch 1310 may connect the operating voltage line 1920 to the power voltage line 1910 or disconnect the operating voltage line 1920 from the power voltage line 1910 based on the control signal k4. .

FIG. 11 is a graph showing operating voltage levels according to operating states of logic blocks in the power gating circuit of FIG. 10 . 10 is also referred to for better understanding of the present invention.

When the logic block 1100 is in a fully operating or non-operating state, the power gating circuit 1000d illustrated in FIG. 10 may provide operations corresponding to those of the power gating circuit 1000a illustrated in FIG. 3 . When the logic block 1100 is in a fully operated state, the level L5 of the operating voltage VVDD illustrated in FIG. 10 may correspond to the level L2 of the operating voltage VVDD illustrated in FIG. 4 . Hereinafter, the power gating circuit 1000d when the logic block 1100 is in the holding state will be described.

The power gating circuit 1000d may control the operating state of the logic block 1100 based on the power signals s4 and s5. From time 't2' to time 't3', while the logic block 1100 is in the maintenance state, the power signals s4 and s5 may have a logic '1' value and a logic '0' value, respectively. The power switches 1210 and 1220 may disconnect the operating voltage line 1920 from the power voltage line 1910 based on the power signal s4 . When the logic value of the power signal s5 is '0', the control signal k4 may have the same logic value as that of the signal a3.

As described with reference to FIG. 10 , the signal a1 may have a logic '0' value when the level of the operating voltage VVDD is lower than the fourth reference level. Signal a2 may have a logic '0' value when the level of operating voltage VVDD is lower than the fifth reference level. Since the fourth reference level is lower than the fifth reference level, the third gate 1650 outputs a signal a3 having a logic value of '0' when the level of the operating voltage VVDD is lower than the fourth reference level. can do. The fourth gate 1660 may output a control signal k4 having a logic '0' value.

The signal a1 may have a logic '1' value when the level of the operating voltage VVDD is higher than the fourth reference level. Signal a2 may have a logic value of '1' when the level of operating voltage VVDD is higher than the fifth reference level. Since the fifth reference level is higher than the fourth reference level, the third gate 1650 outputs the signal a3 having a logic value of '1' when the level of the operating voltage VVDD becomes higher than the fifth reference level. can The fourth gate 1660 may output a control signal k4 having a logic '1' value.

Between time 't2' and time 'ta', the control signal k4 may have a value of logic '1'. The dedicated switch 1310 may disconnect the operating voltage line 1920 from the power supply voltage line 1910 based on the control signal k4 . Accordingly, the level of the operating voltage VVDD may decrease between time 't2' and time 'ta'. The control signal k4 may have a logic '0' value when the level of the operating voltage VVDD is lower than the fourth reference level. At time 'ta', the level of the operating voltage VVDD may be lower than the fourth reference level. At time 'ta', the level of the operating voltage VVDD may be the level L3. The level L3 may be lower than the fourth reference level of the first gate 1610 . However, the level L3 may be close to the fourth reference level. Accordingly, the level L3 may be higher than the level of the loss voltage V0.

Between time 'ta' and time 'tb', the control signal k4 may have a value of logic '0'. The dedicated switch 1310 may connect the operating voltage line 1920 to the power voltage line 1910 based on the control signal k4 . Accordingly, the level of the operating voltage VVDD may increase between the time 'ta' and the time 'tb'. The control signal k4 may have a logic '1' value when the level of the operating voltage VVDD is higher than the fifth reference level. At time 'tb', the level of the operating voltage VVDD may be higher than the fifth reference level. At time 'tb', the level of the operating voltage VVDD may be the level L4. The level L4 may be higher than the fifth reference level of the second gate 1630 . However, the level L4 may be close to the fifth reference level. Accordingly, level L4 may be lower than level L5.

From the time 'tb' to the time 'tc' when the level of the operating voltage VVDD is lower than the fourth reference level, the control signal k4 may have a logic '1' value. Therefore, from the time 'tb' when the operating voltage line 1920 is disconnected from the power supply voltage line 1910 to the time 'tc' when the operating voltage line 1920 is connected to the power supply voltage line 1910, the operating voltage VVDD ) can be reduced to the level L3 again.

According to operations between time 'ta' and time 'tc', the level of the operating voltage VVDD may be increased and decreased repeatedly. The power gating circuit 1000d may operate such that the level of the operating voltage VVDD is between the level L3 and the level L4 based on the power signals s4 and s5 and the control signal k4.

The level of the operating voltage VVDD described with reference to FIGS. 3 and 4 may be substantially maintained at one voltage level L1 while the logic block 1100 is in a holding state. In order to maintain the level of the operating voltage VVDD at substantially one voltage level L1, the dedicated switch 1310 of FIG. 3 must constantly repeat a switching operation. The switching operation may be an operation in which the dedicated switch 1310 connects the operating voltage line 1920 to the power supply voltage line 1910 and disconnects the operating voltage line 1920 from the power supply voltage line 1910 .

On the other hand, the level of the operating voltage VVDD described with reference to FIGS. 10 and 11 may be maintained between the level L3 and the level L4 while the logic block 1100 is in the sustain state. Accordingly, the dedicated switch 1310 of FIG. 10 may perform a switching operation only when the level of the operating voltage VVDD reaches the level L3 or L4. Accordingly, the power consumed by the dedicated switch 1310 shown in FIG. 10 may be less than the power consumed by the dedicated switch 1310 shown in FIG. 3 .

FIG. 12 is a flowchart illustrating an operation of a power gating circuit when the level of an operating voltage is reduced while the logic block of FIG. 10 is in a sustain state. 10 and 11 are referred to together to aid understanding of the present invention.

Before the logic block 1100 is in the maintenance state, the logic block 1100 may be assumed to be in a fully operational state.

Accordingly, as described with reference to FIG. 11 , in operation S210 , the first auxiliary gate 1620 may output a signal a1 having a logic value of '1'. Also, the second auxiliary gate 1640 may output a signal a2 having a logic value of '1'. The third gate 1650 may output a signal a3 having a logic value of '1' based on the signals a1 and a2. The control signal k4 may have the same logic value as that of the signal a3.

In operation S220 , the dedicated switch 1310 may disconnect the operating voltage line 1920 from the power supply voltage line 1910 based on the control signal k4 . The power switches 1210 and 1220 may disconnect the operating voltage line 1920 from the power voltage line 1910 based on the power signal s4 .

In operation S230 , each of the first gate 1610 and the second gate 1630 may receive the operating voltage VVDD.

In operations S240 and S250, the first gate 1610 may output a signal based on the level of the operating voltage VVDD and the fourth reference level. The second gate 1630 may output a signal based on the level of the operating voltage VVDD and the fifth reference level.

When the level of the operating voltage VVDD is lower than the fourth reference level, the level of the operating voltage VVDD may be increased.

When the level of the operating voltage VVDD is equal to or higher than the fourth reference level and the level of the operating voltage VVDD is lower than the fifth reference level, in operation S260, the first gate 1610 and the second gate 1620 are A signal having a logic '0' value and a signal having a logic '1' value may be output. Based on the signal output from the first gate 1610 and the signal output from the second gate 1620, the signal a1 and the signal a2 have a value of logic '1' and a value of logic '0', respectively. can have a value of The power gating circuit 1000d may repeat operations S210 to S250.

When the level of the operating voltage VVDD is equal to or higher than the fifth reference level, each of the first gate 1610 and the second gate 1620 may output a signal having a logic '0' value in operation S265. Based on the signal output from the first gate 1610 and the signal output from the second gate 1620, each of the signal a1 and the signal a2 may have a value of logic '1'. The power gating circuit 1000d may repeat operations S210 to S250.

FIG. 13 is a flowchart illustrating an operation of a power gating circuit when the level of an operating voltage is increased while the logic block of FIG. 10 is in a sustain state. 10 and 11 are referred to together to aid understanding of the present invention.

In operation S310, the first auxiliary gate 1620 may output a signal a1 having a logic '0' value. Also, the second auxiliary gate 1640 may output a signal a2 having a logic '0' value. The third gate 1650 may output a signal a3 having a logic value of '0' based on the signal a1 and the signal a2. The control signal k4 may have the same logic value as that of the signal a3.

In operation S320, the dedicated switch 1310 may connect the operating voltage line 1920 to the power supply voltage line 1910 based on the control signal k4.

In operation S330 , each of the first gate 1610 and the second gate 1630 may receive the operating voltage VVDD.

Accordingly, in operation S340, the first gate 1610 may output a signal based on the level of the operating voltage VVDD and the fourth reference level. The second gate 1630 may output a signal based on the level of the operating voltage VVDD and the fifth reference level.

When the level of the operating voltage VVDD is equal to or greater than the fifth reference level, the level of the operating voltage VVDD may decrease.

When the level of the operating voltage VVDD is lower than the fifth reference level, the level of the operating voltage VVDD may be equal to or higher than the fourth reference level in operation S350. The first gate 1610 and the second gate 1620 may output a signal having a logic '0' value and a signal having a logic '1' value, respectively. Based on the signal output from the first gate 1610 and the signal output from the second gate 1620, the signal a1 and the signal a2 have a value of logic '1' and a value of logic '0', respectively. can have a value of The power gating circuit 1000d may repeat operations S310 to S340.

14 is a circuit diagram showing an exemplary configuration of the power gating circuit of FIG. 2 .

Components 1210, 1220, 1310, and 1720 of the power gating circuit 1000e may provide configurations and operations corresponding to components 1210, 1220, 1310, and 1420a of the power gating circuit 1000a. there is. Therefore, redundant descriptions are omitted below.

The control circuit 1700 may include a clock generator 1710 and a first gate 1720 .

The clock generator 1710 may receive the power voltage VDD from the power voltage line 1910 . The clock generator 1710 may receive the power signal s2. The clock generator 1710 may operate based on the supplied power voltage VDD and the power signal s2. The power signal s2 may have a value of logic '1' when the logic block 1100 is in a maintenance state. The clock generator 1710 may output a clock signal b1 when the logic value of the power signal s2 is '1'.

The first gate 1720 may output the control signal k5 based on the power signal s2 and the clock signal b1. When the logic value of the power signal s2 is '1', the logic value of the control signal k5 may be determined based on the logic value of the clock signal b1. For example, when the clock signal b1 has a logic '1' value, the control signal k5 may have a logic '0' value. When the clock signal b1 has a logic '0' value, the control signal k5 may have a logic '1' value.

FIG. 15 is a graph showing operating voltage levels according to operating states of logic blocks in the power gating circuit of FIG. 14 . 14 is referred to together to facilitate understanding of the present invention.

When the logic block 1100 is in a fully operating or non-operating state, the power gating circuit 1000e illustrated in FIG. 14 may provide operations corresponding to those of the power gating circuit 1000a illustrated in FIG. 3 . When the logic block 1100 is in a fully operating state, the level L8 of the operating voltage VVDD illustrated in FIG. 15 may correspond to the level L2 of the operating voltage VVDD illustrated in FIG. 4 .

Between the time 't2' and the time 't3', the power signal s2 may have a value of logic '1'. The clock generator 1710 may output a clock signal b1 based on the power signal s2.

Between the time 't2' and the time 'ta', the clock signal b1 may have a value of logic '0'. The control signal k5 may have a logic '1' value based on the clock signal b1. The dedicated switch 1310 may disconnect the operating voltage line 1920 from the power voltage line 1910 based on the control signal k5 . Accordingly, the level of the operating voltage VVDD may drop from level L8 to level L6.

Between the time 'ta' and the time 'tb', the clock signal b1 may have a value of logic '1'. The control signal k5 may have a logic '0' value based on the clock signal b1. The dedicated switch 1310 may connect the operating voltage line 1920 to the power supply voltage line 1910 based on the control signal k5 . Accordingly, the level of the operating voltage VVDD may rise from the level L6 to the level L7.

Between the time 'tb' and the time 'tc', the clock signal b1 may have a value of logic '0'. The control signal k5 may have a logic '1' value based on the clock signal b1. The dedicated switch 1310 may disconnect the operating voltage line 1920 from the power voltage line 1910 based on the control signal k5 . Accordingly, the level of the operating voltage VVDD may drop from level L7 to level L6.

The clock generator 1710 may control the period of the clock signal b1 and the length of time between times 'ta' and 't2' so that the level L6 is higher than the level of the loss voltage V0. In addition, the clock generator 1710 may control the period of the clock signal b1 and the length of time between time 'ta' and time 't2' so that the level L7 is lower than the level L8.

The period of the clock signal b1 may be 'tc-ta'. Until time 't3', the clock generator 1710 may repeatedly output the clock signal b1 having the same waveform as the waveform of the clock signal b1 generated between time 'ta' and time 'tc'. Based on the clock signal b1, between the time 'ta' and the time 't3', the level of the operating voltage VVDD drops to the level L6, and the level of the operating voltage VVDD drops to the level L7. The operation of rising to may be repeated. Accordingly, when the length of the period of the clock signal b1 is increased, the level difference between the level L6 and the level L7 may increase.

The clock generator 1710 may control a time 'ta' at which the clock signal b1 having a logic '1' value starts to be output. Depending on the length of time between the time 'ta' and the time 't2', the level of the operating voltage VVDD maintained between the time 'ta' and the time 't3' may be changed. For example, as the length of time between the time 'ta' and the time 't2' increases, the level of the operating voltage VVDD at the time 'ta' may be lower than the level L6. In this case, the level of the operating voltage VVDD may be maintained between a level lower than the level L6 and a level lower than the level L7.

As described with reference to FIG. 3 , the control circuit 1400a may receive the operating voltage VVDD to output the control signal k1 . On the other hand, the control circuit 1700 shown in FIG. 14 may output the control signal k5 without receiving the operating voltage VVDD.

The power gating circuit 1000a may maintain the operating voltage VVDD at substantially the same level as the first reference level L1 while the logic block 1100 is in the sustain state. The first reference level L1 may be determined based on the type of the first gate 1410 . On the other hand, the power gating circuit 1000e may operate such that the level of the operating voltage VVDD is maintained at a level between the level L6 and the level L7 while the logic block 1100 is in the sustain state. The levels L6 and L7 may be determined based on the length of the cycle of the clock signal b1 and the length of time between the time 'ta' and the time 't2'.

In order to maintain the level of the operating voltage VVDD at substantially one voltage level L1, the dedicated switch 1310 of FIG. 3 must constantly repeat a switching operation. The cycle of the switching operation generated by the dedicated switch 1310 shown in FIG. 14 may coincide with the cycle of the clock signal b1. The clock generator 1710 may control the period of the clock signal b1. Accordingly, the power consumed by the dedicated switch 1310 shown in FIG. 14 may be less than the power consumed by the dedicated switch 1310 shown in FIG. 3 .

16 is a circuit diagram showing an exemplary configuration of the power gating circuit of FIG. 2 .

Components 1210, 1220, 1310, and 1820 of the power gating circuit 1000f shown in FIG. 16 correspond to components 1210, 1220, 1310, and 1420a of the power gating circuit 1000a of FIG. Configurations and operations may be provided. Therefore, redundant descriptions are omitted below.

The control circuit 1800 may include a monitoring circuit 1810 and a first gate 1820 .

The monitoring circuit 1810 may receive the power voltage VDD from the power voltage line 1910 . The monitoring circuit 1810 may receive the power signal s2. The monitoring circuit 1810 may operate based on the supplied power voltage VDD and the power signal s2. The power signal s2 may have a value of logic '1' when the logic block 1100 is in a maintenance state. The monitoring circuit 1810 may output a signal c1 when the logic value of the power signal s2 is '1'.

The monitoring circuit 1810 may receive the operating voltage VVDD. The monitoring circuit 1810 may output a conversion value corresponding to the level of the operating voltage VVDD. The monitoring circuit 1810 may use one or more reference values. Information about one or more reference values may be stored in the monitoring circuit 1810 or stored in another memory device. Each of the one or more reference values may correspond to voltage levels.

The monitoring circuit 1810 may compare the conversion value with one or more reference values. The monitoring circuit 1810 may output a signal c1 based on the comparison result. An operation of outputting the signal c1 based on the comparison result will be described with reference to FIG. 17 . The level of the operating voltage VVDD when the logic block 1100 is in the sustain operation state may be related to voltage levels corresponding to one or more reference values.

The first gate 1820 may output a control signal k6 based on the power signal s2 and the signal c1. When the logic value of the power signal s2 is '1', the logic value of the control signal k6 may be determined based on the logic value of the signal c1. For example, when the signal c1 has a logic '1' value, the control signal k6 may have a logic '0' value. When the signal c1 has a logic '0' value, the control signal k6 may have a logic '1' value.

17 is a circuit diagram showing an exemplary configuration of the control circuit of FIG. 16;

The control circuit 1800 may include a monitoring circuit 1810 and a first gate 1820 . The monitoring circuit 1810 may include delay circuits 1811 and 1812 and a comparison circuit 1813 . However, the monitoring circuit 1810 is not limited to including two delay circuits 1811 and 1812, and the monitoring circuit 1810 may include one or more delay circuits. The monitoring circuit 1810 may operate only while the logic block 1100 is in a maintenance state based on the power signal s2. Therefore, the operation of the control circuit 1800 while the logic block 1100 is in the holding state will be described below.

The delay circuit 1811 may receive the operating voltage VVDD. The delay circuit 1811 may output a signal c2 based on the level of the operating voltage VVDD. Signal c2 can optionally have a value of logic '0' or a value of logic '1'.

The delay circuit 1811 may output a signal c2 having a logic value of '0' when the level of the operating voltage VVDD is higher than the sixth reference level. As an example, the delay circuit 1811 may include an inverter. The sixth reference level may correspond to the first reference level described in FIG. 3 .

A first delay may be generated in the delay circuit 1811 . The first delay may be a difference between a time when the delay circuit 1811 receives the operating voltage VVDD and a time when the delay circuit 1811 outputs the signal c2. At a time when the operating voltage VVDD having a level higher than the sixth reference level is received by the first delay, the delay circuit 1811 may output a signal c2 having a logic '1' value. The first delay may increase as the level of the operating voltage VVDD increases. A logic value of the signal c2 may be determined based on the level of the operating voltage VVDD and the first delay.

Delay circuit 1812 can receive signal c2. The delay circuit 1812 may output a signal c3 based on the signal c2. Signal c3 can optionally have a value of logic '0' or a value of logic '1'.

As an example, the delay circuit 1812 can include an inverter. The delay circuit 1812 may output a signal c3 having a logic '1' when receiving a signal c2 having a logic '0'.

A second delay may be generated in the delay circuit 1812 . The second delay may be a difference between a time when the delay circuit 1812 receives the signal c2 and a time when the delay circuit 1812 outputs the signal c3. At the time when the signal c2 having a value of logic '0' is received by the second delay, the delay circuit 1811 may output the signal c3 having a value of logic '0'. The logic value of the signal c3 may be determined based on the level of the operating voltage VVDD and the second delay.

Comparing circuit 1813 may receive signals c2 and c3. The comparison circuit 1813 may generate conversion values corresponding to signals c2 and c3. For example, when the signals c2 and c3 each have a logic '1' value and a logic '0' value, the conversion value may be '10'. Since the conversion value is determined based on the logic values of the signals c2 and c3, the conversion value may be a value related to the level of the operating voltage VVDD, the first delay, and the second delay. The conversion value may include information about the level of the operating voltage VVDD.

The comparison circuit 1813 may use one or more reference values. One reference value may include information corresponding to one voltage level. The comparison circuit 1813 may compare the conversion value with one or more reference values. The comparison circuit 1813 may output a signal c1 based on the comparison result.

For example, the comparison circuit 1813 may store a first reference value, a second reference value, and a third reference value. The first reference value '11', the second reference value '01', and the third reference value '00' may correspond to the first voltage level, the second voltage level, and the third voltage level, respectively. The first voltage level may be lower than the second voltage level, and the second level may be lower than the third level.

For example, the comparison circuit 1813 may compare the first reference value, the third reference value, and the conversion value. The comparator 1813 may output a signal c1 having a value of logic '0' when the conversion value is the third reference value. The comparator 1813 may output a signal c1 having a value of logic '0' until the conversion value is changed from the third reference value to the first reference value. The comparator 1813 may output a signal c1 having a logic value of '1' when the converted value is the first reference value. The comparator 1813 may output a signal c1 having a value of logic '0' until the conversion value is changed from the first reference value to the third reference value.

Accordingly, the level of the operating voltage VVDD of the power gating circuit 1000f may correspond to the level of the operating voltage VVDD of the power gating circuit 1000d described with reference to FIG. 11 . The first voltage level and the third voltage level may respectively correspond to the fourth reference level described in FIG. 11 and the fifth reference level described in FIG. 11 .

In example embodiments of the present disclosure, the power gating circuit 1000 may control the level of the operating voltage without receiving voltages other than the power supply voltage VVDD, the operating voltage VVD, and the ground voltage VSS. Also, since the control circuit 1400 is implemented as a digital circuit, the area of the power gating circuit 1000 may be reduced.

The foregoing are specific embodiments for carrying out the present invention. The present invention will include not only the above-described embodiments, but also embodiments that can be simply or easily changed in design. In addition, the present invention will also include techniques that can be easily modified and practiced using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments and should not be defined by the following claims as well as those equivalent to the claims of this invention.

Claims (10)

a first switch circuit configured to disconnect the first voltage line from a second voltage line while a logic block coupled to the first voltage line is in a first operating state;
a gate circuit configured to output a control signal having a first logic value when a level of a first voltage of the first voltage line is lower than a reference level while the logic block is in the first operating state; and
a second switch circuit configured to connect the first voltage line to the second voltage line based on the first logic value of the control signal;
The power gating circuit of claim 1 , wherein the reference level changes based on a type of a logic gate included in the gate circuit and a level of the second voltage of the second voltage line. delete According to claim 1,
The gate circuit is further configured to output the control signal having a second logic value different from the first logic value when the level of the first voltage is higher than the reference level while the logic block is in the first operating state. constituted,
and the second switch circuit is further configured to disconnect the first voltage line from the second voltage line based on the second logic value of the control signal. According to claim 1,
and a power gating circuit configured to generate a power signal related to an operating state of the logic block such that the logic block is in the first operating state or the second operating state. According to claim 4,
the first switch circuit is further configured to connect the first voltage line to the second voltage line based on the power signal while the logic block is in the second operating state;
the gate circuit is further configured to output the control signal having a second logic value different from the first logic value based on the power signal while the logic block is in the second operating state;
and the second switch circuit is further configured to disconnect the first voltage line from the second voltage line based on the second logic value of the control signal. In a first mode, a gate circuit configured to output a control signal selectively having a first logic value or a second logic value based on a level of a first voltage of a first voltage line connected to the logic block and a first reference level. ; and
In the first mode, the first voltage line is disconnected from the second voltage line based on the first logic value of the control signal and the first voltage line is disconnected based on the second logic value of the control signal. A first switch circuit configured to connect to the second voltage line,
The power gating circuit of claim 1 , wherein the first reference level is changed based on a type of a logic gate included in the gate circuit and a level of a second voltage of the second voltage line. According to claim 6,
The gate circuit outputs the control signal of the first logic value when the level of the first voltage is higher than the first reference level in the first mode, and the level of the first voltage in the first mode The power gating circuit is further configured to output the control signal of the second logic value when the value becomes lower than the first reference level. According to claim 6,
The gate circuit includes a first logic gate and a second logic gate outputting signals related to the control signal based on the first voltage;
The gate circuit is configured to selectively output the control signal of the first logic value or the control signal of the second logic value based on the level of the first voltage, the first reference level, and the second reference level. more composed,
the first reference level varies based on the type of the first logic gate and the level of the second voltage;
wherein the second reference level varies based on the type of the second logic gate and the level of the second voltage. According to claim 8,
When the first reference level is lower than the second reference level in the first mode,
The gate circuit,
outputting the control signal of the second logic value when the level of the first voltage is lower than the first reference level in a first time interval in which the level of the first voltage decreases;
and outputting the control signal of the second logic value when the level of the first voltage is lower than the second reference level in a second time interval in which the level of the first voltage increases. According to claim 9,
In the first mode, the first switch circuit disconnects the first voltage line from the second voltage line when the level of the first voltage becomes the second reference level and the level of the first voltage The power gating circuit is further configured to connect the first voltage line to the second voltage line when the voltage becomes the first reference level.

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