KR102282363B1 - Bit-serial hight operation apparatus and its method, computer-readable recording medium and computer program having program language for the same - Google Patents

Abstract

The present invention relates to a bit serial HIGHT arithmetic device and method, and a computer-readable recording medium and computer program including instructions for causing a processor to perform the method, using an input master key (MasterKey) to perform initial conversion and A key scheduling module unit that selects and provides a whitening key for final conversion and a sub-key for round operation, and provides the whitening key or sub-key by calculating the master key through a key shift register; The input plain text is output by performing the initial transformation, round operation, and final transformation using the whitening key or sub-key, but the plain text is inputted and the shift data stored in the first text shift register and the whitening key Alternatively, by including a round function module unit that operates using a subkey, a multiplexer (MUX) required for data control can be minimized, and a 1-bit operation can be performed every cycle without delay.

Description

BIT-SERIAL HIGHT OPERATION APPARATUS AND ITS METHOD, COMPUTER-READABLE RECORDING MEDIUM AND COMPUTER PROGRAM HAVING A bit serial HIGHT arithmetic device and method, and a computer-readable recording medium and computer program containing instructions for causing a processor to perform the method PROGRAM LANGUAGE FOR THE SAME}

The present invention can minimize a multiplexer (MUX) required for data control by implementing a text register and a key register as a shift register, and implement a byte unit auxiliary function in 1-bit units through an additional shift register. A bit serial HIGHT arithmetic device and method capable of performing 1-bit unit operation without delay in every cycle by adjusting the position of the calculated data, and a computer-readable computer readable method including instructions for causing a processor to perform the method It relates to a recording medium and a computer program.

As is well known, encryption is a process of encoding so that its meaning is not clear, and decryption means a process of converting an encrypted message into its original form. The form is called cipher text.

On the other hand, the symmetric encryption system is a system in which the sender's key used for encryption and the receiver's key are the same for decryption. ) As a block encryption technology, the HIGHT (High Encryption Standard) encryption algorithm has been developed, and various research and development are being conducted to implement it.

This HIGHT has a 64-bit plaintext (P) and a 128-bit key length, as shown in FIGS. 1 to 3, and includes an initial transformation and a final transformation and 32 rounds of operations. can perform encryption and decryption operations.

HIGHT hardware implementation designed with the smallest area so far is a round-based method that calculates one round per clock cycle, and has an area of about 3000GE (Gate Equivalents), but passive RFID (passive RFID) In order to perform encryption in an environment where area and power consumption are limited, such as RFID), it is necessary to design smaller than 2000GE.

In the conventional round-based HIGHT hardware, a 64-bit round operation unit and a 64-bit and 128-bit multiplexer (MUX) for selecting text and key data occupy a large area. In order to reduce the area, a symmetric round operation unit is used. The traditional folding technique of sharing hardware by making it in 32-bit or 16-bit units can be applied, but not only does it not have a great effect due to the additional cost of a multiplexer (MUX) to control it, but also auxiliary functions F0, Since F1 and addition operations are performed in units of 8 bits (1 byte), there is a problem in that it is difficult to implement a HIGHT operation structure of 8 bits or less with a simple folding technique.

1. Korea Patent No. 10-1330664 (Registered on Nov. 8, 2013) 2. Korean Patent Publication No. 10-2015-0123476 (published on November 4, 2015)

The present invention can minimize a multiplexer required for data control by implementing a text register and a key register as a shift register, and by implementing a byte-by-byte auxiliary function in 1-bit units through an additional shift register to adjust the position of the data to be calculated. , It is intended to provide a bit serial HIGHT arithmetic device capable of performing 1-bit unit operation without delay in every cycle, a method therefor, and a computer-readable recording medium and computer program including instructions for causing a processor to perform the method .

In addition, the present invention uses the input master key (MasterKey) to select and provide a whitening key for initial conversion and final conversion and a sub key for round operation, but the master key is transferred through a key shift register operation to generate a whitening key or sub-key, and performing initial transformation, round operation, and final transformation of the input plain text using the whitening key or sub-key, and outputting the shift data, where the plain text is input and stored in the first text shift register An object of the present invention is to provide a computer-readable recording medium and computer program including a bit serial HIGHT arithmetic device capable of calculating using a whitening key or a sub-key, a method thereof, and instructions for a processor to perform the method.

The purpose of the embodiments of the present invention is not limited to the above-mentioned purpose, and other objects not mentioned will be clearly understood by those of ordinary skill in the art to which the present invention belongs from the description below. .

According to one aspect of the present invention, a whitening key for initial conversion and final conversion using an input master key and a sub key for round operation are selected and provided, but the master key is used as a key A key scheduling module unit that provides the whitening key or sub-key by calculating through a shift register, and performing the initial transformation, round operation, and final transformation of input plain text using the whitening key or sub-key There may be provided a bit-serial HIGHT calculating device including a round function module unit for outputting the plaintext and performing an operation using shift data stored in a first text shift register and the whitening key or sub-key to which the plaintext is input.

In addition, according to an aspect of the present invention, the key scheduling module unit includes a key shift register that is a basis for selectively generating any one of the whitening key and the sub-key, and 1 bit each through the key shift register. There may be provided a bit serial HIGHT arithmetic device for calculating and providing the whitening key or the sub-key to the round function module unit bit by bit.

In addition, according to an aspect of the present invention, the round function module unit includes a bit serial having a 1 byte second text shift register for calculating the first auxiliary function and the second auxiliary function in units of 8 bits in units of 1 bit. A HIGHT computing device may be provided.

Also, according to an aspect of the present invention, the round function module unit stores the round operation on the even-numbered byte text data in the second text shift register while performing the round operation on the even-numbered byte text data, and performs the round operation on the odd-numbered byte text data. When performing an operation, a bit serial HIGHT operation device may be provided that outputs the result of the first auxiliary function or the second auxiliary function bit by bit while cyclically shifting the value stored in the second text shift register. there is.

Also, according to an aspect of the present invention, the round function module unit outputs the result of the first auxiliary function or the second auxiliary function by 1 bit, and with respect to the result value of the first auxiliary function or the second auxiliary function, The round operation is performed, and the output value obtained by the round operation is stored in the first text shift register, but in the case of an addition operation in which a carry occurs, a 1-bit flip-flop is used for every cycle. A bit serial HIGHT arithmetic device for storing the carry generated every time may be provided.

According to another aspect of the present invention, a whitening key for initial conversion and final conversion using an input master key and a sub key for round operation are selected and provided, but the master key is a key providing the whitening key or sub-key by calculating through a shift register; and performing the initial transformation, round operation, and final transformation on the input plain text using the whitening key or sub-key to output, A bit-serial HIGHT calculation method may be provided, including calculating the plaintext input using shift data stored in a first text shift register and the whitening key or sub-key.

In addition, according to another aspect of the present invention, the step of providing the whitening key or sub-key comprises calculating 1 bit each through a key shift register that is a basis for selective generation of any one of the whitening key or the sub-key. A bit-serial HIGHT calculation method for selectively providing the whitening key or the sub-key one bit at a time to the round function module unit may be provided.

In addition, according to another aspect of the present invention, the calculating using the whitening key or the sub-key comprises: a 1 byte second for calculating the first auxiliary function in units of 8 bits and the second auxiliary function in units of 1 bit A bit serial HIGHT operation method having a text shift register may be provided.

According to another aspect of the present invention, the calculating using the whitening key or the sub-key includes storing in the second text shift register while performing the round operation on the even-numbered byte text data, and storing the odd-numbered byte text data. Bit for outputting the result of the first auxiliary function or the second auxiliary function bit by bit while cyclically shifting the value stored in the second text shift register when the round operation is performed on byte text data A serial HIGHT calculation method may be provided.

According to another aspect of the present invention, the calculating using the whitening key or the sub-key may include outputting the result of the first auxiliary function or the second auxiliary function 1 bit by bit, and the first auxiliary function or the second auxiliary function 2 The round operation is performed on the result value of the auxiliary function, and the output value obtained by the round operation is stored in the first text shift register. In the case of an addition operation in which a carry occurs, a 1-bit flip-flop (flip-flop) is performed. -flop) may be used to provide a bit serial HIGHT calculation method for storing the carry that occurs in every cycle.

According to another aspect of the present invention, as a computer-readable recording medium storing a computer program, the computer program is, when executed by a processor, for initial conversion and final conversion using an input master key (MasterKey) Selecting and providing a whitening key and a sub-key for round operation, calculating the master key through a key shift register to provide the whitening key or sub-key, and input plain text is output by performing the initial transformation, round operation, and final transformation using the whitening key or sub-key, and is calculated using shift data stored in the first text shift register after the plain text is input and the whitening key or sub-key A computer-readable recording medium containing instructions for causing the processor to perform a method comprising the step of doing may be provided.

According to another aspect of the present invention, as a computer program stored in a computer-readable recording medium, the computer program, when executed by a processor, using the input master key (MasterKey) for initial conversion and final conversion Selecting and providing a whitening key and a sub-key for round operation, calculating the master key through a key shift register to provide the whitening key or sub-key, and input plain text is output by performing the initial transformation, round operation, and final transformation using the whitening key or sub-key, and is calculated using shift data stored in the first text shift register after the plain text is input and the whitening key or sub-key There may be provided a computer program including instructions for causing the processor to perform a method comprising the step of:

The present invention can minimize a multiplexer required for data control by implementing a text register and a key register as a shift register, and by implementing a byte-by-byte auxiliary function in 1-bit units through an additional shift register to adjust the position of the data to be calculated. , it is possible to perform 1-bit operation without delay in every cycle.

In addition, the present invention uses the input master key (MasterKey) to select and provide a whitening key for initial conversion and final conversion and a sub key for round operation, but the master key is transferred through a key shift register operation to generate a whitening key or sub-key, and performing initial transformation, round operation, and final transformation of the input plain text using the whitening key or sub-key, and outputting the shift data, where the plain text is input and stored in the first text shift register and whitening key or sub-key.

In particular, since the structure of the bit serial HIGHT operation device proposed in the present invention replaces the text register and the key register with a shift register, and most of the registers except for a specific position are shifted to the next position without exception, it is necessary for data control. The advantage is that most of the multiplexer can be eliminated.

In addition, the present invention can implement 1-bit unit of auxiliary functions (F0, F1) including byte-unit cyclic shift operation by utilizing a 1-byte shift register, so that the entire round operation unit can be configured in 1-bit units. In addition, since the hardware that performs encryption and decryption operations is the same except for the control signal, reconfigurable hardware between encryption and decryption can be implemented in a low area without additional cost, and the entire hardware area can be reduced to the conventional round-based HIGHT structure. can be significantly reduced compared to

1A to 1C are diagrams illustrating a conventional HIGHT calculation algorithm,
2 is a block diagram showing a bit serial HIGHT arithmetic device according to an embodiment of the present invention;
3 to 6 are diagrams for explaining bit serial HIGHT operation according to an embodiment of the present invention;
7 is a step-by-step flowchart illustrating a process of performing a bit serial HIGHT operation according to another embodiment of the present invention.

Advantages and features of embodiments of the present invention, and methods of achieving them, will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the art to which the present invention pertains It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout.

In describing the embodiments of the present invention, if it is determined that a detailed description of a well-known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. In addition, the terms to be described later are terms defined in consideration of functions in an embodiment of the present invention, which may vary according to intentions or customs of users and operators. Therefore, the definition should be made based on the content throughout this specification.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating an apparatus for bit-serial HIGHT operation according to an embodiment of the present invention, and FIGS. 3 to 6 are diagrams for explaining a bit-serial HIGHT operation according to an embodiment of the present invention.

Here, the encryption process using the bit serial HIGHT operation device according to an embodiment of the present invention may consist of initial transformation, round operation, and final transformation, and the decryption process is initial transformation, round operation, and encryption, which are inverse transformations of the encryption final transformation. The final conversion, which is the inverse conversion of the initial conversion, can be performed to synchronize the operation and operation time of the register through a clock signal under the control of the controller, and the encryption operation and decryption operation through the mode signal under the control of the controller can be selected.

Referring to FIG. 2 , the bit serial HIGHT operation device according to an embodiment of the present invention may include a key scheduling module unit 110 , a round function module unit 120 , and the like.

The key scheduling module unit 110 selects and provides a whitening key for initial conversion and final conversion and a sub key for round operation using the input master key (MasterKey), but the master key is key shifted A whitening key or sub-key can be provided by operating through the register.

Here, the key scheduling module unit 110 includes a key shift register as a basis for selectively generating any one of a whitening key or a sub-key, and calculates each bit by 1 bit through the key shift register to generate a whitening key or a sub-key. The round function module can select and provide one bit at a time.

The round function module unit 120 performs initial transformation, round operation, and final transformation on the input plain text by using the whitening key or sub-key, and outputs the plain text inputted and stored in the first text shift register. It can be calculated using data and whitening key or sub-key.

Here, the round function module unit 120 may include a 1 byte second text shift register for calculating the first auxiliary function F0 and the second auxiliary function F1 in units of 8 bits in units of 1 bit. there is.

In addition, the round function module unit 120 stores in the second text shift register while performing a round operation on the text data of the even-numbered byte, and performs a second text shift when the round operation is performed on the text data of the odd-numbered byte. The result of the first auxiliary function or the second auxiliary function may be output bit by bit while the value stored in the register is cyclically shifted.

In addition, the round function module unit 120 outputs the result of the first auxiliary function or the second auxiliary function by 1 bit, performs a round operation on the result value of the first auxiliary function or the second auxiliary function, and performs a round operation. The output value obtained by performing ? is stored in the first text shift register, but in the case of an addition operation in which a carry occurs, a carry occurring in every cycle may be stored using a 1-bit flip-flop.

For example, the bit serial HIGHT operation device according to an embodiment of the present invention performs a module performing a round function as shown in FIG. 3 and key scheduling as shown in FIG. 4 . It may be provided as a module that executes. In each module, text is stored in a 64-bit shift register and a key value is stored in a 128-bit shift register, so that each module can be shifted by 1 bit every clock cycle.

In addition, the round function module can perform a 1-bit round operation using 1-bit data selected from an appropriate position among 8 positions of the text register and a 1-bit key received from the key scheduler.

In particular, as shown in FIG. 5 , a 1-byte shift register may be provided to implement the auxiliary functions F0 and F1 in units of 8 bits (1 byte) in units of 1 bit, and the text of the even-numbered byte (Even Byte) is may be stored in a shift register provided at the same time as performing a round operation, and then, when performing a round operation on the text of an odd-numbered byte (Odd Byte), F0, F1 in 1-bit units while cyclic shifting the previously stored value You can print the function result.

In particular, in the hardware of the bit serial HIGHT arithmetic device according to an embodiment of the present invention, the round operation and the conversion operation are bundled into one, and the result of one of the two types (Type A, Type B) to be calculated is selected and stored in the text register. It can be stored in an appropriate location, and in the case of an addition operation in which a carry occurs, a carry that occurs every cycle can be stored using a 1-bit flip-flop.

On the other hand, the key scheduler module may operate one bit at a time through the shift register in a similar manner to the round function module, and may provide the whitening key and the sub key to the round function module one bit at a time.

When the entire operation process according to time of the bit serial HIGHT operation device according to an embodiment of the present invention as described above will be described with reference to FIG. 6 , one cycle may correspond to 8 clock cycles, and each index is in 1 byte unit, the location of the data selected for round operation in the text register is indicated by a dotted line, the values that have been calculated are indicated in gray, and the key used in the round operation is indicated in gray in the key register. .

Here, in the encryption process, the position of the data calculated within one round is constant, but in the decryption process, it can be seen that the operation position is not constant, considering that the LFSR (Linear feedback shift register) value changes in the reverse order, At the end of the round operation, a one-byte rotation operation is performed on the data. In the hardware of the bit serial HIGHT operation device according to an embodiment of the present invention, instead of actually rotating it, the position at which the round operation is performed is appropriately selected in the text register. By selecting, you can perform a virtual rotation.

Accordingly, the present invention can minimize the multiplexer (MUX) required for data control by implementing the text register and the key register as shift registers, and the auxiliary function in units of bytes is implemented in units of 1 bit through an additional shift register. By adjusting the position of the data to be calculated by implementing , it is possible to perform 1-bit operation in every cycle without delay.

Next, a whitening key and a sub-key are provided by performing an operation through a 128-bit shift register using the master key in the bit serial HIGHT arithmetic device having the configuration as described above, and the data selected from the 64-bit shift register and the whitening key or sub key The process of performing a round operation through a key will be described.

7 is a step-by-step flowchart illustrating a process of performing a bit serial HIGHT operation according to another embodiment of the present invention.

Referring to FIG. 7 , a whitening key for initial conversion and final conversion and a sub key for round operation are selected and provided using the input master key, but the whitening key or sub key is calculated by calculating the master key through the key shift register. may be provided (step 710).

Here, the key scheduling module unit 110 includes a key shift register that is the basis for selectively generating any one of a whitening key or a sub-key, and calculates 1 bit each through the key shift register to generate a whitening key or a sub-key. The round function module can select and provide one bit at a time.

Next, the input plain text is output by performing initial transformation, round operation, and final transformation using the whitening key or sub-key, but the plain text is input and the shift data stored in the first text shift register and the whitening key or sub-key are used. can be calculated (step 720).

Here, the round function module unit 120 may include a 1 byte second text shift register for operating the first auxiliary function F0 and the second auxiliary function F1 in units of 8 bits in units of 1 bit. there is.

Then, the round function module unit 120 stores in the second text shift register while performing a round operation on the text data of the even-numbered byte, and when the round operation is performed on the text data of the odd-numbered byte, the second text shift The result of the first auxiliary function or the second auxiliary function may be output bit by bit while the value stored in the register is cyclically shifted.

In addition, the round function module unit 120 outputs the result of the first auxiliary function or the second auxiliary function by 1 bit, performs a round operation on the result value of the first auxiliary function or the second auxiliary function, and performs a round operation. The output value obtained by performing ? is stored in the first text shift register, but in the case of an addition operation in which a carry occurs, a carry occurring in every cycle may be stored using a 1-bit flip-flop.

Accordingly, the present invention also provides a whitening key for initial conversion and final conversion and a sub-key for round operation using the input master key, but the whitening key or sub-key is calculated by calculating the master key through the key shift register. is generated, and the input plaintext is output by performing initial transformation, round operation, and final transformation using the whitening key or subkey, but the plaintext is input and the shift data stored in the first text shift register and the whitening key or subkey are output. can be calculated using

In particular, since the structure of the bit serial HIGHT operation device proposed in the present invention replaces the text register and the key register with a shift register, and most of the registers except for a specific position are shifted to the next position without exception, it is necessary for data control. The advantage is that most of the multiplexer can be eliminated.

In addition, the present invention can implement 1-bit unit of auxiliary functions (F0, F1) including byte-unit cyclic shift operation by utilizing a 1-byte shift register, so that the entire round operation unit can be configured in 1-bit units. In addition, since the hardware that performs encryption and decryption operations is the same except for the control signal, reconfigurable hardware between encryption and decryption can be implemented in a low area without additional cost, and the entire hardware area can be reduced to the conventional round-based HIGHT structure. can be significantly reduced compared to

On the other hand, the bit serial HIGHT calculation method as described above may be provided as a computer-readable recording medium storing a computer program,

The computer program, when executed by a processor,

A whitening key for initial conversion and final conversion and a sub key for round operation are selected and provided using the input master key (MasterKey), but the whitening is performed by calculating the master key through a key shift register providing a key or sub-key;

The input plain text is output by performing the initial transformation, round operation, and final transformation using the whitening key or sub-key, but the plain text is inputted and the shift data stored in the first text shift register and the whitening key Alternatively, it may include an instruction for causing the processor to perform a method including calculating using a subkey.

In addition, the bit serial HIGHT calculation method as described above may be provided as a computer program stored in a computer-readable recording medium,

The computer program, when executed by a processor,

A whitening key for initial conversion and final conversion and a sub key for round operation are selected and provided using the input master key (MasterKey), but the whitening is performed by calculating the master key through a key shift register providing a key or sub-key;

The input plain text is output by performing the initial transformation, round operation, and final transformation using the whitening key or sub-key, but the plain text is inputted and the shift data stored in the first text shift register and the whitening key Alternatively, it may include an instruction for causing the processor to perform a method including calculating using a subkey.

In the above description, various embodiments of the present invention have been presented and described, but the present invention is not necessarily limited thereto. It will be readily appreciated that branch substitutions, transformations and alterations are possible.

110: key scheduling module unit
120: round function module unit

Claims (12)

A whitening key for initial conversion and final conversion and a sub key for round operation are selected and provided using the input master key (MasterKey), but the whitening is performed by calculating the master key through a key shift register a key scheduling module unit for providing a key or sub-key;
The input plain text is output by performing the initial transformation, round operation, and final transformation using the whitening key or sub-key, but the plain text is inputted and the shift data stored in the first text shift register and the whitening key or a round function module unit that operates using a subkey,
The key scheduling module unit includes a key shift register that is a basis for selectively generating any one of the whitening key or the sub-key, and calculates each bit by 1 bit through the key shift register to obtain the whitening key or the sub-key. Bit serial HIGHT arithmetic device that selects and provides 1 bit by bit to the round function module unit
delete The method of claim 1,
wherein the round function module unit includes a 1-byte second text shift register for calculating the first auxiliary function and the second auxiliary function in units of 8 bits in units of 1 bit.
4. The method of claim 3,
The round function module unit stores in the second text shift register while performing the round operation on the text data of the even-numbered byte, and when the round operation is performed on the text data of the odd-numbered byte, the second text shift A bit serial HIGHT arithmetic device that outputs the result of the first auxiliary function or the second auxiliary function bit by bit while cyclically shifting a value stored in a register.
5. The method of claim 4,
The round function module unit outputs the result of the first auxiliary function or the second auxiliary function one bit at a time, performs the round operation on the result value of the first auxiliary function or the second auxiliary function, and performs the round operation A bit serial that stores the output value obtained by performing , in the first text shift register, and stores the carry occurring in every cycle using a 1-bit flip-flop in the case of an addition operation in which a carry occurs. HIGHT computing unit.
A whitening key for initial conversion and final conversion and a sub key for round operation are selected and provided using the input master key (MasterKey), but the whitening is performed by calculating the master key through a key shift register providing a key or sub-key;
The input plain text is output by performing the initial transformation, round operation, and final transformation using the whitening key or sub-key, but the plain text is inputted and the shift data stored in the first text shift register and the whitening key Or comprising the step of calculating using a subkey,
In the step of providing the whitening key or sub-key, the whitening key or the sub-key is calculated by 1 bit each through a key shift register that is a basis for selectively generating any one of the whitening key or the sub-key, and the whitening key or the sub-key is converted into a round function. Bit serial HIGHT calculation method that selects and provides 1 bit by module part.
delete 7. The method of claim 6,
The step of calculating using the whitening key or sub-key is a bit serial HIGHT operation having a 1 byte second text shift register for calculating the first auxiliary function in units of 8 bits and the second auxiliary function in units of 1 bit. method.
9. The method of claim 8,
The operation using the whitening key or sub-key includes storing the round operation on the even-numbered byte text data in the second text shift register while performing the round operation on the even-numbered byte text data, and performing the round operation on the odd-numbered byte text data. When executed, a bit serial HIGHT calculation method for outputting the result of the first auxiliary function or the second auxiliary function bit by bit while cyclically shifting the value stored in the second text shift register.
10. The method of claim 9,
In the calculating using the whitening key or sub-key, the result of the first auxiliary function or the second auxiliary function is outputted one bit at a time, and the rounding is performed with respect to the result value of the first auxiliary function or the second auxiliary function. An operation is performed and the output value obtained by performing the round operation is stored in the first text shift register, but in the case of an addition operation in which a carry occurs, it occurs every cycle using a 1-bit flip-flop. Bit serial HIGHT calculation method for storing the carry.
As a computer-readable recording medium storing a computer program,
The computer program, when executed by a processor,
A whitening key for initial conversion and final conversion and a sub key for round operation are selected and provided using the input master key (MasterKey), but the whitening is performed by calculating the master key through a key shift register providing a key or sub-key;
The input plain text is output by performing the initial transformation, round operation, and final transformation using the whitening key or sub-key, but the plain text is inputted and the shift data stored in the first text shift register and the whitening key or an instruction for causing the processor to perform a method comprising the step of calculating using a subkey,
In the step of providing the whitening key or sub-key, the whitening key or the sub-key is calculated by 1 bit each through a key shift register that is a basis for selectively generating any one of the whitening key or the sub-key, and the whitening key or the sub-key is converted into a round function. Provides a selection of 1 bit at a time to the module part
computer readable recording medium.
As a computer program stored in a computer-readable recording medium,
The computer program, when executed by a processor,
By using the input master key (MasterKey), a whitening key for initial and final conversion and a sub key for round operation are selected and provided, but the whitening key is calculated through a key shift register to perform the whitening providing a key or sub-key;
The input plain text is output by performing the initial transformation, round operation, and final transformation using the whitening key or sub-key, but the plain text is inputted and the shift data stored in the first text shift register and the whitening key or an instruction for causing the processor to perform a method comprising the step of calculating using a subkey,
In the step of providing the whitening key or sub-key, the whitening key or the sub-key is calculated by 1 bit each through a key shift register that is a basis for selectively generating any one of the whitening key or the sub-key, and the whitening key or the sub-key is converted into a round function. Provides a selection of 1 bit at a time to the module part
computer program.

Images