KR101849571B1 - Gate driving circuit - Google Patents

Abstract

The present invention relates to a gate drive circuit, and more particularly to a gate drive circuit capable of stabilizing an output from a stage by preventing leakage of charge from a voltage of a set node, wherein n is an integer of 2 or more A first clock generator for outputting clock pulses for controlling the output of the first clock generator; (M is a natural number) output clock pulses having different phases and having a high-level portion overlapping each other, arranging the m * n output clock pulses in phase order, grouping them into n units, And a rising edge of the output clock pulses having a kth phase sequence of each group is generated in a high period of a clock pulse for output control having a kth phase sequence among the n output control clock pulses, A second clock generator for outputting m * n output clock pulses so as to be located within the first clock generator; And a shift register for receiving n output control clock pulses from the first clock generator and m * n output clock pulses from the second clock generator and sequentially outputting a plurality of scan pulses .

Description

[0001] GATE DRIVING CIRCUIT [0002]

The present invention relates to a gate drive circuit, and more particularly to a gate drive circuit capable of stabilizing an output from a stage by preventing leakage of a charge from a voltage of a set node.

The shift register sequentially outputs a plurality of scan pulses to sequentially drive gate lines of a display device such as a liquid crystal display device. For this purpose, the shift register includes a plurality of switching elements therein, and an oxide semiconductor transistor may be used as the switching element.

1 is a graph showing a relationship between a gate voltage and a drain current according to a temperature of a conventional oxide semiconductor transistor.

When an N-type oxide semiconductor transistor is used in a shift register, it is preferable that its threshold voltage has a positive value. However, as shown in FIG. 1, as the temperature increases, the threshold voltage of the oxide semiconductor transistor shifts in the negative direction. As a result, the N-type oxide semiconductor transistor to be turned off in the output period of the shift register The leakage current does not normally turn on at a high temperature and the voltage of the set node is lowered due to the leakage current and the output of the shift register is not normally generated.

FIG. 2 is a view showing voltage and scan pulse voltage of a set node according to a change in threshold voltage of a conventional oxide semiconductor transistor.

As shown in FIG. 2A, when the threshold voltage of the oxide semiconductor transistor is -1, the voltage of the set node is lowered rapidly due to the leakage current of the oxide semiconductor transistor, so that the output, that is, the voltage of the scan pulse, It can be seen that it is descending.

Also, as shown in FIG. 2B, when the threshold voltage of the oxide semiconductor transistor is -3, the leakage current of the oxide semiconductor transistor is further increased, so that the voltage of the set node is not even raised. As a result, no scan pulse is generated at all .

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and it is an object of the present invention to provide a method and an apparatus for controlling a clock pulse supplied to a pull- So that a leakage current from the set node can be prevented, thereby generating a normally generated gate drive circuit.

According to another aspect of the present invention, there is provided a gate driving circuit comprising: a first clock generator for outputting n (n is a natural number equal to or greater than 2) output clock pulses having different phases; (M is a natural number) output clock pulses having different phases and having a high-level portion overlapping each other, arranging the m * n output clock pulses in phase order, grouping them into n units, And a rising edge of the output clock pulses having a kth phase sequence of each group is generated in a high period of a clock pulse for output control having a kth phase sequence among the n output control clock pulses, A second clock generator for outputting m * n output clock pulses so as to be located within the first clock generator; And a shift register for receiving n output control clock pulses from the first clock generator and m * n output clock pulses from the second clock generator and sequentially outputting a plurality of scan pulses .

Each of the n output control clock pulses and the m * n output clock pulses includes a plurality of impulses periodically generated; the rising edge of the impulse included in the output clock pulse belonging to the group j (j is a natural number equal to or smaller than m) and having the kth phase order is within the high interval of the impulse of the output controlling clock pulse having the kth phase order .

the m * nth output clock pulse further comprises a dummy impulse; And the dummy impulse has the same output timing as a start pulse having a phase prior to the first output clock pulse.

The voltage of each row section of the n output control clock pulses is less than or equal to the voltage of each row section of the m * n output clock pulses.

And each of the m * n output clock pulses does not overlap with at least one of the n output control clock pulses.

Wherein the shift register comprises a plurality of stages for sequentially outputting scan pulses; Each of the stages outputs a scan pulse through its output terminal; The n output control clock pulses are transmitted through n output control clock lines; The m * n output clock pulses are transmitted through m * n output clock lines; The p-th (p is a natural number) stage is turned on or off according to any one of the n output control clock pulses. The output terminal of the pq-th stage (q is a natural number smaller than p) A first switching element for connecting any one of the start transmission lines for transmitting the start pulse and the set node to each other; And a second switching power supply line connected to the set node and a first discharge power supply line for transmitting the first discharge voltage when the switch is turned on according to any one of the n output control clock pulses, device; And a pull-up switching element that is turned on or off according to a voltage applied to the set node and connects output terminals of one of the output clock lines and the output terminal of the p-th stage in turn-on state; The high section of the output clock pulse and the high section of the output control clock pulse supplied to the second switching element do not overlap; The voltage of the low section of each of the n output control clock pulses is less than or equal to the first discharge voltage; A high period of the output clock pulse supplied to the p-q stage is partially overlapped with a high period of the output clock pulse supplied to the p stage; And a rising edge of an output clock pulse supplied to the pull-up switching element is located within a high period of an output control clock pulse supplied to the first switching element.

And q is one of 1 and 2.

The p-th stage is turned on or off according to a clock pulse for output from any one of the output clock lines. The p-th stage is connected to the charge power supply line for transferring the charge voltage at the turn- 3 switching device; A fourth switching device that turns on or off according to a voltage applied to the set node and connects the reset node and a second discharge power supply line that transmits a second discharge voltage when turning on; And a third discharging power supply line for transmitting a third discharging voltage to the output terminal of the pth stage at the time of turn-on, Further comprising a pull-down switching element; And the pull-up switching element and the third switching element are supplied with the same output clock pulse.

The p-th stage is turned on or off according to a scan pulse from the (p + r) th (r is a natural number) stage, 5 switching devices; A sixth switching device that is turned on or off according to a voltage applied to the output terminal of the pth stage and connects the reset node and the second discharge power supply line to each other when turned on; A seventh switching device that turns on or off according to a scan pulse from the p + rth stage and connects the output terminal of the pth stage to the third discharge power supply line when turned on; And an eighth switching element that turns on or off according to a scan pulse from the psth (s is a natural number) stage and connects the charging power supply line and the set node when turned on, . ≪ / RTI >

The voltage of the high section of each of the m * n output clock pulses is equal to or greater than the voltage of the high section of each of the n output control clock pulses.

The p-th stage is turned on or off according to a clock pulse for output from any one of the output clock lines. The p-th stage is connected to the charging power supply line for transmitting the charging voltage at the turn- device; A fourth switching element that turns on or off according to a voltage applied to the set node and connects the common node and a second discharging power supply line for transmitting a second discharging voltage upon turning on; A fifth switching element that is turned on or off according to a voltage applied to the common node and connects the charging power supply line and the reset node when turned on; A sixth switching element that is turned on or off according to a voltage applied to the set node and connects the reset node and the second discharge power supply line to each other when the switch is turned on; And a third discharging power supply line for transmitting a third discharging voltage to the output terminal of the pth stage at the time of turn-on, Further comprising a pull-down switching element; And the pull-up switching element and the third switching element are supplied with the same output clock pulse.

a third switching device that turns on or off according to a scan pulse from the p-rth stage and connects the set node with a charging power supply line for transmitting a charging voltage when turning on; A fourth switching element that is turned on or off according to a voltage applied to the set node and connects the reset node to a second power supply line for transmitting a second discharge voltage; And a third discharge power supply line for transmitting a third discharge voltage at an output terminal of the p-th stage at the time of turn-on, wherein the third discharge power supply line is turned on or off according to a voltage applied to the reset node, device; And a capacitor connected between the output clock transmission line connected to the pull-up switching element and the reset node.

a third switching device that turns on or off according to a scan pulse from the p-st stage and connects the set node with a charging power supply line for transmitting a charging voltage when turning on; A fourth switching element that is turned on or off according to an output clock pulse from any one of the output clock lines and connects the charging power supply line for transmitting the charging voltage at the turn-on time and the reset node to each other; A fifth switching element that turns on or off according to a voltage applied to the set node and connects the reset node and a second discharge power supply line that transmits a second discharge voltage when turning on; And a third discharging power supply line for transmitting a third discharging voltage to the output terminal of the pth stage at the time of turn-on, Further comprising a pull-down switching element; And the fourth switching element and the pull-up switching element are supplied with the same output clock pulse.

The p-th stage is turned on or off according to the voltage applied to the output terminal of the p-th stage, and the second power supply line for transmitting the second discharge voltage to the turn- A third switching element connected to the third switching element; A fourth switching element that is turned on or off according to an output clock pulse from any one of the output clock lines and connects the charging power supply line for transmitting the charging voltage at the turn-on time and the reset node to each other; A fifth switching element that is turned on or off according to a voltage applied to the set node and connects the reset node and the second discharge power supply line to each other when turned on; And a third discharging power supply line for transmitting a third discharging voltage to the output terminal of the pth stage at the time of turn-on, Further comprising a pull-down switching element; And the fourth switching element and the pull-up switching element are supplied with the same output clock pulse.

A third switching element that is turned on according to a charging voltage from the charging power supply line and connects the charging power supply line and the reset node to each other; And a second discharging power supply line for transmitting the second discharging voltage to the reset node when the first discharging power supply line is turned on according to a clock pulse for output from any one of the output clock transmission lines, 4 switching devices; And a third discharging power supply line for transmitting a third discharging voltage to the output terminal of the pth stage at the time of turn-on, Further comprising a pull-down switching element; And the fourth switching element and the pull-up switching element are supplied with the same output clock pulse.

A third switching element that is turned on according to a charging voltage from the charging power supply line and connects the charging power supply line and the reset node to each other; And a second discharging power supply line for transmitting the second discharging voltage to the reset node when the first discharging power supply line is turned on according to a clock pulse for output from any one of the output clock transmission lines, 4 switching devices; A fifth switching element that turns on or off according to a voltage applied to the set node and connects the reset node and a second discharge power supply line that transmits a second discharge voltage when turning on; And a pulldown switching element that is turned on or off according to a voltage applied to the reset node and connects the output terminal of the pth stage and the third discharge power supply line to each other when the turn-on is turned on; And the fourth switching element and the second switching element are supplied with the same output clock pulse

And the high sections of the n output control clock pulses do not overlap with each other.

At least two of the first to third discharge voltages are equal to each other.

Wherein the shift register comprises a plurality of stages for sequentially outputting scan pulses; Each of the stages outputs a scan pulse through its output terminal; The n output control clock pulses are transmitted through n output control clock lines; The m * n output clock pulses are transmitted through m * n output clock lines; The p-th (p is a natural number) stage is turned on or off according to any one of the n output control clock pulses. The output terminal of the pq-th stage (q is a natural number smaller than p) A first switching element for connecting any one of the start transmission lines for transmitting the start pulse and the set node to each other; A pull-up switching element which is turned on or off according to a voltage applied to the set node and connects the output terminal of one of the output clock lines and the output terminal of the p-th stage when the switch is turned on; A third switching element that is turned on or off according to an output clock pulse from any one of the output clock lines and connects the charging power supply line for transmitting the charging voltage at the turn-on time and the reset node to each other; A fourth switching device that turns on or off according to a voltage applied to the set node and connects the reset node and a second discharge power supply line that transmits a second discharge voltage when turning on; And a third discharging power supply line for transmitting a third discharging voltage to the output terminal of the pth stage at the time of turn-on, A pull-down switching element; Wherein the pull-up switching element and the third switching element receive the same output clock pulse; The voltage of the low interval of each of the n output control clock pulses is less than or equal to the second and third discharge voltages; A high period of the output clock pulse supplied to the p-q stage is partially overlapped with a high period of the output clock pulse supplied to the p stage; And a rising edge of an output clock pulse supplied to the pull-up switching element is located within a high period of an output control clock pulse supplied to the first switching element.

Wherein the shift register comprises a plurality of stages for sequentially outputting scan pulses; Each of the stages outputs a scan pulse through its output terminal; The n output control clock pulses are transmitted through n output control clock lines; The m * n output clock pulses are transmitted through m * n output clock lines; The p-th (p is a natural number) stage is turned on or off according to any one of the n output control clock pulses. The output terminal of the pq-th stage (q is a natural number smaller than p) A first switching element for connecting any one of the start transmission lines for transmitting the start pulse and the set node to each other; A pull-up switching element which is turned on or off according to a voltage applied to the set node and connects the output terminal of one of the output clock lines and the output terminal of the p-th stage when the switch is turned on; A third switching device that turns on or off according to a clock pulse for output from any one of the output clock lines and connects the output clock line and the reset node to each other upon turning on; A fourth switching device that turns on or off according to a voltage applied to the set node and connects the reset node and a second discharge power supply line that transmits a second discharge voltage when turning on; And a third discharging power supply line for transmitting a third discharging voltage to the output terminal of the pth stage at the time of turn-on, A pull-down switching element; Wherein the pull-up switching element and the third switching element receive the same output clock pulse; The high section of the output clock pulse and the high section of the output control clock pulse supplied to the first switching element do not overlap; The voltage of the low interval of each of the n output control clock pulses is less than or equal to the second and third discharge voltages; A high period of the output clock pulse supplied to the p-q stage is partially overlapped with a high period of the output clock pulse supplied to the p stage; And a rising edge of an output clock pulse supplied to the pull-up switching element is located within a high period of an output control clock pulse supplied to the first switching element.

Wherein the shift register comprises a plurality of stages for sequentially outputting scan pulses; Each of the stages outputs a scan pulse through its output terminal; The n output control clock pulses are transmitted through n output control clock lines; The m * n output clock pulses are transmitted through m * n output clock lines; The p-th (p is a natural number) stage is turned on or off according to any one of the n output control clock pulses. The output terminal of the pq-th stage (q is a natural number smaller than p) A first switching element for connecting any one of the start transmission lines for transmitting the start pulse and the set node to each other; A pull-up switching element which is turned on or off according to a voltage applied to the set node and connects the output terminal of one of the output clock lines and the output terminal of the p-th stage when the switch is turned on; A third switching device that is turned on according to a charging voltage from a charging power supply line and connects one of the output clock lines and the reset node to each other; A fourth switching device that turns on or off according to a voltage applied to the set node and connects the reset node and a second discharge power supply line that transmits a second discharge voltage when turning on; And a third discharging power supply line for transmitting a third discharging voltage to the output terminal of the pth stage at the time of turn-on, A pull-down switching element; Wherein the pull-up switching element and the third switching element receive the same output clock pulse; The high section of the output clock pulse and the high section of the output control clock pulse supplied to the first switching element do not overlap; The voltage of the low interval of each of the n output control clock pulses is less than or equal to the second and third discharge voltages; A high period of the output clock pulse supplied to the p-q stage is partially overlapped with a high period of the output clock pulse supplied to the p stage; And a rising edge of an output clock pulse supplied to the pull-up switching element is located within a high period of an output control clock pulse supplied to the first switching element.

Wherein the shift register comprises a plurality of stages for sequentially outputting scan pulses; Each of the stages outputs a scan pulse through its output terminal; The n output control clock pulses are transmitted through n output control clock lines; The m * n output clock pulses are transmitted through m * n output clock lines; The p-th (p is a natural number) stage is turned on or off according to any one of the n output control clock pulses. The output terminal of the pq-th stage (q is a natural number smaller than p) A first switching element for connecting any one of the start transmission lines for transmitting the start pulse and the set node to each other; A pull-up switching element which is turned on or off according to a voltage applied to the set node and connects the output terminal of one of the output clock lines and the output terminal of the p-th stage when the switch is turned on; A third switching element that is turned on or off according to an output clock pulse from any one of the output clock lines and connects the charging power supply line for transmitting the charging voltage at the turn-on time and the common node to each other; A fourth switching element that turns on or off according to a voltage applied to the set node and connects the common node and a second discharging power supply line for transmitting a second discharging voltage upon turning on; A fifth switching element that is turned on or off according to a voltage applied to the common node and connects the charging power supply line and the reset node when turned on; A sixth switching element that is turned on or off according to a voltage applied to the set node and connects the reset node and the second discharge power supply line to each other when the switch is turned on; And a third discharging power supply line for transmitting a third discharging voltage to the output terminal of the pth stage at the time of turn-on, A pull-down switching element; The high section of the output clock pulse and the high section of the output control clock pulse supplied to the first switching element do not overlap; The voltage of the low interval of each of the n output control clock pulses is smaller than the second and third discharge voltages; Wherein the pull-up switching element and the third switching element receive the same output clock pulse; A high period of the output clock pulse supplied to the p-q stage is partially overlapped with a high period of the output clock pulse supplied to the p stage; And a rising edge of an output clock pulse supplied to the pull-up switching element is located within a high period of an output control clock pulse supplied to the first switching element.

According to the present invention, since the low voltage of the output control clock pulse is set to be smaller than the low voltage (corresponding to the low voltage of the scan pulse) of the output clock pulse and smaller than the first to third discharge voltage, The current leaked through the first and second switching elements can be minimized in a period in which the pulse is held at the low voltage. Therefore, the output from the shift register can be stabilized.

1 is a graph showing a relationship between a gate voltage and a drain current according to the temperature of a conventional oxide semiconductor transistor;
2 is a graph showing a voltage and a scan pulse voltage of a set node according to a change in threshold voltage of a conventional oxide semiconductor transistor
3 is a view showing a gate drive circuit according to an embodiment of the present invention
4 is a timing chart of clock pulses for output control and output clock pulses according to the first embodiment;
5 is a timing chart of clock pulses for output control and output clock pulses according to the first embodiment;
6 is a detailed configuration diagram of the shift register of FIG.
Figs. 7 to 17 are diagrams showing the configurations of the stages according to the first to eleventh embodiments
18 is a diagram showing simulation waveforms for the first to fourth output clock pulses and the first to fourth output control clock pulses of FIG. 4
FIG. 19 is a diagram showing simulation waveforms for positive clock pulses and semi-iso clock pulses for the first output clock pulse in FIG. 18
FIG. 20 is a diagram showing simulation waveforms for voltages of set nodes, reset nodes, scan pulses, and output clock pulses generated according to the operation of the stage of FIG. 8
FIG. 21 is a diagram showing simulation waveforms for voltages of set nodes, reset nodes, scan pulses, and output clock pulses generated according to the operation of the stage of FIG. 11
22 is a diagram showing simulation waveforms for output control clock pulses and output clock pulses supplied to the stages of Figs. 13 and 14
23 is a diagram showing a simulation waveform for the voltages of the set node, the reset node, the scan pulse, and the output clock pulse generated in accordance with the operation of the stage of Fig. 10
24 is a diagram showing simulation waveforms for voltages of set nodes, reset nodes, scan pulses, and output clock pulses generated in accordance with the operation of the stage of Fig. 12
FIG. 25 is a diagram showing a simulation waveform for the voltages of the set node, the reset node, the scan pulse, and the output clock pulse generated in accordance with the operation of the stage of FIG. 16
FIG. 26 is a diagram showing a simulation waveform for a voltage of a set node, a reset node, a scan pulse, and an output clock pulse generated according to the operation of the stage of FIG. 17
Fig. 27 is a view showing a modified structure of Fig. 8
28 is a view showing a modified structure of Fig. 27
29 is a view showing another modified structure of Fig. 27
30 is a view showing another modified structure of Fig. 10

3 is a view illustrating a gate driving circuit according to an embodiment of the present invention.

The gate driving circuit according to the embodiment of the present invention includes a first clock generator CG1, a second clock generator CG2 and a shift register SR, as shown in Fig.

The first clock generator CG1 outputs n (n is a natural number of 2 or more) output control clock pulses i-CLK having different phases. The n output control clock pulses are transmitted through n output control clock lines.

The second clock generator CG2 outputs m * n output clock pulses CLK having different phases. Particularly, the second clock generator CG2 generates m * n (m is a natural number) output clock pulses having different phases and having a high-level section overlapping each other, and outputs the m * n output clock pulses as phase And group them into m to generate n groups having m output clock pulses. And the rising edge of the output clock pulses having the kth phase order of each group is located within the high period of the output control clock pulse having the kth phase sequence out of the n output control clock pulses, m * n output clock pulses Lt; / RTI > These m * n output control clock pulses are transmitted through m * n output clock lines.

Wherein each of n output control clock pulses and m * n output clock pulses includes a plurality of impulses generated periodically. Within the high interval of the impulse of the output control clock pulse belonging to the group j (j is a natural number less than or equal to n) and having a kth phase order that is the rising edge of the first impulse included in the output clock pulse having the kth phase order Located.

The m * nth output clock pulse may further include a dummy impulse, which has the same output timing as a start pulse having a phase earlier than the first output clock pulse.

the voltage of each row interval of the n output control clock pulses is smaller than the voltage of each row interval of the m * n output clock pulses.

each of the m * n output clock pulses does not overlap with at least one of the n output control clock pulses.

The shift register SR is supplied with n output control clock pulses from the first clock generator CG1 and m * n output clock pulses from the second clock generator CG2, And sequentially outputs scan pulses of a predetermined number (e.g., a natural number).

The output control clock pulses output from the first clock generator CG1 and the output clock pulses output from the second clock generator CG2 will now be described.

4 is a timing chart of clock pulses for output control and output clock pulses according to the first embodiment.

As shown in FIG. 4, the output control clock pulses include four kinds of output control clock pulses (i-CLK1 to i-CLK4) having different phases. The output clock pulses include four kinds of output clock pulses having different phases Output clock pulses CLK1 to CLK4. 4 shows waveforms of clock pulses for output control and output clock pulses when n = 4, m = 1, and j = 1.

As shown in FIG. 4, the high sections of the first to fourth output clock pulses CLK1 to CLK4 overlap each other by a third. The first to fourth output clock pulses CLK1 to CLK4 each include a plurality of impulses which are generated periodically.

The first to fourth output control clock pulses (i-CLK1 to i-CLK4) include a plurality of impulses generated periodically or non-periodically, respectively. The high sections of the first to fourth output control clock pulses (i-CLK1 to i-CLK4) may or may not overlap with each other. In Fig. 4, the first to fourth output control clock pulses i-CLK1 to i-CLK4 in which the high period does not overlap are shown. The first to fourth output control clock pulses (i-CLK1 to i-CLK4) are transmitted through the first to fourth output control clock lines.

The voltage of each row interval of the first to fourth output control clock pulses i-CLK1 to i-CLK4 is less than or equal to the voltage of each row interval of the first to fourth output clock pulses CLK1 to CLK4. The first to fourth output clock pulses CLK1 to CLK4 are transmitted through the first to fourth output clock lines.

As shown in Fig. 4, the rising edge of the first output clock pulse CLK1 is located in the high period of the first output control clock pulse i-CLK1. The rising edge of the second output clock pulse CLK2 is located in the high period of the second output control clock pulse (i-CLK2). The rising edge of the third output clock pulse CLK3 is located in the high period of the third output control clock pulse (i-CLK3). The rising edge of the fourth output clock pulse CLK4 is located in the high period of the fourth output control clock pulse (i-CLK4).

The high period of the first output clock pulse CLK1 overlaps with the first to third output control clock pulses i-CLK1 to i-CLK3, but does not overlap with the fourth output control clock pulse i-CLK4 . The high period of the second output clock pulse CLK2 overlaps with the second to fourth output control clock pulses i-CLK2 to i-CLK4, but does not overlap with the first output control clock pulse i-CLK1 . The high period of the third output clock pulse CLK3 overlaps with the third, fourth and first output control clock pulses i-CLK3, i-CLK4, i-CLK1 while the second output control clock pulse i -CLK2). The high period of the fourth output clock pulse CLK4 overlaps with the fourth, first and second output control clock pulses i-CLK4, i-CLK1, i-CLK2 while the third output control clock pulse i -CLK3).

When the first output control clock pulse (i-CLK1) having the high period including the rising edge of the first output clock pulse (CLK1) is defined as the iso clock pulse, the first output clock pulse (CLK1) (I-CLK4) for the fourth output control which does not overlap with the high period of the clock signal CLK4 can be defined as a half-iso clock pulse corresponding to the small clock pulse. 4, the first output control clock pulse (i-CLK1) and the fourth output control clock pulse (i-CLK4) are the small and semi-iso clock pulses for the first output clock pulse (CLK1) The second output control clock pulse (i-CLK2) and the first output control clock pulse (i-CLK1) are the small and half isochronous clock pulses for the second output clock pulse CLK2, and the third output control clock pulse (i-CLK3) and the second output control clock pulse (i-CLK2) are positive and negative quasi clock pulses for the third output clock pulse CLK3, respectively, and the fourth output control clock pulse (i- And the third output control clock pulse (i-CLK3) are positive and negative quasi clock pulses for the fourth output clock pulse (CLK4), respectively.

The clock pulses and the semi-iso clock pulses, which correspond to each other, may overlap each other or not overlap each other. For example, the first output control clock pulse (i-CLK1) and the fourth output control clock pulse (i-CLK4) having positive and negative quadrature relations with respect to the first output clock pulse (CLK1) They may not overlap.

Meanwhile, in FIG. 4, the first impulse generated among the impulses included in the fourth output clock pulse CLK4 is a dummy impulse. This dummy impulse is synchronized with the start pulse.

5 is a timing chart of clock pulses for output control and output clock pulses according to the first embodiment.

As shown in FIG. 5, the high sections of the first through sixth output clock pulses CLK1 through CLK6 overlap one another by one third. The first to sixth output clock pulses CLK1 to CLK6 each include a plurality of impulses periodically generated.

The first to third output control clock pulses (i-CLK1 to i-CLK3) include a plurality of impulses generated cyclically or non-periodically, respectively. The high periods of the first to third output control clock pulses (i-CLK1 to i-CLK3) may or may not overlap with each other. 5 shows the first to third output control clock pulses (i-CLK1 to i-CLK3) in which the high period does not overlap.

The voltage (low voltage) in each row section of the first to third output control clock pulses i-CLK1 to i-CLK3 is a voltage (low voltage) of each low section of the first to sixth output clock pulses CLK1 to CLK6 Voltage).

As shown in FIG. 5, the output control clock pulses include three types of output control clock pulses having different phases, and the output clock pulses include six output clock pulses having different phases. 5 shows waveforms of output clock pulses and output clock pulses when n is 3, m is 2, and j is 2.

The output clock pulses and the output control clock pulses can have a relationship of m: 1, and FIG. 5 shows an example in which the output clock pulses and the output control clock pulses have a 2: 1 relationship.

The first group includes the first to third output clock pulses CLK3, and the second group includes the fourth to sixth output clock pulses. The rising edge of the output clock pulses having the kth phase order in each group is located in the high period of the output control clock pulse having the kth phase order. For example, the rising edge of the first output clock pulse CLK1 having the first phase order in the first group and the rising edge of the fourth output clock pulse CLK4 having the first phase order in the second group (I-CLK1) for the first output control having the first phase sequence. Specifically, the rising edge of the first output clock pulse CLK1 is located in a high section of the first impulse of the first output control clock pulse (i-CLK1), and the rising edge of the fourth output clock pulse CLK4 1 < / RTI > output control clock pulse (i-CLK1).

In the same manner, each rising edge of the second and fifth output clock pulses is located in a high period of the second output control clock pulse (i-CLK2), and each rising edge of the third and sixth output clock pulses is 3 output control clock pulse (i-CLK3).

The first to third output control clock pulses (i-CLK1 to i-CLK3) in Fig. 5 can also be defined as positive clock pulses and semi-iso clock pulses as described above.

That is, the first output control clock pulse (i-CLK1) and the third output control clock pulse (i-CLK3) are the small and semi-iso clock pulses for the first and fourth output clock pulses (CLK4) 2 output control clock pulse (i-CLK2) and the first output control clock pulse (i-CLK1) are the small and half isochronous clock pulses for the second and fifth output clock pulses, respectively, and the third output control clock pulse i-CLK3 and the first output control clock pulse (i-CLK1) are the small and half-iso clock pulses for the third and sixth output clock pulses, respectively.

In FIG. 5, the impulse generated at the beginning of the impulses included in the sixth output clock pulse CLK6 is a dummy impulse. This dummy impulse is synchronized with the start pulse.

4 and 5 may be applied to the shift register SR of FIG. 1, for output control clock pulses and output clock pulses.

6 is a detailed configuration diagram of the shift register SR of FIG.

The shift register SR according to the embodiment of the present invention includes h stages ST1 to STh as shown in Fig. Here, each of the stages ST1 to STh + 1 outputs one scan pulse (SP1 to SPh + 1) for one frame period through each output terminal OT.

Each of the stages ST1 to STh drives a gate line connected thereto by using a scan pulse. In addition, each stage ST1 to STh + 1 controls the operation of the stage located at the rear end from itself. Further, according to the configuration of the shift register, each stage may control not only the rear stage but also the operation of the stage located at the preceding stage from the stage itself. At this time, a dummy stage for supplying a scan pulse to the h-th stage is further provided at the rear stage of the h-th stage STh. Depending on the configuration of the shift register, this dummy stage can be a plurality, not one.

The stages ST1 to STh + 1 sequentially output scan pulses in the order of the first stage ST1 to the hth stage STh. That is, the first stage ST1 outputs the first scan pulse SP1, the second stage ST2 outputs the second scan pulse SP2, and the third stage ST3 outputs the second scan pulse SP2. Th scan pulse SP3 and finally the h-th stage STh outputs the h-th scan pulse SPn.

The scan pulses output from the stages ST1 to STh except for the dummy stage are sequentially supplied to the gate lines of the liquid crystal panel (not shown), thereby sequentially scanning the gate lines. The scan pulse output from the stages is supplied only to the stage located at the previous stage from the stage itself, or to the stage located at the front stage and to the stage located at the rear stage, or to the stage located at the rear stage.

Such a shift register SR may be incorporated in the liquid crystal panel. That is, the liquid crystal panel has a display portion for displaying an image and a non-display portion surrounding the display portion, and the shift register SR is embedded in the non-display portion.

The entire stages ST1 to STh + 1 of the shift register SR configured as described above are supplied with the above-described clock pulses for output control and output clock pulses. As shown in FIG. 6, Output control clock pulses (i-CLK1 to i-CLK4) and the first to fourth output clock pulses (CLK1 to CLK4) are shown.

6 shows a structure in which the p-th stage is supplied with a scan pulse from the (p-1) -th stage and a scan pulse from the (p + 2) -th stage. Instead of this structure, A scan pulse and a scan pulse from the p + 3 < th > stage may be supplied.

6 shows a structure in which the p-th stage is connected to the front stage and the rear stage. Instead of this structure, a structure in which the p-th stage is connected to the front stage is also possible.

The configuration of each stage will be described in more detail as follows.

FIGS. 7 to 17 are diagrams showing the configurations of the stages according to the first to eleventh embodiments, wherein i-CLKa and i-CLKb in the respective drawings denote a small clock pulse and a half- . That is, i-CLKa denotes a quasi-small clock pulse for CLKc, and i-CLKb denotes a half-isochronous pulse to CLKc.

In the stages of FIGS. 7 to 17, the first to fourth output control clock pulses (i-CLK1 to i-CLK4) and the first to fourth output clock pulses CLK1 to CLK4 shown in FIG. 4 are supplied .

The configuration of the stage according to the first embodiment will be described with reference to FIG.

As shown in FIG. 7, the p-th stage includes a first switching device Tr1, a second switching device Tr2, and a pullup switching device Pu.

The first switching device Tr1 provided in the p-th stage is turned on or off according to a small clock pulse, and the output terminal OT of the (p-1) -th stage and the set node Q Connect each other. Here, when the pth stage is the first stage to receive the start pulse, the first switching device Tr1 is connected to the start transmission line instead of the output terminal OT of the (p-1) th stage. A start pulse is supplied to the start transmission line.

The second switching device Tr2 provided in the p-th stage is turned on or off according to a semi-iso clock pulse, and transmits the set node Q and the first discharge voltage VSS1 when turned on Connect the first discharge power lines to each other.

The pull-up switching element Pu provided in the p-th stage is turned on or off according to the voltage applied to the set node Q. When the turn-on state of one of the output clock lines and the output terminal OT) to each other. The output clock line CLKc is supplied to the output clock line connected to the pull-up switching element Pu. When CLKc is the first output clock pulse CLK1, i-CLKa and i-CLKb are output for the first output control Clock pulse (i-CLK1) and the fourth output control clock pulse (i-CLK4).

The high section of the output control clock pulse supplied to the first switching element Tr1 and the high section of the output control clock pulse supplied to the second switching element Tr2 may or may not overlap with each other.

a high section of the output clock pulse (i-CLKa) supplied to the p-q-th stage and a high section of the output clock pulse (i-CLKa) supplied to the p-th stage may partially overlap.

The configuration of the stage according to the second embodiment will be described with reference to FIG.

As shown in FIG. 8, the p-th stage includes first through fourth switching elements Tr1 through Tr4, a pull-up switching element Pu, and a pull-down switching element Pd.

The first switching device Tr1 provided in the p-th stage is turned on or off according to a small clock pulse, and the output terminal OT of the (p-1) -th stage and the set node Q Connect each other. When this p-th stage is the first stage to receive the start pulse, this first switching element Tr1 is connected to the start transmission line instead of the output terminal OT of the (p-1) -th stage. A start pulse is supplied to the start transmission line.

The second switching device Tr2 provided in the p-th stage is turned on or off according to a semi-iso clock pulse, and transmits the set node Q and the first discharge voltage VSS1 when turned on Connect the first discharge power lines to each other.

The third switching device Tr3 provided in the p-th stage is turned on or off according to the clock pulse for output from any one of the output clock lines, and is turned on for charging for transmitting the turn-on charging voltage VDD Connect the power supply line and the reset node (QB) to each other.

The fourth switching device Tr4 provided in the p-th stage is turned on or off according to the voltage applied to the set node Q, and the turn-on reset node QB and the second discharge voltage VSS2 are connected to each other.

The pull-up switching element Pu provided in the p-th stage is turned on or off according to the voltage applied to the set node Q. When the turn-on state of one of the output clock lines and the output terminal OT) to each other. The output clock line CLKc is supplied to the output clock line connected to the pull-up switching element Pu. When CLKc is the first output clock pulse CLK1, i-CLKa and i-CLKb are output for the first output control Clock pulse (i-CLK1) and the fourth output control clock pulse (i-CLK4).

The pull-down switching device Pd provided in the p-th stage is turned on or turned off according to the voltage applied to the reset node QB, and the output terminal OT of the p-th stage at the turn- And a third discharge power supply line for transferring the exclusive voltage VSS3 are connected to each other.

Hereupon, the pull-up switching element Pu and the third switching element Tr3 receive the same output clock pulse. The voltage of the low period of each of the output control clock pulses is equal to or smaller than the first discharge voltage VSS1.

The first discharge specific voltage VSS1 is equal to or different from the second discharge specific voltage VSS2. At this time, the first discharge voltage VSS1 is smaller than or greater than the second discharge voltage VSS2.

Or the first to third discharge voltages VSS1 to VSS3 may be the same or any two of the first to third discharge voltages VSS1 to VSS3 may be the same.

The first discharge specific voltage VSS1 is equal to or different from the second discharge specific voltage VSS2. At this time, the first discharge voltage VSS1 is smaller than or greater than the second discharge voltage VSS2.

Here, the rising edge of the output clock pulse supplied to the pull-up switching element Pu may be located within the high period of the output control clock pulse supplied to the first switching element Tr1.

The configuration of the stage according to the third embodiment will be described with reference to FIG.

As shown in FIG. 9, the p-th stage includes first through eighth switching elements Tr1 through Tr8, a pull-up switching element Pu, and a pull-down switching element Pd.

The first switching device Tr1 provided in the p-th stage is turned on or off according to a small clock pulse, and the output terminal OT of the (p-1) -th stage and the set node Q Connect each other. When this p-th stage is the first stage to receive the start pulse, this first switching element Tr1 is connected to the start transmission line instead of the output terminal OT of the (p-1) -th stage. A start pulse is supplied to the start transmission line.

The second switching device Tr2 provided in the p-th stage is turned on or off according to a semi-iso clock pulse, and transmits the set node Q and the first discharge voltage VSS1 when turned on Connect the first discharge power lines to each other.

The third switching device Tr3 provided in the p-th stage is turned on or off according to a clock pulse for output from any one of the output clock lines, and the power supply line for charge and the reset node QB for turn- . Here, the third switching device Tr3 may be supplied with the charging voltage VDD or another output clock pulse (output clock pulse other than CLKc) in place of the output clock pulse.

The fourth switching device Tr4 provided in the p-th stage is turned on or off according to the voltage applied to the set node Q, and the turn-on reset node QB and the second discharge voltage VSS2 are connected to each other.

The fifth switching device Tr5 provided in the p-th stage is turned on or off according to a scan pulse from the (p + 2) -th stage, and the set-on node Q and the first power- Connect each other. Here, the fifth switching device Tr5 may receive a scan pulse from the (p + 3) -th stage instead of the (p + 2) -th stage.

The sixth switching element Tr6 provided in the p-th stage is turned on or off according to the voltage applied to the output terminal OT of the p-th stage, and the turn-on reset node QB and the second Connect the dedicated power lines to each other.

The seventh switching device Tr7 provided in the pth stage is turned on or off according to the scan pulse from the (p + 2) -th stage, and the output terminal OT of the pth stage at the turn- Connect the dedicated power lines to each other. Here, the seventh switching device Tr7 may receive scan pulses from the (p + 3) th stage instead of the (p + 2) th stage.

The eighth switching device Tr8 provided in the p-th stage is turned on or off according to a scan pulse from the (p-1) -th stage, and the charge power supply line and the set node Q are turned on do. Here, when the p-th stage is the first stage to receive the start pulse, the eighth switch Tr8 is supplied with the start pulse from the start transmission line instead of the (p-1) th stage.

The pull-up switching element Pu provided in the p-th stage is turned on or off according to the voltage applied to the set node Q. When the turn-on state of one of the output clock lines and the output terminal OT) to each other. The output clock line CLKc is supplied to the output clock line connected to the pull-up switching element Pu. When CLKc is the first output clock pulse CLK1, i-CLKa and i-CLKb are output for the first output control Clock pulse (i-CLK1) and the fourth output control clock pulse (i-CLK4).

The pull-down switching device Pd provided in the p-th stage is turned on or turned off according to the voltage applied to the reset node QB, and the output terminal OT of the p-th stage at the turn- And a third discharge power supply line for transferring the exclusive voltage VSS3 are connected to each other.

Here, the first to third discharging voltage VSS3 and the charging voltage VDD are both DC voltages, and the first to third discharging voltages VSS3 are set to be smaller than the charging voltage VDD. For example, the charging voltage VDD may have a positive value, and the discharging voltage may have a negative value.

The first to third discharge voltages VSS1 to VSS3 may all have the same voltage value, or at least two of them may have different values. At this time, the first discharge voltage VSS1 of the first to third discharge voltages VSS1 to VSS3 may be the greatest or smallest, or the first to third discharge voltages VSS1 to VSS3, The two-discharge-specific voltage VSS2 may be the largest or the smallest, or the third discharge-specific voltage VSS3 of the first to third discharge voltages VSS1 to VSS3 may be the largest or the smallest. The first discharge voltage VSS1 of the first to third discharge voltages VSS1 to VSS3 is set to be the largest and the third discharge voltage VSS3 is set to be the smallest, (VSS2) may be set to have a value between the first discharge voltage (VSS1) and the third discharge voltage (VSS3). Also, the second discharge voltage VSS2 of the first to third discharge voltages VSS1 to VSS3 is set to be the largest, the third discharge voltage VSS3 is set to be the smallest, The voltage VSS1 may be set to have a value between the second discharge voltage VSS2 and the third discharge voltage VSS3. Also, the third discharge voltage VSS3 of the first to third discharge voltages VSS1 to VSS3 is set to be the largest, the first discharge voltage VSS1 is set to be the smallest, (VSS2) may be set to have a value between the third discharge voltage (VSS3) and the first discharge voltage (VSS1). The first discharge voltage VSS1 and the third discharge voltage VSS3 are set to the same value and the second discharge voltage VSS2 is set to be less than or equal to the third discharge voltage VSS3 .

Here, the rising edge of the output clock pulse supplied to the pull-up switching element Pu may be located within the high period of the output control clock pulse supplied to the first switching element Tr1.

On the other hand, in the third embodiment, the first discharge voltage VSS1 may be replaced with an output clock pulse. At this time, the output clock pulse to replace the first discharge voltage VSS1 is the same clock pulse as the output clock pulse supplied to the pull-up switching element Pu.

In this third embodiment, the voltage (high voltage) in the high period of each of the output control clock pulses i-CLK1 to i-CLK4 is the voltage of the high period of each of the output clock pulses CLK1 to CLK4 ).

Also, the first and second discharge voltages VSS1 and VSS2 may be less than or equal to the voltage of the low period of the output control clock pulse, respectively.

On the other hand, in the structure of the third embodiment, at least one of the fifth to eighth switching elements Tr5 to Tr8 may be removed.

The configuration of the stage according to the fourth embodiment will be described with reference to FIG.

10, the p-th stage includes first through sixth switching elements Tr1 through Tr6, a pull-up switching element Pu, and a pull-down switching element Pd.

The first switching device Tr1 provided in the p-th stage is turned on or off according to a small clock pulse, and the output terminal OT of the (p-1) -th stage and the set node Q Connect each other. When this p-th stage is the first stage to receive the start pulse, this first switching element Tr1 is connected to the start transmission line instead of the output terminal OT of the (p-1) -th stage. A start pulse is supplied to the start transmission line.

The second switching device Tr2 provided in the p-th stage is turned on or off according to the half-iso clock pulse, and is turned on when the turn-on set node Q and the first discharging voltage VSS1 Connect one dedicated power line to each other.

The third switching device Tr3 provided in the p-th stage is turned on or off according to the clock pulse for output from any one of the output clock lines, and is turned on for charging for transmitting the turn-on charging voltage VDD Connect the power supply line and the common node (CN) to each other.

The fourth switching device Tr4 provided in the p-th stage is turned on or off according to the voltage applied to the set node Q. The fourth node Tr4 is turned on or off according to the voltage applied to the set node Q, To the second power supply line.

The fifth switching device Tr5 provided in the p-th stage is turned on or off according to the voltage applied to the common node CN, and the power source line for charge and the reset node QB are turned on Connect.

The sixth switching element Tr6 provided in the p-th stage is turned on or off according to the voltage applied to the set node Q, and the turn-on reset node QB and the second discharge power supply line .

The pull-up switching element Pu provided in the p-th stage is turned on or off according to the voltage applied to the set node Q. When the turn-on state of one of the output clock lines and the output terminal OT) to each other. The output clock line CLKc is supplied to the output clock line connected to the pull-up switching element Pu. When CLKc is the first output clock pulse CLK1, i-CLKa and i-CLKb are output for the first output control Clock pulse (i-CLK1) and the fourth output control clock pulse (i-CLK4).

The pull-down switching device Pd provided in the p-th stage is turned on or turned off according to the voltage applied to the reset node QB, and the output terminal OT of the p-th stage at the turn- And a third discharge power supply line for transferring the exclusive voltage VSS3 are connected to each other.

Here, the first to third discharging voltages VSS3 in the fourth embodiment may have the same characteristics as the first to third discharging voltages VSS3 in the third embodiment described above.

Here, the rising edge of the output clock pulse supplied to the pull-up switching element Pu may be located within the high period of the output control clock pulse supplied to the first switching element Tr1.

The configuration of the stage according to the fifth embodiment will be described with reference to FIG.

As shown in FIG. 11, the p-th stage includes first through sixth switching elements Tr1 through Tr6, a pull-up switching element Pu, and a pull-down switching element Pd.

The stage according to the fifth embodiment is almost the same as the fourth embodiment described above except that the second discharging voltage VSS2 and the third discharging voltage VSS3 are the same. That is, according to FIG. 11, the first and second discharge voltages VSS2 are applied.

The first and second discharge voltages VSS2 may have the same characteristics as the first and second discharge voltages VSS2 of the second embodiment described above. Alternatively, the first and second discharge voltages VSS2 may have the same characteristics as the first and second discharge voltages VSS2 of the third embodiment described above.

The configuration of the stage according to the sixth embodiment will be described with reference to FIG.

12, the p-th stage includes first through fourth switching devices Tr4, Pu, Pd, and a capacitor C, respectively.

The first switching device Tr1 provided in the p-th stage is turned on or off according to a small clock pulse, and the output terminal OT of the (p-1) -th stage and the set node Q Connect each other. When this p-th stage is the first stage to receive the start pulse, this first switching element Tr1 is connected to the start transmission line instead of the output terminal OT of the (p-1) -th stage. A start pulse is supplied to the start transmission line.

The second switching device Tr2 provided in the p-th stage is turned on or off according to the half-iso clock pulse, and is turned on when the turn-on set node Q and the first discharging voltage VSS1 Connect one dedicated power line to each other.

The third switching device Tr3 provided in the p-th stage is turned on or off according to a scan pulse from the (p-1) -th stage, and the set node Q and the charging voltage VDD are turned on Connect the charging power supply lines to each other.

The fourth switching device Tr4 provided in the p-th stage is turned on or off according to the voltage applied to the set node Q, and the turn-on reset node QB and the second discharge voltage VSS2 are connected to each other.

The pull-up switching element Pu provided in the p-th stage is turned on or off according to the voltage applied to the set node Q. When the turn-on state of one of the output clock lines and the output terminal OT) to each other. The output clock line CLKc is supplied to the output clock line connected to the pull-up switching element Pu. When CLKc is the first output clock pulse CLK1, i-CLKa and i-CLKb are output for the first output control Clock pulse (i-CLK1) and the fourth output control clock pulse (i-CLK4).

The pull-down switching device Pd provided in the p-th stage is turned on or turned off according to the voltage applied to the reset node QB, and the output terminal OT of the p-th stage at the turn- And a third discharge power supply line for transferring the exclusive voltage VSS3 are connected to each other.

The capacitor C is connected between the output clock transmission line connected to the pull-up switching element Pu and the reset node QB.

Here, the first to third discharge voltages VSS1 to VSS3 in the sixth embodiment may have the same characteristics as the first to third discharge voltages VSS1 to VSS3 in the third embodiment described above.

On the other hand, in the sixth embodiment, the first discharge voltage VSS1 may be replaced with an output clock pulse. At this time, the output clock pulse to replace the first discharge voltage VSS1 is the same clock pulse as the output clock pulse supplied to the pull-up switching element Pu.

In this sixth embodiment, the voltage of the high period of each of the output control clock pulses is set to be smaller than or equal to the voltage of the high period of each of the output clock pulses.

Also, the third discharge voltage VSS3 may be less than or equal to the voltage of the low period of the output control clock pulse, respectively.

Here, the rising edge of the output clock pulse supplied to the pull-up switching element Pu may be located within the high period of the output control clock pulse supplied to the first switching element Tr1.

The configuration of the stage according to the seventh embodiment will be described with reference to FIG.

As shown in FIG. 13, the p-th stage includes first through fifth switching elements Tr5, a pull-up switching element Pu, and a pull-down switching element Pd.

The first switching device Tr1 provided in the p-th stage is turned on or off according to a small clock pulse, and the output terminal OT of the (p-1) -th stage and the set node Q Connect each other. When this p-th stage is the first stage to receive the start pulse, this first switching element Tr1 is connected to the start transmission line instead of the output terminal OT of the (p-1) -th stage. A start pulse is supplied to the start transmission line.

The second switching device Tr2 provided in the p-th stage is turned on or off according to the half-iso clock pulse, and is turned on when the turn-on set node Q and the first discharging voltage VSS1 Connect one dedicated power line to each other.

The third switching device Tr3 provided in the p-th stage is turned on or off according to a scan pulse from the (p-1) -th stage, and the set node Q and the charging voltage VDD are turned on Connect the charging power supply lines to each other.

The fourth switching device Tr4 provided in the p-th stage is turned on or off according to an output clock pulse from any one of the output clock lines, and is turned on for charging Connect the power supply line and the reset node (QB) to each other.

The fifth switching device Tr5 provided in the p-th stage is turned on or off according to the voltage applied to the set node Q, and the turn-on reset node QB and the second discharge voltage VSS2 are connected to each other.

The pull-up switching element Pu provided in the p-th stage is turned on or off according to the voltage applied to the set node Q. When the turn-on state of one of the output clock lines and the output terminal OT) to each other. The output clock line CLKc is supplied to the output clock line connected to the pull-up switching element Pu. When CLKc is the first output clock pulse CLK1, i-CLKa and i-CLKb are output for the first output control Clock pulse (i-CLK1) and the fourth output control clock pulse (i-CLK4).

The pull-down switching device Pd provided in the p-th stage is turned on or off according to the voltage applied to the reset node QB, and the output terminal OT of the p-th stage in the turn- Connect the dedicated power lines to each other. This pull-down switching element Pd may be connected to the above-mentioned third discharging power line instead of the second discharging power line. At this time, the first to third discharge voltages VSS1 to VSS3 may have the same characteristics as the first to third discharge voltages VSS1 to VSS2 of the third embodiment described above.

Here, the fourth switching element Tr4 and the pull-up switching element Pu are supplied with the same output clock pulse.

The first and second discharge voltages VSS2 may have the same characteristics as the first and second discharge voltages VSS2 of the second embodiment described above. Alternatively, the first and second discharge voltages VSS2 may have the same characteristics as the first and second discharge voltages VSS1 and VSS2 of the third embodiment described above.

Here, the rising edge of the output clock pulse supplied to the pull-up switching element Pu may be located within the high period of the output control clock pulse supplied to the first switching element Tr1.

The configuration of the stage according to the eighth embodiment will be described with reference to Fig.

As shown in FIG. 14, the p-th stage includes first through fifth switching elements Tr1 through Tr5, a pull-up switching element Pu, and a pull-down switching element Pd.

The first switching device Tr1 provided in the p-th stage is turned on or off according to a small clock pulse, and the output terminal OT of the (p-1) -th stage and the set node Q Connect each other. When this p-th stage is the first stage to receive the start pulse, this first switching element Tr1 is connected to the start transmission line instead of the output terminal OT of the (p-1) -th stage. A start pulse is supplied to the start transmission line.

The second switching device Tr2 provided in the p-th stage is turned on or off according to the half-iso clock pulse, and is turned on when the turn-on set node Q and the first discharging voltage VSS1 Connect one dedicated power line to each other.

The third switching device Tr3 provided in the p-th stage is turned on or off according to the voltage applied to the output terminal OT of the p-th stage, and the turn-on reset node QB and the second And the second discharge power supply line for transferring the discharge voltage VSS2 are connected to each other.

The fourth switching device Tr4 provided in the p-th stage is turned on or off according to an output clock pulse from any one of the output clock lines, and is turned on for charging Connect the power supply line and the reset node (QB) to each other.

The fifth switching device Tr5 provided in the p-th stage is turned on or off according to the voltage applied to the set node Q. When the reset node QB and the second discharging power source Connect the lines together.

The pull-up switching element Pu provided in the p-th stage is turned on or off according to the voltage applied to the set node Q. When the turn-on state of one of the output clock lines and the output terminal OT) to each other. The output clock line CLKc is supplied to the output clock line connected to the pull-up switching element Pu. When CLKc is the first output clock pulse CLK1, i-CLKa and i-CLKb are output for the first output control Clock pulse (i-CLK1) and the fourth output control clock pulse (i-CLK4).

The pull-down switching device Pd provided in the p-th stage is turned on or off according to the voltage applied to the reset node QB, and the output terminal OT of the p-th stage in the turn- Connect the dedicated power lines to each other. This pull-down switching element Pd may be connected to the above-mentioned third discharging power line instead of the second discharging power line. At this time, the first to third discharge voltages VSS1 to VSS3 may have the same characteristics as the first to third discharge voltages VSS1 to VSS2 of the third embodiment described above. Here, the fourth switching element Tr4 and the pull-up switching element Pu are supplied with the same output clock pulse.

The first and second discharge voltages VSS1 and VSS2 may have the same characteristics as the first and second discharge voltages VSS1 and VSS2 of the second embodiment described above. Alternatively, the first and second discharge voltages VSS1 and VSS2 may have the same characteristics as the first and second discharge voltages VSS1 and VSS2 of the third embodiment described above.

Here, the rising edge of the output clock pulse supplied to the pull-up switching element Pu may be located within the high period of the output control clock pulse supplied to the first switching element Tr1.

The configuration of the stage according to the ninth embodiment will be described with reference to FIG.

As shown in FIG. 15, the p-th stage includes first through fourth switching elements Tr1 through Tr4, a pull-up switching element Pu, and a pull-down switching element Pd.

The first switching device Tr1 provided in the p-th stage is turned on or off according to a small clock pulse, and the output terminal OT of the (p-1) -th stage and the set node Q Connect each other. When this p-th stage is the first stage to receive the start pulse, this first switching element Tr1 is connected to the start transmission line instead of the output terminal OT of the (p-1) -th stage. A start pulse is supplied to the start transmission line.

The second switching device Tr2 provided in the p-th stage is turned on or off according to the half-iso clock pulse, and is turned on when the turn-on set node Q and the first discharging voltage VSS1 Connect one dedicated power line to each other.

The third switching device Tr3 provided in the p-th stage is turned on in accordance with the charging voltage VDD from the charging power supply line to connect the charging power supply line and the reset node QB to each other.

The fourth switching device Tr4 provided in the p-th stage is turned on or off according to a clock pulse for output from any of the output clock transmission lines, and the turn-on reset node QB and the second And a second discharging power supply line for transmitting the exclusive voltage VSS2 are connected to each other.

The pull-up switching element Pu provided in the p-th stage is turned on or off according to the voltage applied to the set node Q. When the turn-on state of one of the output clock lines and the output terminal OT) to each other. The output clock line CLKc is supplied to the output clock line connected to the pull-up switching element Pu. When CLKc is the first output clock pulse CLK1, i-CLKa and i-CLKb are output for the first output control Clock pulse (i-CLK1) and the fourth output control clock pulse (i-CLK4).

The pull-down switching device Pd provided in the p-th stage is turned on or turned off according to the voltage applied to the reset node QB, and the output terminal OT of the p-th stage at the turn- And a third discharge power supply line for transferring the exclusive voltage VSS3 are connected to each other.

Here, the fourth switching element Tr4 and the pull-up switching element Pu are supplied with the same output clock pulse.

The first to third discharge voltages VSS1 to VSS3 may have the same characteristics as the first to third discharge voltages VSS1 to VSS3 of the third embodiment described above.

Here, the rising edge of the output clock pulse supplied to the pull-up switching element Pu may be located within the high period of the output control clock pulse supplied to the first switching element Tr1.

The configuration of the stage according to the tenth embodiment will be described with reference to Fig.

As shown in FIG. 16, the p-th stage includes first through sixth switching elements Tr1 through Tr6, a pull-up switching element Pu, and a pull-down switching element Pd.

The first switching device Tr1 provided in the p-th stage is turned on or off according to a small clock pulse, and the output terminal OT of the (p-1) -th stage and the set node Q Connect each other. When this p-th stage is the first stage to receive the start pulse, this first switching element Tr1 is connected to the start transmission line instead of the output terminal OT of the (p-1) -th stage. A start pulse is supplied to the start transmission line.

The second switching device Tr2 provided in the p-th stage is turned on or off according to the half-iso clock pulse, and is turned on when the turn-on set node Q and the first discharging voltage VSS1 Connect one dedicated power line to each other.

The third switching device Tr3 provided in the p-th stage is turned on or off according to the clock pulse for output from any one of the output clock lines, and is turned on for charging for transmitting the turn-on charging voltage VDD Connect the power supply line and the common node (CN) to each other.

The fourth switching device Tr4 provided in the p-th stage is turned on or off according to the voltage applied to the set node Q. The fourth node Tr4 is turned on or off according to the voltage applied to the set node Q, To the second power supply line.

The fifth switching device Tr5 provided in the p-th stage is turned on or off according to the voltage applied to the common node CN, and the power source line for charge and the reset node QB are turned on Connect.

The sixth switching element Tr6 provided in the p-th stage is turned on or off according to the voltage applied to the set node Q, and the turn-on reset node QB and the second discharge power supply line .

The pull-up switching element Pu provided in the p-th stage is turned on or off according to the voltage applied to the set node Q. When the turn-on state of one of the output clock lines and the output terminal OT) to each other. The output clock line CLKc is supplied to the output clock line connected to the pull-up switching element Pu. When CLKc is the first output clock pulse CLK1, i-CLKa and i-CLKb are output for the first output control Clock pulse (i-CLK1) and the fourth output control clock pulse (i-CLK4).

The pull-down switching device Pd provided in the p-th stage is turned on or off according to the voltage applied to the reset node QB, and the output terminal OT of the p-th stage in the turn- Connect the dedicated power lines to each other.

The first and second discharge voltages VSS1 and VSS2 may have the same characteristics as the first and second discharge voltages VSS1 and VSS2 of the second embodiment described above. Alternatively, the first and second discharge voltages VSS1 and VSS2 may have the same characteristics as the first and second discharge voltages VSS1 and VSS2 of the third embodiment described above.

Here, the rising edge of the output clock pulse supplied to the pull-up switching element Pu may be located within the high period of the output control clock pulse supplied to the first switching element Tr1.

The configuration of the stage according to the eleventh embodiment will be described with reference to FIG.

As shown in FIG. 17, the p-th stage includes first through fifth switching elements Tr1 through Tr5, a pull-up switching element Pu, and a pull-down switching element Pd.

The first switching device Tr1 provided in the p-th stage is turned on or off according to a small clock pulse, and the output terminal OT of the (p-1) -th stage and the set node Q Connect each other. When this p-th stage is the first stage to receive the start pulse, this first switching element Tr1 is connected to the start transmission line instead of the output terminal OT of the (p-1) -th stage. A start pulse is supplied to the start transmission line.

The second switching device Tr2 provided in the p-th stage is turned on or off according to the half-iso clock pulse, and is turned on when the turn-on set node Q and the first discharging voltage VSS1 Connect one dedicated power line to each other.

The third switching device Tr3 provided in the p-th stage is turned on in accordance with the charging voltage VDD from the charging power supply line to connect the charging power supply line and the reset node QB to each other.

The fourth switching device Tr4 provided in the p-th stage is turned on or off according to a clock pulse for output from any of the output clock transmission lines, and the turn-on reset node QB and the second And a second discharging power supply line for transmitting the exclusive voltage VSS2 are connected to each other.

The fifth switching device Tr5 provided in the p-th stage is turned on or off according to the voltage applied to the set node Q. When the reset node QB and the second discharging voltage And a second power supply line for transmitting power VSS3 are connected to each other.

The pull-up switching element Pu provided in the p-th stage is turned on or off according to the voltage applied to the set node Q. When the turn-on state of one of the output clock lines and the output terminal OT) to each other. The output clock line CLKc is supplied to the output clock line connected to the pull-up switching element Pu. When CLKc is the first output clock pulse CLK1, i-CLKa and i-CLKb are output for the first output control Clock pulse (i-CLK1) and the fourth output control clock pulse (i-CLK4).

The pull-down switching device Pd provided in the p-th stage is turned on or off according to the voltage applied to the reset node QB, and the output terminal OT of the p-th stage in the turn- Connect the dedicated power lines to each other.

The first to third discharge voltages VSS1 to VSS3 may have the same characteristics as the first to third discharge voltages VSS1 to VSS3 of the third embodiment described above.

Here, the rising edge of the output clock pulse supplied to the pull-up switching element Pu may be located within the high period of the output control clock pulse supplied to the first switching element Tr1.

Here, the operation of the stage of FIG. 9 according to the first to fourth output-use clock pulses CLK1 to CLK4 and the first to fourth output control clock pulses i-CLK1 to i-CLK4 will be described as follows .

Assume that the stage of FIG. 9 is the fifth stage. CLKa is the first clock pulse for i-CLK1, I-CLKb is the fourth output control clock pulse i-CLK4, CLKc is the first clock pulse, SP (p-1) It is a scan pulse from the fourth stage, and SP (p + 1) is a scan pulse from the sixth stage. It is assumed that the first to third discharge voltages VSS3 have the same value.

First, when the first output control clock pulse (i-CLK1) maintains the high voltage, the first and eighth switching elements Tr1 and Tr8 are turned on. Then, a scan pulse from the fourth stage is supplied to the set node Q through the turned-on first switching element Tr1, and the charging voltage VDD is supplied to the set node Q through the eighth switching element Tr8 turned on. And is supplied to the set node (Q). Therefore, the set node Q is charged, and the pull-up switching element Pu and the fourth switching element Tr4 connected to the charged set node Q through the gate electrode are turned on. Then, the second discharging power source is supplied to the reset node QB through the turned-on fourth switching device Tr4 to discharge the reset node QB, thereby discharging the discharged reset node QB. Down switching element Pd connected through the gate electrode is turned off.

Then, when the first output clock pulse CLK1 maintains a high voltage, the first output clock pulse CLK1 is output as a scan pulse through the turn-on pull-up switching element Pu. The scan pulse is applied to the fifth gate line through the output terminal OT, the fourth stage (the fifth and seventh switching elements Tr5 and Tr7 of the fourth stage) and the sixth stage (the first and second stages of the sixth stage, 8 switching elements Tr1 and Tr8). In other words, a high-voltage scan pulse is supplied to the output terminal OT. The sixth switching element Tr6 connected to the output terminal OT through the gate electrode is turned on and the second discharging voltage VSS2 is turned on via the sixth switching element Tr6 turned on. And is supplied to the reset node QB.

On the other hand, the third switching element Tr3 is turned on by the first output clock pulse CLK1, and the charging voltage VDD is supplied to the reset node (Tr3) through the turned- QB. Since the reset node QB is supplied with the second discharge voltage VSS2 by the fourth and sixth switching elements Tr6, the discharge node QB is maintained in the discharge state regardless of the charging voltage VDD.

Next, a scan pulse from the sixth stage is supplied to the gate electrode of the fifth switching device Tr5 and the gate electrode of the seventh switching device Tr7. Thus, the fifth and seventh switching elements Tr5 and Tr7 are turned on. Then, the first discharging voltage VSS1 is supplied to the set node Q through the fifth switching element Tr5 turned on to discharge the set node Q. As a result, the set node Q is discharged and the pull-up switching element Pu and the fourth switching element Tr4 connected to the set node Q through the gate electrode are turned off. On the other hand, the third discharge voltage VSS3 is supplied to the output terminal OT through the turned-on seventh switching device Tr7. As a result, the output terminal OT is discharged, and the sixth switching element Tr6 connected to the discharged output terminal OT through the gate electrode is turned off.

On the other hand, as the fourth and sixth switching elements Tr4 and Tr6 are turned off, the reset node QB is turned on by the charging voltage VDD supplied by the turned-on third switching element Tr3 Is charged. That is, the scan pulse from the sixth stage is generated by the second output clock pulse CLK2. The scan pulse from the sixth stage is generated by the first output clock pulse CLK2 and the first output clock pulse CLK1, The third switching element Tr3 is turned on during the period corresponding to the reset node QB, and the reset node QB is charged. Then, the pull-down switching element Pd connected to the charged reset node QB via the gate electrode is turned on. Then, the third discharge voltage VSS3 is supplied to the output terminal OT through the turn-on pull-down switching element Pd.

Thereafter, when the fourth output control clock pulse (i-CLK4) is maintained at a high voltage, the second switching device Tr2 is turned on, and the first discharging voltage (VSS1) is supplied to the set node (Q). Then, the set node Q is discharged.

According to the present invention, since the low voltage of the output control clock pulse is set to be smaller than the low voltage (corresponding to the low voltage of the scan pulse) of the output clock pulse and smaller than the first to third discharge voltage VSS3, The leakage current through the first and second switching elements Tr1 and Tr2 can be minimized while the clock pulse for output control is maintained at the low voltage.

The operation of the stage of FIG. 10 according to the first to fourth output clock pulses CLK1 to CLK4 and the first to fourth output control clock pulses i-CLK1 to i-CLK4 of FIG. 4 will be described below. same.

Assume that the stage of FIG. 10 is the fifth stage. CLKa is the first clock pulse for i-CLK1, I-CLKb is the fourth output control clock pulse i-CLK4, CLKc is the first clock pulse, SP (p-1) It can be seen that the scan pulse is from the fourth stage. It is assumed that the first to third discharge voltages VSS3 have the same value.

First, when the first output control clock pulse (i-CLK1) maintains the high voltage, the first switching element Tr1 is turned on. Then, the scan pulse from the fourth stage is supplied to the set node Q through the turned-on first switching element Tr1. The pull-up switching element Pu, the fourth switching element Tr4 and the sixth switching element Tr6, which are connected to the set node Q through the gate electrode, Is turned on. Then, the second discharge voltage VSS2 is supplied to the common node CN through the turned-on fourth switching element Tr4, and the common node CN is discharged. Therefore, the fifth switching element Tr5 connected to the common node CN through the gate electrode is turned off. On the other hand, the second discharging power source is supplied to the reset node QB through the sixth switching element Tr6 turned on to discharge the reset node QB, Down switching element Pd connected through the gate electrode is turned off.

Then, when the first output clock pulse CLK1 maintains a high voltage, the first output clock pulse CLK1 is output as a scan pulse through the turn-on pull-up switching element Pu. This scan pulse is supplied to the fifth gate line and the sixth stage (the first switching element Tr1 of the sixth stage) through the output terminal OT. The third switching element Tr3 is turned on by the first output clock pulse CLK1 and the charging voltage VDD is supplied to the common node CN via the third switching element Tr3 turned on. . Since the common node CN is supplied with the second discharge voltage VSS2 by the fourth switching device Tr4, the common node CN is maintained in the discharge state regardless of the charging voltage VDD.

Then, when the fourth output control clock pulse (i-CLK4) is maintained at the high voltage, the second switching element Tr2 is turned on and the first discharging voltage Tr2 is turned on via the second switching element Tr2 turned on. (VSS1) is supplied to the set node (Q). Then, the pull-up switching element Pu, the fourth switching element Tr4 and the sixth switching element Tr6, which are connected to the set node Q through the gate electrode, are discharged, do.

On the other hand, as the fourth switching device Tr4 is turned off, the common node CN is charged by the charging voltage VDD supplied by the turned-on third switching device Tr3. That is, the scan pulse from the sixth stage is generated by the second output clock pulse CLK2. The scan pulse from the sixth stage is generated by the first output clock pulse CLK2 and the first output clock pulse CLK1, The third switching element Tr3 is turned on and the common node CN is charged. Therefore, the fifth switching element Tr5 connected to the common node CN through the gate electrode is turned on, and the charging voltage VDD is supplied to the reset node N5 through the fifth switching element Tr5, (QB). Then, the reset node QB is charged, and the pull-up switching element Pu connected to the charged reset node QB via the gate electrode is turned on. The third discharge voltage VSS3 is supplied to the fifth gate line and the sixth stage (the first switching element Tr1 of the sixth stage) through the turn-on pull-up switching element Pu.

According to the present invention, since the low voltage of the output control clock pulse is set to be smaller than the low voltage (corresponding to the low voltage of the scan pulse) of the output clock pulse and smaller than the first to third discharge voltage VSS3, The leakage current through the first and second switching elements Tr1 and Tr2 can be minimized while the clock pulse for output control is maintained at the low voltage.

FIG. 18 is a diagram showing simulation waveforms for the first to fourth output clock pulses CLK1 to CLK4 and the first to fourth output control clock pulses (i-CLK4 to i-CLK4) in FIG. 18A shows the first to fourth output clock pulses CLK1 to CLK4 and FIG. 18B shows the first to fourth output control clock pulses i-CLK1 to i-CLK4.

FIG. 19 is a diagram showing simulation waveforms for positive clock pulses and semi-iso clock pulses for the first output clock pulse CLK1 in FIG. 18; FIG.

FIG. 20 is a diagram showing a simulation waveform for the voltages of the set node Q, the reset node QB, the scan pulse, and the output clock pulse generated according to the operation of the stage of FIG. As can be seen from this figure, the first switching element Tr1 is turned on during a period in which the first output control clock pulse (i-CLK1) and the scan pulse (SP (p-1) So that the set node Q is charged. At this time, since the fourth output control clock pulse (i-CLK4) is held at the low voltage, the second switching element Tr2 is turned off. Thereafter, when the first output clock pulse CLK1 transitions to a high voltage, a scan pulse is generated. Then, the set node Q is discharged when the fourth output control clock pulse (i-CLK4) becomes a high voltage.

A circuit having a negative threshold voltage is supplied with a leakage current due to the first output clock pulse CLK1 while the set node Q is kept at a low voltage and therefore the voltage rise of the set node Q . According to the present invention, the noise charge generated by the first output clock pulse CLK1 when the set node Q is held at the low voltage by the discharge voltage is the first output control clock pulse i-CLK1 ) Flows out through the gate line and the pull-down switching device Pd connected to the front stage during a period in which the high voltage is maintained.

FIG. 21 is a diagram showing a simulation waveform for the voltages of the set node Q, the reset node QB, the scan pulse, and the output clock pulse generated in accordance with the operation of the stage of FIG.

FIG. 22 is a diagram showing simulation waveforms for output control clock pulses and output clock pulses supplied to the stages of FIGS. 13 and 14. FIG. According to this, the voltage (high voltage) of the high section of each of the first to fourth output clock pulses CLK1 to CLK4 is 25 [V] and the voltage of the low section (low voltage) is -5 [V]. The high voltage (high voltage) of each of the first to fourth output control clock pulses i-CLK1 to i-CLK4 is 20 [V] and the voltage of the low period (low voltage) is -15 [ V].

FIG. 23 is a diagram showing a simulation waveform for the voltages of the set node Q, the reset node QB, the scan pulse, and the output clock pulse generated in accordance with the operation of the stage of FIG.

FIG. 24 is a diagram showing a simulation waveform for the voltages of the set node Q, the reset node QB, the scan pulse, and the output clock pulse generated in accordance with the operation of the stage of FIG. Specifically, FIG. 24A shows a state where the first and third discharge voltages VSS1 and VSS3 are both -5 V and the second discharge voltage VSS2 is -7 [V] FIG. 24B is a graph showing the voltage of the reset node QB, the scan pulse and the output clock pulse when the first and third discharge voltages VSS3 are both -5 V, , The reset node QB, the scan pulse, and the output clock pulse under the condition that the second discharge voltage VSS2 is -2 [V].

FIG. 25 is a diagram showing a simulation waveform for the voltages of the set node Q, the reset node QB, the scan pulse, and the output clock pulse generated in accordance with the operation of the stage of FIG.

Fig. 26 is a diagram showing a simulation waveform for the voltages of the set node Q, the reset node QB, the scan pulse, and the output clock pulse generated in accordance with the operation of the stage of Fig.

FIG. 27 is a view showing a modified structure of FIG. 8. FIG.

As shown in FIG. 27, the stage shown in FIG. 8 may not include the second switching device Tr2. 27, the p-th stage includes a first switching device Tr1, a third switching device Tr3, a fourth switching device Tr4, a pull-up switching device Pu, and a pulldown switching device Pd). In this case, the set node Q is discharged by the low voltage from the gate line connected to the front stage.

The first switching element Tr1, the third switching element Tr3, the fourth switching element Tr4, the pull-up switching element Pu and the pull-down switching element Pd shown in Fig. 1 switching element Tr1, the third switching element Tr3, the fourth switching element Tr4, the pull-up switching element Pu and the pull-down switching element Pd.

At this time, a high section of the output clock pulse (i-CLKa) supplied to the p-q-th stage and a high section of the output clock pulse (i-CLKa) supplied to the p-th stage may partially overlap.

On the other hand, the charging voltage VDD may be applied to the gate electrode of the third switching device Tr3 in FIG. 27 instead of the output clock pulse CLKc.

Here, the rising edge of the output clock pulse supplied to the pull-up switching element Pu may be located within the high period of the output control clock pulse supplied to the first switching element Tr1.

FIG. 28 is a view showing a modified structure of FIG. 27; FIG.

The third switching device Tr3 shown in FIG. 27 may have a connection structure of the type shown in FIG.

That is, as shown in FIG. 28, the third switching device Tr3 is turned on or off according to the output clock pulse from any one of the output clock lines. When the third switching device Tr3 is turned on, Nodes QB to each other. CLKc is supplied to the output clock line connected to the third switching device Tr3. When CLKc is the first output clock pulse CLK1, i-CLKa and i-CLKb are respectively output to the first output The control clock pulse i-CLK1 and the fourth output control clock pulse i-CLK4.

At this time, a high section of the output clock pulse (i-CLKa) supplied to the p-q-th stage and a high section of the output clock pulse (i-CLKa) supplied to the p-th stage may partially overlap.

Here, the rising edge of the output clock pulse supplied to the pull-up switching element Pu may be located within the high period of the output control clock pulse supplied to the first switching element Tr1.

29 is a view showing another modified structure of Fig.

The third switching device Tr3 shown in FIG. 27 may have a connection structure of the type shown in FIG.

29, the third switching device Tr3 is turned on in accordance with the charging voltage VDD from the charging power supply line, so that any one output clock line and the reset node QB Connect each other. CLKc is supplied to the output clock line connected to the third switching device Tr3. When CLKc is the first output clock pulse CLK1, i-CLKa and i-CLKb are respectively output to the first output The control clock pulse i-CLK1 and the fourth output control clock pulse i-CLK4.

On the other hand, the output clock pulse CLKc may be applied to the gate electrode of the third switching device Tr3 in FIG. 29 instead of the charging voltage VDD.

Here, the rising edge of the output clock pulse supplied to the pull-up switching element Pu may be located within the high period of the output control clock pulse supplied to the first switching element Tr1.

FIG. 30 is a view showing another modified structure of FIG. 10; FIG.

As shown in FIG. 30, the stage shown in FIG. 10 may not include the second switching device Tr2. 30, the p-th stage includes a first switching element Tr1, third to sixth switching elements Tr3 to Tr6, a pull-up switching element Pu, and a pull-down switching element Pd. . In this case, the set node Q is discharged by the low voltage from the gate line connected to the front stage. On the other hand, the drain electrode of the third switching device Tr3 in Fig. 30 can be connected to the charging power supply line instead of the output clock line.

At this time, a high section of the output clock pulse (i-CLKa) supplied to the p-q-th stage and a high section of the output clock pulse (i-CLKa) supplied to the p-th stage may partially overlap.

On the other hand, the charging voltage VDD may be applied to the gate electrode of the third switching device Tr3 in FIG. 30 instead of the output clock pulse CLKc.

Here, the rising edge of the output clock pulse supplied to the pull-up switching element Pu may be located within the high period of the output control clock pulse supplied to the first switching element Tr1.

On the other hand, in all embodiments, two identical discharge voltages may be supplied through separate discharge power lines, or may be supplied through the same discharge power line.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

CLKe: clock pulse for e-th output i-CLKf: clock pulse for f-th output

Claims (22)

A first clock generator for outputting n (n is a natural number of 2 or more) output clock pulses having different phases;
(M is a natural number) output clock pulses having different phases and having a high-level portion overlapping each other, arranging the m * n output clock pulses in phase order, grouping them into n units, And a rising edge of the output clock pulses having a kth phase sequence of each group is generated in a high period of a clock pulse for output control having a kth phase sequence among the n output control clock pulses, A second clock generator for outputting m * n output clock pulses so as to be located within the first clock generator;
And a shift register for receiving n output control clock pulses from the first clock generator and m * n output clock pulses from the second clock generator and sequentially outputting a plurality of scan pulses,
Wherein the shift register comprises a plurality of stages for sequentially outputting scan pulses;
The p-th (p is a natural number)
A first switching circuit that connects either the output terminal of the pqth (q is a natural number smaller than p) stage output terminal and the start transmission line for transmitting the start pulse and the set node in response to any one of the n output control clock pulses, device;
A second switching element for connecting the set node to a first power supply line for transmitting a first discharge voltage in response to any one of the n output control clock pulses;
And a pull-up switching element for connecting the output clock line for transmitting one of the m * n output clock pulses to the output terminal of the p-th stage in response to a voltage applied to the set node;
The high section of the output clock pulse and the high section of the output control clock pulse supplied to the second switching element do not overlap;
The voltage of the low section of each of the n output control clock pulses is less than or equal to the first discharge voltage;
A high period of the output clock pulse supplied to the pq stage and a high period of the output clock pulse supplied to the p stage are partially overlapped;
And a rising edge of an output clock pulse supplied to the pull-up switching element is located within a high period of a clock pulse for output control supplied to the first switching element. The method according to claim 1,
Each of the n output control clock pulses and the m * n output clock pulses includes a plurality of impulses periodically generated;
the rising edge of the impulse included in the output clock pulse belonging to the group j (j is a natural number equal to or smaller than m) and having the kth phase order is within the high interval of the impulse of the output controlling clock pulse having the kth phase order The gate drive circuit characterized in that the gate drive circuit comprises: 3. The method of claim 2,
the m * nth output clock pulse further comprises a dummy impulse;
Wherein the dummy impulse has the same output timing as a start pulse having a phase prior to the first output clock pulse. 3. The method of claim 2,
Wherein voltage of each row interval of the n output control clock pulses is less than or equal to voltage of each row interval of the m * n output clock pulses. 5. The method of claim 4,
Wherein each of the m * n output clock pulses does not overlap with at least any one of the n output control clock pulses. delete The method according to claim 1,
Wherein q is any one of 1 and 2. The method according to claim 1,
The p < th >
A third switching element that is turned on or off according to an output clock pulse from any one of the output clock lines and connects the charging power supply line for transmitting the charging voltage at the turn-on time and the reset node to each other;
A fourth switching device that turns on or off according to a voltage applied to the set node and connects the reset node and a second discharge power supply line that transmits a second discharge voltage when turning on; And
And a third discharge power supply line for transmitting a third discharge voltage at an output terminal of the p-th stage at the time of turn-on, wherein the third discharge power supply line is turned on or off according to a voltage applied to the reset node, Further comprising a device;
And the pull-up switching element and the third switching element are supplied with the same output clock pulse. 9. The method of claim 8,
The p < th >
a fifth switching device that turns on or off according to a scan pulse from the (p + r) th (r is a natural number) stage and connects the set node and the first discharge power supply line to each other when turned on;
A sixth switching device that is turned on or off according to a voltage applied to the output terminal of the pth stage and connects the reset node and the second discharge power supply line to each other when turned on;
A seventh switching device that turns on or off according to a scan pulse from the p + rth stage and connects the output terminal of the pth stage to the third discharge power supply line when turned on; And
further comprising at least one of an eighth switching element which turns on or off according to a scan pulse from the psth (s is a natural number) stage, and connects the charging power supply line and the set node at the time of turn-on And a gate drive circuit. 3. The method of claim 2,
Wherein the voltage of the high section of each of the m * n output clock pulses is equal to or greater than the voltage of the high section of each of the n output control clock pulses. The method according to claim 1,
In the p-th stage,
A third switching element that is turned on or off according to an output clock pulse from any one of the output clock lines and connects the charging power supply line for transmitting the charging voltage at the turn-on time and the common node to each other;
A fourth switching element that turns on or off according to a voltage applied to the set node and connects the common node and a second discharging power supply line for transmitting a second discharging voltage upon turning on;
A fifth switching element that is turned on or off according to a voltage applied to the common node and connects the charging power supply line and the reset node when turned on;
A sixth switching element that is turned on or off according to a voltage applied to the set node and connects the reset node and the second discharge power supply line to each other when the switch is turned on; And
And a third discharge power supply line for transmitting a third discharge voltage at an output terminal of the p-th stage at the time of turn-on, wherein the third discharge power supply line is turned on or off according to a voltage applied to the reset node, Further comprising a device;
Wherein the pull-up switching element and the third switching element are supplied with the same output clock pulse. The method according to claim 1,
In the p-th stage,
a third switching element that turns on or off according to a scan pulse from the pr-th stage and connects the set node with a charging power supply line for transmitting a charging voltage when turned on;
A fourth switching element that is turned on or off according to a voltage applied to the set node and connects the reset node to a second power supply line for transmitting a second discharge voltage;
And a third discharge power supply line for transmitting a third discharge voltage at an output terminal of the p-th stage at the time of turn-on, wherein the third discharge power supply line is turned on or off according to a voltage applied to the reset node, device; And
Further comprising a capacitor connected between the reset node and the output clock transmission line connected to the pull-up switching element. The method according to claim 1,
In the p-th stage,
a third switching element that turns on or off according to a scan pulse from the psth stage and connects the set node with a charging power supply line for transmitting a charging voltage when turned on;
A fourth switching element that is turned on or off according to an output clock pulse from any one of the output clock lines and connects the charging power supply line for transmitting the charging voltage at the turn-on time and the reset node to each other;
A fifth switching element that turns on or off according to a voltage applied to the set node and connects the reset node and a second discharge power supply line that transmits a second discharge voltage when turning on; And
And a third discharge power supply line for transmitting a third discharge voltage at an output terminal of the p-th stage at the time of turn-on, wherein the third discharge power supply line is turned on or off according to a voltage applied to the reset node, Further comprising a device;
Wherein the fourth switching element and the pull-up switching element are supplied with the same output clock pulse. The method according to claim 1,
In the p-th stage,
A third switching power supply line connected between the reset node and a second power supply line for transmitting a second discharge voltage, the third switching power supply line being turned on or off according to a voltage applied to the output terminal of the pth stage, device;
A fourth switching element that is turned on or off according to an output clock pulse from any one of the output clock lines and connects the charging power supply line for transmitting the charging voltage at the turn-on time and the reset node to each other;
A fifth switching element that is turned on or off according to a voltage applied to the set node and connects the reset node and the second discharge power supply line to each other when turned on; And
And a third discharge power supply line for transmitting a third discharge voltage at an output terminal of the p-th stage at the time of turn-on, wherein the third discharge power supply line is turned on or off according to a voltage applied to the reset node, Further comprising a device;
Wherein the fourth switching element and the pull-up switching element are supplied with the same output clock pulse. The method according to claim 1,
A third switching element that is turned on according to a charging voltage from the charging power supply line and connects the charging power supply line and the reset node to each other;
And a second discharging power supply line for transmitting the second discharging voltage to the reset node when the first discharging power supply line is turned on according to a clock pulse for output from any one of the output clock transmission lines, 4 switching devices; And
And a third discharge power supply line for transmitting a third discharge voltage at an output terminal of the p-th stage at the time of turn-on, wherein the third discharge power supply line is turned on or off according to a voltage applied to the reset node, Further comprising a device;
Wherein the fourth switching element and the pull-up switching element are supplied with the same output clock pulse. The method according to claim 1,
A third switching element that is turned on according to a charging voltage from the charging power supply line and connects the charging power supply line and the reset node to each other;
And a second discharging power supply line for transmitting the second discharging voltage to the reset node when the first discharging power supply line is turned on according to a clock pulse for output from any one of the output clock transmission lines, 4 switching devices;
A fifth switching element that turns on or off according to a voltage applied to the set node and connects the reset node and a second discharge power supply line that transmits a second discharge voltage when turning on; And
Further comprising a pull-down switching element for turning on or off according to a voltage applied to the reset node and for connecting the output terminal of the p-th stage and the third discharge power supply line to each other when turned on;
Wherein the fourth switching element and the second switching element receive the same output clock pulse. The method according to claim 1,
And the n high output control clock pulses do not overlap each other. The method according to any one of claims 8, 9, 11, 12, 13, 14, 15 and 16,
Wherein at least two of the first to third discharge voltages are equal to each other. 3. The method of claim 2,
Wherein the shift register comprises a plurality of stages for sequentially outputting scan pulses;
Each of the stages outputs a scan pulse through its output terminal;
The n output control clock pulses are transmitted through n output control clock lines;
The m * n output clock pulses are transmitted through m * n output clock lines;
The p-th (p is a natural number)
The output terminal of the pq-th stage (q is a natural number smaller than p) and the start transmission line for transmitting the start pulse are turned on or off according to any one of the n output control clock pulses. A first switching element for connecting one of the plurality of sets to the set node;
A pull-up switching element which is turned on or off according to a voltage applied to the set node and connects the output terminal of one of the output clock lines and the output terminal of the p-th stage when the switch is turned on;
A third switching element that is turned on or off according to an output clock pulse from any one of the output clock lines and connects the charging power supply line for transmitting the charging voltage at the turn-on time and the reset node to each other;
A fourth switching device that turns on or off according to a voltage applied to the set node and connects the reset node and a second discharge power supply line that transmits a second discharge voltage when turning on; And
And a third discharge power supply line for transmitting a third discharge voltage at an output terminal of the p-th stage at the time of turn-on, wherein the third discharge power supply line is turned on or off according to a voltage applied to the reset node, Device;
Wherein the pull-up switching element and the third switching element receive the same output clock pulse;
The voltage of the low interval of each of the n output control clock pulses is less than or equal to the second and third discharge voltages;
A high period of the output clock pulse supplied to the pq stage and a high period of the output clock pulse supplied to the p stage are partially overlapped;
And a rising edge of an output clock pulse supplied to the pull-up switching element is located within a high period of a clock pulse for output control supplied to the first switching element. 3. The method of claim 2,
Wherein the shift register comprises a plurality of stages for sequentially outputting scan pulses;
Each of the stages outputs a scan pulse through its output terminal;
The n output control clock pulses are transmitted through n output control clock lines;
The m * n output clock pulses are transmitted through m * n output clock lines;
The p-th (p is a natural number)
The output terminal of the pq-th stage (q is a natural number smaller than p) and the start transmission line for transmitting the start pulse are turned on or off according to any one of the n output control clock pulses. A first switching element for connecting one of the plurality of sets to the set node;
A pull-up switching element which is turned on or off according to a voltage applied to the set node and connects the output terminal of one of the output clock lines and the output terminal of the p-th stage when the switch is turned on;
A third switching device that turns on or off according to a clock pulse for output from any one of the output clock lines and connects the output clock line and the reset node to each other upon turning on;
A fourth switching device that turns on or off according to a voltage applied to the set node and connects the reset node and a second discharge power supply line that transmits a second discharge voltage when turning on; And
And a third discharge power supply line for transmitting a third discharge voltage at an output terminal of the p-th stage at the time of turn-on, wherein the third discharge power supply line is turned on or off according to a voltage applied to the reset node, Device;
Wherein the pull-up switching element and the third switching element receive the same output clock pulse;
The high section of the output clock pulse and the high section of the output control clock pulse supplied to the first switching element do not overlap;
The voltage of the low interval of each of the n output control clock pulses is less than or equal to the second and third discharge voltages;
A high period of the output clock pulse supplied to the pq stage and a high period of the output clock pulse supplied to the p stage are partially overlapped;
And a rising edge of an output clock pulse supplied to the pull-up switching element is located within a high period of a clock pulse for output control supplied to the first switching element. 3. The method of claim 2,
Wherein the shift register comprises a plurality of stages for sequentially outputting scan pulses;
Each of the stages outputs a scan pulse through its output terminal;
The n output control clock pulses are transmitted through n output control clock lines;
The m * n output clock pulses are transmitted through m * n output clock lines;
The p-th (p is a natural number)
The output terminal of the pq-th stage (q is a natural number smaller than p) and the start transmission line for transmitting the start pulse are turned on or off according to any one of the n output control clock pulses. A first switching element for connecting one of the plurality of sets to the set node;
A pull-up switching element which is turned on or off according to a voltage applied to the set node and connects the output terminal of one of the output clock lines and the output terminal of the p-th stage when the switch is turned on;
A third switching device that is turned on according to a charging voltage from a charging power supply line and connects one of the output clock lines and the reset node to each other;
A fourth switching device that turns on or off according to a voltage applied to the set node and connects the reset node and a second discharge power supply line that transmits a second discharge voltage when turning on; And
And a third discharge power supply line for transmitting a third discharge voltage at an output terminal of the p-th stage at the time of turn-on, wherein the third discharge power supply line is turned on or off according to a voltage applied to the reset node, Device;
Wherein the pull-up switching element and the third switching element receive the same output clock pulse;
The high section of the output clock pulse and the high section of the output control clock pulse supplied to the first switching element do not overlap;
The voltage of the low interval of each of the n output control clock pulses is less than or equal to the second and third discharge voltages;
A high period of the output clock pulse supplied to the pq stage and a high period of the output clock pulse supplied to the p stage are partially overlapped;
And a rising edge of an output clock pulse supplied to the pull-up switching element is located within a high period of a clock pulse for output control supplied to the first switching element. 3. The method of claim 2,
Wherein the shift register comprises a plurality of stages for sequentially outputting scan pulses;
Each of the stages outputs a scan pulse through its output terminal;
The n output control clock pulses are transmitted through n output control clock lines;
The m * n output clock pulses are transmitted through m * n output clock lines;
The p-th (p is a natural number)
The output terminal of the pq-th stage (q is a natural number smaller than p) and the start transmission line for transmitting the start pulse are turned on or off according to any one of the n output control clock pulses. A first switching element for connecting one of the plurality of sets to the set node;
A pull-up switching element which is turned on or off according to a voltage applied to the set node and connects the output terminal of one of the output clock lines and the output terminal of the p-th stage when the switch is turned on;
A third switching element that is turned on or off according to an output clock pulse from any one of the output clock lines and connects the charging power supply line for transmitting the charging voltage at the turn-on time and the common node to each other;
A fourth switching element that turns on or off according to a voltage applied to the set node and connects the common node and a second discharging power supply line for transmitting a second discharging voltage upon turning on;
A fifth switching element that is turned on or off according to a voltage applied to the common node and connects the charging power supply line and the reset node when turned on;
A sixth switching element that is turned on or off according to a voltage applied to the set node and connects the reset node and the second discharge power supply line to each other when the switch is turned on; And
And a third discharge power supply line for transmitting a third discharge voltage at an output terminal of the p-th stage at the time of turn-on, wherein the third discharge power supply line is turned on or off according to a voltage applied to the reset node, Device;
The high section of the output clock pulse and the high section of the output control clock pulse supplied to the first switching element do not overlap;
The voltage of the low interval of each of the n output control clock pulses is smaller than the second and third discharge voltages;
Wherein the pull-up switching element and the third switching element receive the same output clock pulse;
A high period of the output clock pulse supplied to the pq stage and a high period of the output clock pulse supplied to the p stage are partially overlapped;
And a rising edge of an output clock pulse supplied to the pull-up switching element is located within a high period of a clock pulse for output control supplied to the first switching element.

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