KR101219769B1 - Carbon nanostructured material pattern and manufacturing method of the same, and carbon nanostructured material thin film transistor and manufacturing method of the same - Google Patents

Abstract

Herein, forming a metal catalyst layer on a substrate, forming a mask layer on the metal catalyst layer, etching the metal catalyst layer and the mask layer to form a mold pattern having a metal catalyst layer exposed on the side, Growing a carbon nanostructure layer on the side of the metal catalyst layer of the template pattern, and removing a part or all of the metal catalyst layer and the mask layer of the template pattern to form a carbon nanostructure pattern, the carbon nanostructure pattern It relates to a method for producing.
In addition, the present application relates to a carbon nanostructure thin film transistor and a method for manufacturing the same, the side of the patterned metal catalyst layer on the substrate, characterized in that the leakage current is small and can be manufactured in a large size on a large substrate and mass production is possible. The present invention relates to a carbon nanostructure thin film transistor including a carbon nanostructure layer in the form of a nanoribbon formed thereon and a method of manufacturing the same.

Description

CARBON NANOSTRUCTURED MATERIAL PATTERN AND MANUFACTURING METHOD OF THE SAME, AND CARBON NANOSTRUCTURED MATERIAL THIN FILM TRANSISTOR AND MANUFACTURING METHOD OF THE SAME

The present invention relates to a carbon nanostructured material pattern and a method for manufacturing the same, and a carbon nanostructure thin film transistor and a method for manufacturing the same, and specifically, comprising selectively growing carbon nanostructure on the side of a metal catalyst layer pattern. The present invention relates to a method of manufacturing a carbon nanostructure pattern, a carbon nanostructure pattern manufactured by the method, a carbon nanostructure thin film transistor including the carbon nanostructure pattern layer, and a method of manufacturing the same.

Carbon nanostructures such as carbon nanotubes (CNT), graphene, and carbon nanofibers are used in nanoelectronics, nanoelectromechanical systems (NEMS), sensors, contact electrodes, and nanophotonics. ) And some of the most promising candidates for future growth in nanobiotechnology and the like. This is primarily due to the one-dimensional nature, unique electrical, optical and mechanical properties of the carbon nanostructures.

On the other hand, graphene (graphene) of the carbon nanostructures refers to a single layer of carbon of hexagonal structure, that is, (0001) cotton monolayer of graphite, such graphene is known to have better physical properties than carbon nanotubes. In particular, since graphene has an electrical conductivity of 50 to 100 times that of silicon, much research is being conducted as a new material that can replace a semiconductor such as silicon.

Generally, graphene is obtained by peeling from high crystalline graphite or the like using a scotch tape. In addition, mechanical methods [B. Z. Jang et al., Nano-scaled graphite plates, US 7,071,258 B1] and electrostatic methods [A. N. Sidorov et al., Electrostatic deposition of graphene, Nanotechnology 18 (2007) 135301] has been proposed to prepare the graphene. Common to these methods is the mechanical cleavage of graphene from high crystalline graphite.

In addition, Alfonso et al. Nano Lett. In the January 2009 issue, a method of using a metal catalyst as a method of growing a graphene substrate is disclosed, which is a method of growing graphene by CVD after depositing a metal catalyst. The method has the advantage of growing large graphene because of the use of CVD, but since it uses a metal catalyst, the fundamental limitation of removing the metal catalyst after deposition of graphene to attach the graphene deposited thereon to another substrate It has the disadvantage of being very difficult to use in mass production.

However, since planar graphene is a semi-metal, when the transistor is manufactured, there is a problem in that the leakage current is very large because current cannot be cut off completely.

In the related art, the graphene is patterned through lithography, and the graphene is etched (top-down) or bottom-up by O ₂ plasma. There was a method for synthesizing the graphene. However, the first traditional top-down method is known to have a limited leakage current due to the lithography limitation and the problem of damaging graphene during plasma etching. And the second bottom-up method has a fatal drawback that it is not a method that can be used for mass production.

In addition, many conventional graphene growth methods for manufacturing graphene transistors based on graphene substrates have limitations in growing graphene in large quantities, thus making it difficult to manufacture graphene transistors based on the graphene substrate. It shows technical limitations.

Therefore, there is a need for a transistor having a small leakage current, suitable for use as a transistor, capable of mass production, and manufacturing in a large size on a large substrate.

Graphene, a flat single atomic layer of carbon atoms, has a high electron mobility that can lead to ultrafast transistors or very thin and / or transparent electrodes. For use in device applications, the bandgap of graphene must be initiated because graphene is a zero-bandgap material. It is known that the bandgap of graphene ribbons increases as the width of the ribbon decreases. Graphene ribbons can be implemented through graphene synthesis, patterning, and etching of ribbons. So synthesis, patterning, and etching are all important for making graphene ribbons. There have been many reports for graphene synthesis. Among them, chemical vapor deposition (CVD) on metal catalysts is very promising thanks to high quality films and easy scale-up.

However, to implement a CVD-grown graphene ribbon, a subsequent transfer process is necessary because of the metal catalyst underneath the synthesized graphene layer. Common wet transfer methods involve separating the graphene film from the metal catalyst and transferring it to the desired substrate. Although roll-to-roll transfer techniques have recently been reported, low cost, high power transfer methods without folds and defects are still being studied. In addition to the transfer process, a subsequent O ₂ plasma etch process for patterning graphene ribbons can cause additional damage at the ribbon edges. Thus, both transfer and etching processes are obstacles that must be overcome to make good graphene ribbons from CVD-grown graphene.

Thus, in order to solve the conventional problems as described above, the present application, a method for producing a carbon nanostructure pattern comprising selectively growing a carbon nanostructure on the side of the metal catalyst layer using a metal catalyst layer pattern, It provides a carbon nanostructure pattern produced by the manufacturing method.

In addition, the present application is a carbon nanostructure thin film transistor including a carbon nanostructure layer formed along the side surface of the metal catalyst layer in the form of nanoribbons, which can be produced in a large size on a large substrate with a small leakage current, and its production. To provide a method.

However, the problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

In order to achieve the above technical problem, the first aspect of the present application provides a method of manufacturing a carbon nanostructured material pattern, comprising the following steps:

Forming a metal catalyst layer on the substrate;

Forming a mask layer on the metal catalyst layer;

Etching the metal catalyst layer and the mask layer to form a mold pattern having exposed metal catalyst layers on side surfaces thereof;

Growing a carbon nanostructure layer on the side of the metal catalyst layer of the template pattern; And

Removing a part or all of the metal catalyst layer and the mask layer of the template pattern to form a carbon nanostructure pattern.

The second aspect of the present application provides a carbon nanostructure pattern produced by the method of producing a carbon nanostructure pattern according to the present application.

A third aspect of the present application provides an electrical and electronic device including the carbon nanostructure pattern.

The fourth aspect of the present application provides a field emission device including the carbon nanostructure pattern.

A fifth aspect of the present application provides a method of manufacturing a carbon nanostructure thin film transistor, comprising the following steps:

Forming a metal catalyst layer on the substrate;

Forming a mask layer on the metal catalyst layer;

Etching the metal catalyst layer and the mask layer to form a mold pattern having the metal catalyst layer exposed on a side surface thereof;

Forming a carbon nanostructure layer on the side of the metal catalyst layer of the template pattern;

Removing a part or all of the metal catalyst layer and the mask layer of the template pattern to form a carbon nanostructure pattern layer;

Forming a gate insulating layer on the substrate;

Forming a gate electrode on the substrate; And

Forming a source / drain electrode in electrical contact with the carbon nanostructure pattern layer.

A sixth aspect of the present disclosure may provide a carbon nanostructure thin film transistor manufactured according to the manufacturing method.

The method of manufacturing the carbon nanostructure pattern of the present application includes selectively forming a carbon nanostructure layer only on the side of the metal catalyst layer, thereby eliminating the process of transferring the prepared carbon nanostructure layer or pattern to another substrate. This simplifies the manufacturing process, thereby lowering the manufacturing cost of the carbon nanostructure pattern and at the same time preventing breakage of the carbon nanostructure layer or pattern that may occur by implanting the carbon nanostructure layer or pattern onto another substrate.

In addition, according to the present application, a carbon nanostructure thin film transistor including a carbon nanostructure layer in which carbon nanostructure pattern layers of various forms such as nanoribbons are selectively grown on a side of a metal catalyst layer may be manufactured. The carbon nanostructure thin film transistor includes various types of carbon nanostructure layers such as nanoribbons, and the width of the carbon nanostructure layers of various forms such as the nanoribbons is very low, and leakage current is very low. The method of growing a nanoribbon is suitable for producing on a large substrate or in large quantities so that carbon nanostructure thin film transistors can be manufactured in large sizes or in large quantities on large substrates. In addition, since the graphene ribbon manufactured according to the present application is a fin-type vertical type, a practical dual gate graphene transistor can be easily implemented. Specifically, graphene of the carbon nanostructures is a semi-metal material. In order to manufacture such a semi-metal material into graphene having semiconductor properties, the width of the graphene must be made very narrow. The structure in which the width of the graphene is very narrow is referred to as a "nanoribbon structure", and the narrower the width of the nanoribbons, the larger the bandgap and the smaller the leakage current when the transistor is turned off.

1 is a perspective view of a carbon nanostructure pattern manufactured by a method of manufacturing a carbon nanostructure pattern according to an embodiment of the present application;
2 is a cross-sectional view taken along II-II of FIG. 1,
3 is a flowchart illustrating a method of manufacturing a carbon nanostructure pattern according to an embodiment of the present application;
4A to 4C are cross-sectional views illustrating a method of manufacturing a carbon nanostructure pattern according to an embodiment of the present application;
5 is a flowchart illustrating a method of manufacturing a carbon nanostructure thin film transistor according to an embodiment of the present disclosure,
6A through 6F are cross-sectional views illustrating a method of manufacturing a carbon nanostructure thin film transistor according to an exemplary embodiment of the present disclosure.
7 is a perspective view of a carbon nanostructure thin film transistor according to an embodiment of the present disclosure,
8A to 8E are cross-sectional views illustrating a method of manufacturing a carbon nanostructure thin film transistor according to an exemplary embodiment of the present application.
9A to 9D are perspective views illustrating a method of manufacturing a carbon nanostructure thin film transistor according to an exemplary embodiment of the present application.
10A to 10B are SEM images of carbon nanostructures according to an embodiment of the present disclosure,
10c is a Raman spectrum of a carbon nanostructure according to an embodiment of the present application,
11A is a schematic view of carbon nanostructures in accordance with an embodiment of the present disclosure,
11B is a cross-sectional SEM image of carbon nanostructures according to an embodiment of the present disclosure,
11C is a cross-sectional TEM image of carbon nanostructures according to an embodiment of the present disclosure,
11D is a cross-sectional TEM image of carbon nanostructures according to an embodiment of the present disclosure,
12A is a view showing an apparatus for measuring IV of carbon nanostructures according to an embodiment of the present disclosure,
12A and 12B are IV curves before and after Ni time of a carbon nanostructure ribbon according to one embodiment of the present application,
13A is a view showing an apparatus for measuring IV of a carbon nanostructure ribbon transistor according to an embodiment of the present application,
13B and 13C are graphs illustrating output and transmission characteristics of a back gate voltage of a carbon nanostructure ribbon transistor according to an exemplary embodiment of the present disclosure.
13D is a graph showing the mutual conductivity of carbon nanostructures according to an embodiment of the present disclosure.

DETAILED DESCRIPTION Hereinafter, embodiments and examples of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present disclosure.

It should be understood, however, that the present invention may be embodied in many different forms and is not limited to the embodiments and examples described herein. In the drawings, the same reference numbers are used throughout the specification to refer to the same or like parts.

As used throughout this specification, the terms "about", "substantially", and the like, are used at, or in the vicinity of, numerical values when a manufacturing and material tolerance inherent in the meanings indicated are given and an understanding of the invention Accurate or absolute figures are used to help prevent unfair use by unscrupulous infringers. As used throughout this specification, the terms "step (to)" or "step of (d)" do not mean "step for".

Throughout this specification, when a member is located "on" with another member, this includes not only when a member is in contact with another member, but also when there is another member between the two members. In addition, when a part is said to "include" a certain component, which means that it may further include other components, except to exclude other components unless specifically stated otherwise.

In a first aspect of the present disclosure, the method of manufacturing the carbon nanostructured material pattern may include the following steps:

Forming a metal catalyst layer on the substrate;

Forming a mask layer on the metal catalyst layer;

Etching the metal catalyst layer and the mask layer to form a mold pattern having exposed metal catalyst layers on side surfaces thereof;

Growing a carbon nanostructure layer on the side of the metal catalyst layer of the template pattern; And

Removing a part or all of the metal catalyst layer and the mask layer of the template pattern to form a carbon nanostructure pattern.

In one embodiment of the present application, the "carbon nanostructure" may include graphene, carbon nanotubes, carbon nanofibers, carbon nanowires or carbon nanocones, but is not limited thereto.

In another embodiment of the present invention, the metal catalyst layer may include a metal that can be used as a catalyst for carbon nanostructure growth, the metal is made of Cu, Fe, Ni, Co, Pt, Ir, Pd and Ru One or more metals selected from the group or alloys thereof may be included, but is not limited thereto.

In another embodiment of the present disclosure, the mask layer may include one or more selected from the group consisting of SiO ₂ , SiN _x , Al ₂ O ₃ , HfO _x , and TiN, but is not limited thereto.

In another embodiment of the present disclosure, growing the carbon nanostructures on the side of the metal catalyst layer of the template pattern may include growing the carbon nanostructure layer by decomposing a precursor including carbon by heat or plasma. Can be.

In another embodiment of the present disclosure, the method may further include forming a barrier layer between the substrate and the metal catalyst layer.

In another embodiment of the present disclosure, the barrier layer may include one or more selected from the group consisting of SiO ₂ , SiN _x , Al ₂ O _3, and HfO _x , but is not limited thereto.

The second aspect of the present application provides a carbon nanostructure pattern produced by the method of producing a carbon nanostructure pattern according to the present application.

In one embodiment of the present application, the carbon nanostructure pattern may have a nanoribbon form, but is not limited thereto.

The third aspect of the present application provides an electrical and electronic device comprising the carbon nanostructure pattern according to the present application.

The fourth aspect of the present application provides a field emission device comprising the carbon nanostructure pattern according to the present application.

Hereinafter, an embodiment according to the present disclosure will be described in more detail with reference to the accompanying drawings.

1 is a perspective view of a carbon nanostructure pattern manufactured by a method of manufacturing a carbon nanostructure pattern according to an embodiment of the present disclosure, and FIG. 2 is a cross-sectional view taken along II-II of FIG. 1.

As shown in FIGS. 1 and 2, the carbon nanostructure pattern may include a substrate 10, an optional barrier layer 20, and a carbon nanostructure layer 30, which will be described later. It is manufactured by the method.

Hereinafter, a method of manufacturing a carbon nanostructure pattern according to the present application will be described in detail with reference to the drawings.

3 is a flowchart illustrating a method of manufacturing a carbon nanostructure pattern according to an embodiment of the present disclosure, and FIGS. 4A to 4C are cross-sectional views illustrating a method of manufacturing a carbon nanostructure pattern according to an embodiment of the present disclosure.

First, as shown in FIGS. 3 and 4A, the metal catalyst layer 50 is formed on the substrate 10 (S100).

Specifically, the substrate 10 is not particularly limited, and may be, for example, silicon, glass, plastic, oxide substrate, or the like. When the substrate and the metal catalyst may react, a barrier layer 20 including an insulator may be formed on the substrate 10 to prevent such a reaction. In this case, the carbon nanostructure layer 30 is formed on the barrier layer 20.

Barrier layer 20 may include, but is not limited to, SiO ₂ , SiN _x , Al ₂ O ₃ , HfO _x , and the like. When the substrate 10 is a silicon substrate, the silicon substrate surface may be treated with ultraviolet (UV) and O ₃ to form a barrier layer 20 including SiO ₂ , or the silicon substrate surface may be in a nitrogen atmosphere. By processing, the barrier layer 20 containing SiN _x can be formed.

The barrier layer 20 may be selectively formed on the substrate 10, and then the metal catalyst layer 50 may be formed on the substrate 10. The height of the metal catalyst layer 50 is not particularly limited and may be appropriately selected by those skilled in the art in a range suitable for the characteristics of the desired electrical and electronic device, and may be, for example, in the range of nanometer, micrometer, or millimeter size, but is not limited thereto. It doesn't happen. The metal catalyst layer 50 may include all common metals that may be used as a catalyst for growth of the carbon nanostructure layer 30 to be formed later, for example, Cu, Fe, Ni, Co, Pt, Ir, Pd And it may include one or more metals or alloys thereof selected from the group consisting of Ru. The metal catalyst layer 50 is, by way of non-limiting example, sputtering, e-beam evaporation, sol-gel combustion of metal mixtures, ion exchange precipitation using metal precursors, electroplating (Electroplating), electroless plating (Electroless Plating) and the like can be formed.

Next, a mask layer 60 is formed on the metal catalyst layer 50 (S110).

Specifically, the mask layer 60 is formed on the metal catalyst layer 50 using, for example, chemical vapor deposition (CVD) or plasma vapor deposition. The mask layer 60 may include any insulating material capable of preventing the growth reaction of the carbon nanostructure layer 30 by the metal catalyst layer 50 upon growth of the carbon nanostructure layer 30 to be formed later. For example, in addition to one or more insulating materials selected from the group consisting of SiO ₂ , SiN _x , Al ₂ O _3, and HfO _x , TiN may not serve as a growth catalyst for the carbon nanostructure layer 30. In addition, the mask layer 60 may be formed using, for example and non-limiting examples, an arc discharge method, a laser vaporization method, an electrolysis method, or a flame synthesis method.

Next, as shown in FIGS. 3 and 4B, the metal catalyst layer 50 and the mask layer 60 are etched to form a desired pattern (S120). This etching method can be performed using traditional lithography and etching. On the other hand, the term "desired pattern" is, for example, in the form of a conductive pattern constituting a thin film transistor, or in the form of a conductive pattern constituting a chip formed on a chip on substrate (chip on substrate) May be, but is not limited thereto.

Specifically, for example, first, after forming a photoresist layer on the mask layer 60, the photoresist layer is exposed and developed through a mask in which the set pattern is formed to correspond to the set pattern. A photoresist pattern is formed. In this case, the photoresist pattern exposes portions of the metal catalyst layer 50 and the mask layer 60 to be etched. Next, the metal catalyst layer 50 and the mask layer 60 exposed through the photoresist pattern are etched using the photoresist pattern as a mask to include the metal catalyst layer 50 and the mask layer 60 on the substrate 10. To form the desired pattern. Thereafter, the photoresist pattern is removed from the mask layer 60 using an ashing process or a lift off process. On the other hand, the photoresist pattern may not be removed if necessary.

The mask layer 60 for blocking the metal catalyst layer 50 is exposed on the upper surface of the pattern formed by etching the metal catalyst layer 50 and the mask layer 60 using a photolithography process. The metal catalyst layer 50 is exposed on the side surface of the pattern.

Next, as shown in FIGS. 3 and 4C, the carbon nanostructure layer 30 is grown on the side surface 51 of the metal catalyst layer 50 of the pattern (S130).

For example, chemical vapor deposition that decomposes a precursor containing carbon such as acetylene (C ₂ H ₂ ) or methane (CH ₄ ) using thermal energy or plasma chemical vapor deposition that decomposes using plasma energy. Etc., the carbon nanostructure layer 30 is selectively grown on the side surface 51 of the metal catalyst layer 50. The grown carbon nanostructure layer 30 may include graphene, carbon nanotubes, carbon nanofibers, carbon nanowires, or carbon nanocones. In addition, as a non-limiting example, the carbon nanostructure layer 30 may be formed using an arc discharge, laser vaporization, electrolysis, flame synthesis, or the like.

Next, as shown in FIG. 3, the metal catalyst layer 50 and the mask layer 60 of the pattern in which the carbon nanostructure layer 30 is selectively grown on only the side surface are removed (S140).

For example, the metal catalyst layer 50 and the mask layer 60 except for the carbon nanostructure layer 30 using a wet etching process using an etchant in which the metal catalyst layer 50 and the mask layer 60 are selectively etched. By removing some or all of the portion from the substrate 10, only the carbon nanostructure layer 30 is formed on the substrate 10.

As described above, the present application selectively forms the carbon nanostructure layer 30 only on the side surface 51 of the metal catalyst layer 50 formed in a desired pattern, thereby implanting the grown carbon nanostructure layer 30 into another substrate. Since the carbon nanostructure layer 30 can be used as it is in the grown substrate 10, the manufacturing process of the carbon nanostructure pattern is simplified. That is, by simplifying the manufacturing process of the carbon nanostructure pattern, it is possible to lower the manufacturing cost of the carbon nanostructure pattern and at the same time the carbon nanostructure layer 30 that may be generated by the process of implanting the carbon nanostructure layer 30 on another substrate. ) Breakage is prevented. In addition, an additional conductive pattern may be formed on the carbon nanostructure pattern manufactured by the above process to manufacture an electric device such as a thin film transistor.

In addition, the field emission device may be manufactured on the carbon nanostructure pattern manufactured by the above process.

In a fifth aspect of the present disclosure, a method of manufacturing a carbon nanostructure thin film transistor may be provided, comprising the following steps:

Forming a metal catalyst layer on the substrate;

Forming a mask layer on the metal catalyst layer;

Etching the metal catalyst layer and the mask layer to form a mold pattern having the metal catalyst layer exposed on a side surface thereof;

Forming a carbon nanostructure layer on the side of the metal catalyst layer of the template pattern;

Removing a part or all of the metal catalyst layer and the mask layer of the template pattern to form a carbon nanostructure pattern layer;

Forming a gate insulating layer on the substrate;

Forming a gate electrode on the substrate; And

Forming a source / drain electrode in electrical contact with the carbon nanostructure pattern layer.

In one embodiment of the present application, the carbon nanostructure layer may be in the form of a nano-ribbon.

In another embodiment of the present disclosure, the carbon nanostructure may include graphene, carbon nanotubes, carbon nanofibers, carbon nanowires, or carbon nanocones, but is not limited thereto. For example, the carbon nanostructure layer may include graphene, but is not limited thereto. In one embodiment, the graphene may have a nanoribbon form.

In another embodiment of the present disclosure, the metal catalyst layer may include, but is not limited to, a metal used as a catalyst for growth of the carbon nanostructure layer.

In another embodiment of the present disclosure, the metal may include one or more metals or alloys thereof selected from the group consisting of Cu, Fe, Ni, Co, Pt, Ir, Pd, and Ru, but is not limited thereto. Does not.

In another embodiment of the present disclosure, the mask layer includes at least one selected from the group consisting of SiO ₂ , SiN _x , Al ₂ O ₃ , HfO _x , Silicon-on-Glass (SOG), ZrO, and TiN. It may be, but is not limited thereto.

In another embodiment of the present invention, growing the carbon nanostructure layer on the metal catalyst layer side of the template pattern, the carbon nanostructure layer by chemical vapor deposition by decomposing the precursor containing carbon by heat or plasma It may be to include growing.

In another embodiment of the present disclosure, the method may further include forming a barrier layer between the substrate and the metal catalyst layer.

In another embodiment of the present disclosure, the barrier layer may include, but is not limited to, one or more selected from the group consisting of SiO ₂ , SiN _x , Al ₂ O ₃ , HfO _x , SOG, and ZrO. Do not.

In the sixth aspect of the present application, it is possible to provide a carbon nanostructure thin film transistor manufactured according to the manufacturing method.

In one embodiment of the present application, the graphene layer included in the thin film transistor may have a nanoribbon form.

Hereinafter, one embodiment and one embodiment of the carbon nanostructure thin film transistor of the present application and a manufacturing method thereof will be described in detail with reference to the accompanying drawings. However, the present application is not limited thereto.

5 is a flowchart illustrating a method of manufacturing a carbon nanostructure thin film transistor according to an embodiment of the present disclosure, and FIGS. 6A to 6F are cross-sectional views illustrating a method of manufacturing a carbon nanostructure thin film transistor according to an embodiment of the present disclosure. .

First, as shown in FIGS. 5 and 6A, the metal catalyst layer 300 is formed on the substrate 100 (S200).

Specifically, the substrate 100 is not particularly limited and may be, for example, silicon, glass, plastic, oxide substrate, or the like. If there is a possibility that the substrate and the metal catalyst may react, a barrier layer 200 including an insulator may be formed on the substrate 100 to prevent such a reaction. In this case, the carbon nanostructure layer 500 is formed on the barrier layer 200.

The barrier layer 200 may include, but is not limited to, one or more selected from the group consisting of SiO ₂ , SiN _x , Al ₂ O ₃ , HfO _x , SOG, and ZrO. When the substrate 100 is a silicon substrate, the surface of the silicon substrate may be treated with oxygen atmosphere or ultraviolet (UV) and O ₃ to form a barrier layer 200 including SiO ₂ , or the silicon substrate By treating the surface in a nitrogen atmosphere, the barrier layer 200 including SiN _x can be formed.

The barrier layer 200 is selectively formed according to the type of the substrate 100, and then the metal catalyst layer 300 is formed on the substrate 100. The height of the metal catalyst layer 300 is not particularly limited and may be selected by those skilled in the art in a range suitable for the characteristics of the desired electric and electronic device. Here, the height of the carbon nanostructure layer 500 to be later grown on the side (wall) of the metal catalyst layer 300 according to the height (thickness) of the metal catalyst layer 300 [carbon nanostructure layer ribbon width: T (See FIG. 7)] may be determined. The metal catalyst layer 300 may include all common metals that may be used as a catalyst for growth of the carbon nanostructure layer 500 to be formed later, for example, the metal may be Cu, Fe, Ni, Co, Pt, It may include one or more metals or alloys thereof selected from the group consisting of Ir, Pd and Ru, but is not limited thereto. The metal catalyst layer 300 includes, but is not limited to, sputtering, e-beam evaporation, sol-gel combustion of a metal mixture, ion exchange precipitation using a metal precursor, and electroplating. (Electroplating), electroless plating (Electroless Plating) and the like can be formed.

Next, a mask layer 400 is formed on the metal catalyst layer 300 (S210).

Specifically, for example, the mask layer 400 may be formed on the metal catalyst layer 300 using a chemical vapor deposition or a plasma vapor deposition process. The mask layer 400 may include any insulating material capable of preventing a growth reaction of the carbon nanostructure layer 500 on the metal catalyst layer 300 upon growth of the carbon nanostructure layer 500 to be formed later. For example, it may include one or more insulating materials selected from the group consisting of SiO ₂ , SiNx, Al ₂ O ₃ , HfOx, SOG, and ZrO. In addition, the mask layer 400 may be formed using, for example and non-limiting examples, an arc discharge, laser vaporization, electrolysis, flame synthesis, or the like.

Next, as shown in FIG. 6B, the metal catalyst layer 300 and the mask layer 400 are etched to form a desired mold pattern (S220). This etching method can be performed using traditional lithography and etching. On the other hand, herein, the "desired pattern" may be, for example, a conductive pattern in which carbon nanostructures in the form of nanoribbons to be completed may be formed, but are not limited thereto.

Specifically, for example, first, a photoresist layer is formed on the mask layer 400, and then the photoresist layer is exposed and developed through a mask having a set pattern to correspond to the set pattern. A photoresist pattern is formed. In this case, the photoresist pattern exposes portions of the metal catalyst layer 300 and the mask layer 400 to be etched. Next, the metal catalyst layer 300 and the mask layer 400 exposed through the photoresist pattern are etched using the photoresist pattern as a mask to include the metal catalyst layer 300 and the mask layer 400 on the substrate 100. To form the desired pattern. Thereafter, the photoresist pattern is removed from the mask layer 400 using an ashing process or a lift off process. On the other hand, the photoresist pattern may not be removed if necessary.

The mask layer 400 for blocking the metal catalyst layer 300 is exposed on the upper surface of the pattern formed by etching the metal catalyst layer 300 and the mask layer 400 using a photolithography process. The metal catalyst layer 300 is exposed on the side surface of the pattern.

Next, as shown in Figure 6c, the carbon nanostructure layer 500 is grown on the side surface 310 of the metal catalyst layer 300 of the template pattern (S230).

For example, a thermal chemical vapor deposition method for decomposing carbon-containing precursors such as acetylene (C ₂ H ₂ ) or methane (CH ₄ ) using thermal energy or plasma chemical vapor decomposition using plasma energy. The carbon nanostructure layer 500 may be selectively grown on the side surface 310 of the metal catalyst layer 300 by a deposition method or the like. The grown carbon nanostructure 500 may include graphene, carbon nanotubes, carbon nanofibers, carbon nanowires, or carbon nanocones, but is not limited thereto. In addition, the carbon nanostructure layer 500 may be formed using, for example and non-limiting examples, an arc discharge, laser vaporization, electrolysis, or flame synthesis.

Next, as shown in FIG. 6D, the carbon nanostructure pattern layer may be partially or partially removed from the metal catalyst layer 300 and the mask layer 400 of the pattern in which the carbon nanostructure layer 500 is selectively grown on only the side surface. 500 may be formed (S240).

For example, by using a wet etching process using an etchant in which the metal catalyst layer 300 and the mask layer 400 are selectively etched, the mask layer 400 is entirely removed, and the metal catalyst layer 300 is partially removed. The patterned metal catalyst layer 300 and the carbon nanostructure pattern layer 500 formed along the side surface of the metal catalyst layer 300 may be formed on the substrate 100.

Thereafter, as shown in FIG. 6E, the gate insulating layer 600 is formed on the substrate on which the carbon nanostructure pattern layer 500 is formed (S250). The gate insulating layer 600 may be formed of at least one insulating material selected from the group consisting of SiO ₂ , SiN _x , Al ₂ O ₃ , HfO _x , SOG, and ZrO.

Finally, as shown in FIG. 6F, after the gate insulating layer 600 is formed, a gate electrode material layer may be formed on the gate insulating layer 600, and then the gate electrode material layer is patterned. The gate electrode 700 may be formed (S260). The gate electrode material may be a metal such as chromium (Cr), molybdenum (Mo), or aluminum (Al), or a carbon structure, polysilicon, or the like, which is commonly used as the gate electrode material, but is not limited thereto. The gate electrode material layer may be formed by Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD), and the Chemical Vapor Deposition is a metal organic chemical vapor deposition (MOCVD) or atmospheric pressure chemical vapor phase. It may be one of a deposition method (APCVD), low pressure chemical vapor deposition (LPCVD), plasma accelerated chemical vapor deposition (PECVD) and atomic layer deposition (ALD).

Here, the method of patterning the gate electrode material layer may include, but is not limited to, a lithography process using the photoresist pattern described above.

Thereafter, the source / drain electrodes (not shown) may be formed using materials and methods used in the art, and include, for example, Al doped zinc oxide (AZO), indium tin oxide (ITO), and cobalt (Co). ), Iron (Fe), nickel (Ni), chromium (Cr), gold (Au), silver (Ag), copper (Cu), aluminum (Al), platinum (Pt), tin (Sn), tungsten (W ), Ruthenium (Ru), palladium (Pd) and cadmium (Cd) can be formed from one or more of the chemical vapor deposition (Chemical Vapor Deposition, CVD) or physical vapor deposition (Physical vapor deposition, PVD) The source / drain electrode material layer may be formed of, for example, and then patterned by a lithography process to form a source / drain electrode in electrical contact with the carbon nanostructure pattern layer 500 (S270). The chemical vapor deposition may be one of metal organic chemical vapor deposition (MOCVD), atmospheric chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), plasma accelerated chemical vapor deposition (PECVD) and atomic layer deposition (ALD). However, an interlayer insulating layer may be formed between the gate electrode 700 and the source / drain electrode to insulate the two electrodes with the same material as the aforementioned gate insulating layer.

7 is a perspective view of a carbon nanostructure thin film transistor according to one embodiment of the present application as described above.

Hereinafter, the present invention will be described in more detail with reference to Examples, but the scope of the present invention is not limited by these Examples.

First, the silicon substrate was washed as distilled water, acetone, and ethanol, respectively, as the substrate 10, and the N ₂ gas was purged between each washing step to remove contaminants from the substrate.

Next, the silicon substrate surface was treated with ultraviolet and O ₃ to form a barrier layer 20 containing SiO ₂ on the substrate 10.

Next, a metal catalyst layer 50 including Pt was formed on the substrate 10 using a sputtering process on the barrier layer 20.

Next, a mask layer 60 including Al ₂ O ₃ was formed on the metal catalyst layer 50 by using a chemical vapor deposition process.

Next, the metal catalyst layer 50 and the mask layer 60 were etched using a photolithography process to form a desired mold pattern. The metal catalyst layer 50 is exposed on the side surface 51 of the mold pattern.

Next, methane (CH ₄ ), which is a precursor containing carbon, was decomposed using heat by thermal chemical vapor deposition, thereby selectively growing graphene as a carbon nanostructure 30 only on the side surface 51 of the metal catalyst layer 50.

Next, the entire metal catalyst layer 50 and the mask layer 60 are removed from the substrate 10 using a wet etching process using an etchant in which the metal catalyst layer 50 and the mask layer 60 are selectively etched. After removal, only the graphene pattern (nanoribbon) remained on the substrate as it is (see FIG. 4).

First, the silicon substrate (SiO ₂ / Si) on which the silicon oxide film is formed as the substrate 100 is washed in the order of distilled water, acetone, and ethanol, respectively, and N ₂ between washing steps. The gas was purged to remove contaminants from the substrate.

Next, the substrate surface was treated with ultraviolet rays and O ₃ to form a barrier layer 200 including SiO ₂ on the substrate 100.

Next, a metal catalyst layer 300 including Pt was formed on the substrate 100 by using a sputtering process on the barrier layer 200.

Next, a mask layer 400 including Al ₂ O ₃ was formed on the metal catalyst layer 300 by using a chemical vapor deposition process.

Next, the metal catalyst layer 300 and the mask layer 400 were etched using a photolithography process to form a desired mold pattern. The metal catalyst layer 300 is exposed on the side surface 310 of the mold pattern.

Next, the carbon-containing precursor methane (CH ₄ ) is decomposed using heat by thermal chemical vapor deposition, thereby selectively forming the graphene nano ribbon as the carbon nanostructure layer 500 only on the side 310 of the metal catalyst layer 300. Grown.

Next, a part of the metal catalyst layer 300 and the entire mask layer 400 are removed from the substrate 100 by using a wet etching process using an etchant in which the metal catalyst layer 300 and the mask layer 400 are selectively etched. 2), the patterned metal catalyst layer 300 and the pattern of graphene nanoribbons grown on the side of the metal catalyst layer 300 remained on the substrate.

Thereafter, a gate insulating layer 600 including SiO ₂ was formed on the entire surface of the substrate 100.

Finally, the gate electrode 700 was formed by forming a gate electrode material layer on the substrate by chemical vapor deposition using molybdenum (Mo) metal, and then patterning it through a lithography process, and using Ni as a chemical vapor deposition method. A source / drain electrode layer was formed on the substrate 100. Thereafter, the source / drain electrode layer was patterned to contact the metal catalyst layer using a lithography process to form a source / drain electrode to complete the graphene thin film transistor (see FIGS. 6 and 7).

In this embodiment, a schematic overall process flow for producing a fin-type graphene ribbon is shown in FIGS. 8 and 9. In a specific manufacturing process, a 300 nm thick SiO ₂ layer was first deposited on a Si substrate. 300 nm-nickel (Ni) and 200 nm-SiO ₂ were then deposited successively by sputtering and CVD (FIG. 8 (a)). The nickel film serves as a catalyst for graphene growth, the upper SiO ₂ 200 nm serves as a protective layer to protect the top surface of the Ni catalyst from graphene synthesis. The SiO ₂ layer A photoresist (PR) was spin-coated onto the substrate and patterned by photolithography to expose a portion of the SiO ₂ / Ni laminate to form a mold pattern. The exposed SiO ₂ / Ni laminate outer pattern was dry-etched by an inductively coupled plasma (ICP) etcher, or buffered oxide etchant (BOE) for SiO ₂ and Ni, and Wet-etched with each nitric acid (FIG. 8 (b)). Through these steps, only the side of the nickel catalyst is exposed, and graphene can be grown by CVD on the exposed side of the nickel catalyst. Next, the PR was removed with acetone (Fig. 8 (c), Fig. 9 (a)). The sample thus obtained (size 1-2 cm ² ) was loaded into a CVD quartz reactor equipped with a halogen lamp heating system. The chamber was maintained in vacuum under 1 m Torr by a mechanical pump and purged in an argon (Ar) atmosphere (99.999% purity). Hydrogen (H ₂ ) (99.999% purity) gas was then allowed to be injected into the reactor to prevent oxidation of the catalyst nickel metal while increasing the temperature. The samples were pre-annealed under Ar and H ₂ gas atmosphere at 900-950 ° C., and graphene growth was performed at 850-900 ° C. (FIG. 8 (d), FIG. 9 (b)). To realize the pin-type graphene ribbon, after graphene growth, the upper SiO ₂ layer and the Ni layer, respectively, at the center of the entire ribbon pattern were replaced with 10: 1 BOE and FeCl ₃ -based etching solution (Transcene Co. Type I). After etching, two parallel graphene ribbons were obtained, as shown in FIGS. 8 (e) and 9 (c). When performing the top gate (upper gate) process, as shown in FIG. 9 (d), a novel pin-type graphene transistor may be implemented using a graphene ribbon.

Compared with the conventional CVD process for the graphene ribbon transistor, the process according to the present application does not require a graphene transfer process because lateral graphene is used. In addition, since the graphene ribbon is pin-type vertical, practical dual gate graphene transistors can be easily implemented. Graphene synthesized horizontally on conventional continuous nickel films can be easily examined by optical microscopy, Raman spectroscopy, and atomic force microscopy (AFM). However, lateral graphene according to the present application is very difficult to determine if a very thin graphene layer is present only on the side of the metal catalysis. In this embodiment, the lateral growth graphene is observed by a transmission electron microscope (TEM), and current-voltage measurement of a ribbon resistor or a transistor using the same is performed by a semiconductor analyzer (Agilent B1500A).

First, TEM observation of graphene synthesized on bulk Ni catalyst without cap SiO ₂ layer was performed. FIG. 10A shows an optical micrograph of graphene synthesized by CVD on a continuous Ni film without a cap SiO ₂ layer, where a typical optical image of graphene was observed. Some points of graphene synthesized on Ni, which exhibit a darker gray color, are regions composed of a layer of graphene thicker than the surroundings (FIG. 10 b). The number of layers of grown graphene was observed by Raman spectroscopy (FIG. 10C). Some regions show a 2D / G peak ratio of> 1, which represents a single layer graphene, and some regions represent a 2D / G peak ratio of <1, which shows multilayer graphene.

Next, TEM observation was performed on the graphene synthesized on the side of the Ni catalyst. Figure 11 (a) is a cross-sectional schematic of lateral graphene growth, Figure 11 (b) is a cross-sectional SEM image after dry-etching the upper SiO ₂ and Ni layer. The slopes of Ni and SiO ₂ are not perpendicular but ˜64 °. FIG. 11 (c) is a cross-sectional low magnification TEM image of the layer deposited after CVD growth, and FIG. 11 (d) is an enlarged TEM image of the selected side region. After the CVD, lateral graphene (~ several layers of graphene) was identified between the Ni and platinum (Pt) (layer deposited for TEM image) layers, as shown in FIG. 11 (d). In FIG. 11 (d), the interlayer distance was found to be ˜0.3 nm from the intensity profile of the TEM image, indicating layers of graphene. The synthesized lateral graphene ribbon can be used as a channel for a resistor or transistor. For this purpose, the Ni layer supporting the side graphene at the center portion of the ribbon pattern was etched by FeCl ₃ -based wet etching solution (Transcene Co. Type I), and shown in FIGS. 8 (e) and 9 (c). As shown, two parallel graphene ribbons were obtained.

In order to confirm that Ni was completely etched, the I-V curve of the ribbon was measured before and after etching Ni using the measuring apparatus of FIG. 12 (a), respectively, and is shown in FIG. 12 (b, c). It was also confirmed that a negligible amount of current flows for the CVD-skipped samples after the Ni etching. In order to confirm the feasibility of gate modulation on the manufactured graphene ribbon, a back gate was applied to the p-type substrate.

FIG. 13 (a) is a diagram showing an IV measurement of the manufactured side graphene ribbon transistor. 13 (b) and 13 (c) are typical output and transfer characteristics that operate in a back gate configuration. The drain current showed a linear dependence on the drain voltage and did not indicate saturation of the drain current. The drain current is shown to be regulated to the back gate voltage in effect. This is quite surprising that the graphene ribbon produced exhibits back gate modulation characteristics since the back gate oxide only contacts the bottom edge of the ribbon. Many improved output characteristics are expected to be achieved if the ribbon is modulated by the top gate oxide. The transfer characteristic shows a drain current that decreases with increasing gate voltage ((Fig. 13 (c)), which indicates a p-type channel conductivity. The strong p-type conductivity is observed for all manufactured graphene ribbon transistors). Graphene is easily p-doped by adsorbates, which causes charge transfer from graphene to adsorbed molecules, and, in addition, the formation of weak CO bonds between graphene and SiO ₂ from carbon. The transfer of charge to oxygen of the SiO ₂ / Si substrate may contribute to the p-type conductivity in the graphene.

It will be understood by those of ordinary skill in the art that the foregoing description of the embodiments is for illustrative purposes and that those skilled in the art can easily modify the invention without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

The scope of the present application is indicated by the following claims rather than the above description, and it should be construed that all changes or modifications derived from the meaning and scope of the claims and their equivalents are included in the scope of the present application.

10: substrate
20: barrier layer
30: carbon nanostructure layer
50: metal catalyst layer
60 mask layer
100: substrate
200: barrier layer
300: metal catalyst layer
400: mask layer
500: carbon nanostructure layer (pattern)
600: gate insulating layer
700: gate electrode

Claims (24)

A method for producing a graphene pattern, comprising the following steps:
Forming a metal catalyst layer on the substrate;
Forming a mask layer on the metal catalyst layer;
Etching the metal catalyst layer and the mask layer to form a mold pattern having the metal catalyst layer exposed on a side surface thereof;
Growing a graphene layer on the side of the metal catalyst layer of the template pattern; And
Removing the part or all of the metal catalyst layer and the mask layer of the template pattern to form the graphene pattern.
delete The method of claim 1,
The metal catalyst layer is a graphene pattern manufacturing method comprising a transition metal used as the catalyst for graphene growth.
The method of claim 3, wherein
Wherein the metal is one or more metals selected from the group consisting of Cu, Fe, Ni, Co, Pt, Ir, Pd and Ru or alloys thereof, the method for producing a graphene pattern.
The method of claim 1,
Wherein the mask layer comprises one or more selected from the group consisting of SiO ₂ , SiN _x , Al ₂ O ₃ , HfO _x , and TiN, graphene pattern manufacturing method.
The method of claim 1,
The step of growing a graphene layer on the side of the metal catalyst layer of the template pattern, comprising the growth of the graphene layer by decomposing a precursor containing carbon by heat or plasma, graphene pattern manufacturing method.
The method of claim 1,
And forming a barrier layer between the substrate and the metal catalyst layer.
The method of claim 7, wherein
Wherein the barrier layer, SiO ₂ , SiN _x , Al ₂ O ₃ And HfO _{x It} will be one or more selected from the group consisting of, Graphene pattern manufacturing method.
delete delete delete delete A method for manufacturing a graphene thin film transistor, comprising the following steps:
Forming a metal catalyst layer on the substrate;
Forming a mask layer on the metal catalyst layer;
Etching the metal catalyst layer and the mask layer to form a mold pattern having the metal catalyst layer exposed on a side surface thereof;
Forming a graphene layer on the side of the metal catalyst layer of the template pattern;
Removing a part or all of the metal catalyst layer and the mask layer of the template pattern to form a graphene pattern layer;
Forming a gate insulating layer on the substrate;
Forming a gate electrode on the substrate; And
Forming a source / drain electrode in electrical contact with the graphene pattern layer.
delete delete The method of claim 13,
The metal catalyst layer comprises a metal used as the catalyst for graphene layer growth, a graphene thin film transistor manufacturing method.
17. The method of claim 16,
Wherein the metal is one or more metals selected from the group consisting of Cu, Fe, Ni, Co, Pt, Ir, Pd and Ru or alloys thereof, the method for manufacturing a graphene thin film transistor.
The method of claim 13,
The mask layer is a graphene thin film transistor manufacturing method comprising one or more selected from the group consisting of SiO ₂ , SiN _x , Al ₂ O ₃ , HfO _x , SOG, ZrO, and TiN.
The method of claim 13,
Forming a graphene layer on the side of the metal catalyst layer of the template pattern, comprising the growth of the graphene layer by decomposing a precursor containing carbon by heat or plasma, a method for manufacturing a graphene thin film transistor .
The method of claim 13,
And forming a barrier layer between the substrate and the metal catalyst layer.
21. The method of claim 20,
Wherein the barrier layer, SiO _2, SiN _x , Al ₂ O ₃ , HfO _x , SOG and ZrO comprising one or more selected from the group consisting of, a graphene thin film transistor manufacturing method.
The method of claim 13,
The graphene layer is formed in the form of a nano-ribbon, graphene thin film transistor manufacturing method. delete delete

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