KR100788902B1 - Mixcolum block device and method of multiplication calculation thereof - Google Patents

Abstract

A MixColumn block device and a multiplication method using the same are provided to be applied to a small and low power portable device with a simple structure while increasing an encryption performance by including an AES block algorithm. A storing part(210) stores bit data as a byte unit and outputs stored byte data. A first multiplication block(220) outputs a multiplied result by performing [01] and [02] multiplication, which is a hexadecimal value of an input byte received from the storing part. A second multiplication block(230) outputs the multiplied result by performing [01], [02], and [03] multiplication, which is the hexadecimal value, with the result of the [01] and [02] multiplication. An XOR unit(240) outputs an output byte for the input byte by performing XOR operation for the result of the [01], [02], and [03] multiplication.

Description

MixColumn block device and method of multiplication calculation

1 is a hardware configuration diagram illustrating a conventionally used AES encryption algorithm.

FIG. 2 is a diagram for describing a calculation process of a mix column block in a hardware configuration of an AES encryption algorithm used in the present invention.

3 is a hardware configuration diagram of a mix column block device according to an embodiment of the present invention.

FIG. 4 is a diagram for describing {01} and {02} multiplication operations of the first multiplication block unit according to an exemplary embodiment of the present invention.

5 is a view showing in detail the configuration of the {02} multiplication block according to an embodiment of the present invention.

6 is a diagram for describing a {03} multiplication operation according to an embodiment of the present invention.

7 is a view showing in detail the configuration of the exclusive OR operation unit of the mix column block device according to an embodiment of the present invention.

8 is a flowchart illustrating a multiplication operation of the mixed column block device according to an embodiment of the present invention.

9 is a flowchart illustrating a multiplication operation of the {02} multiplication unit of the mix column block device according to an embodiment of the present invention.

FIG. 10 is a diagram for describing a {03} multiplication process of a mix column block device according to an embodiment of the present invention in detail.

11 to 14 are views for explaining the output byte operation process of the mixed column block device according to an embodiment of the present invention.

The present invention relates to a mix column block device and a multiplication operation method using the same. More specifically, the present invention relates to a mixed column block device constituting an AES (Advanced Encryption Standard) block algorithm, and a multiplication operation method using the same.

1 is a hardware configuration diagram illustrating a conventionally used AES encryption algorithm.

According to FIG. 1, the AES encryption algorithm is composed of an initial round processor 110, a repetitive round processor 120, and a last round processor 130.

Here, the initial round processing unit 110 is composed of a round key processing (AddRoundKey) block 124 for processing the round key for encryption, the repeat round processing unit 120 is a sub for performing a substitution operation on each byte Performs additional linear transformation of the matrix moved by the SubRows block 121, the matrix of each data component of the AES, the ShiftRows block 122, and the shift row block 122 to move the rows. The MixColumns (MixColums) block 123 and the Round Key Processing (AddRoundKey) block 124. The last round processor 130 is composed of a SubBytes block 121, a ShiftRows block 122, and a RoundKey Processing (AddRoundKey) block 124.

Here, the shift row block 122 or the round key processing block 124 can be easily implemented in hardware by shifting the positions of bytes (8 bits).

However, when the sub-byte block 121 and the mix column block 123 are implemented in hardware, the overall processing speed according to the multiplication operation is slowed down, and the use of the multiplier uses a lot of hardware resources, which is not suitable for mobile device application. have.

Meanwhile, Korean Patent Application No. 2003-0051111 “Round processing unit circuit and online round key generation circuit for hardware implementation of AES Rijndael (Linedal) encryption algorithm” and Korean Patent Application No. 2005-0092576 “ A data encryption processing device, an AES encryption system, and an AES encryption method to which a masting method is applied ”are disclosed.

The above-mentioned prior arts propose a method of reducing hardware resources by sharing hardware resources or simplifying subbytes, but there is no mention of a multiplier of a mix column block.

In addition, as another prior art, Korean Patent Application No. 2004-0047105, “Multinomial Multiplication Apparatus and Method for Block Ciphers,” refers to a multiplication apparatus for a mix column block. There is a lot of redundancy in the use of hardware.

Accordingly, an object of the present invention is to provide a mix column block device composed of simple hardware and a multiplication operation method using the same, which can be easily applied to a small, low-power portable device while improving encryption performance.

Mix column block device according to a feature of the present invention to achieve the problem as described above,

A Mixed Column (MixColums) block device for performing AES (Advanced Encryption Standard) block cipher round operations, comprising: a storage unit for storing input data in units of bytes and outputting stored input bytes; A first multiplication block block configured to perform a multiplication operation of {01} and {02}, which are hexadecimal values, of the input byte received from the storage unit; A second hexadecimal value {01}, {02} and {03} that are multiplied by a result of performing the {01} and {02} multiplication operations received from the first multiplication block unit; Multiplication operation block portion; And an exclusive OR operation unit configured to output an output byte for the input byte by performing an exclusive OR operation on the result of performing the {01}, {02} and {03} multiplication operations received from the second multiplication operation block unit. It includes.

The multiplication operation method of the mixed column block device according to the characteristics of the present invention,

A multiplication operation method for a mixed column block performing a round operation of an AES block cipher, the method comprising: performing {01} and {02} multiplication operations that are hexadecimal values on an input byte; Performing multiplication operations of hexadecimal values {01}, {02} and {03} using the results of performing the {01} and {02} multiplication operations; Performing an exclusive OR operation on the result of performing the {01}, {02}, and {03} multiplication operations; And outputting a result of performing the exclusive OR operation as an output byte for the input byte.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

In addition, when a part is said to "include" a certain component, this means that it may further include other components, except to exclude other components unless otherwise stated.

In addition, the term module described herein refers to a unit for processing a specific function or operation, which may be implemented in hardware or software, or a combination of hardware and software.

First, for convenience of understanding, the present invention will briefly present a process of calculating a mixed column block according to the present invention.

FIG. 2 is a diagram for describing a calculation process of a mix column block in a hardware configuration of an AES encryption algorithm used in the present invention.

When 128-bit plain text input is passed through a subbyte block to a mixed column block, as shown in FIG. 2, the matrix is arranged in a 4 × 4 matrix form of bytes, and the column unit (32 bits) of the matrix becomes the input of the mixed column block. .

The heat conversion method uses the polynomial shown in Equation 1 below using the finite field GF (28) and the fourth degree modulus x ⁴ +1.

When the mixed column conversion is calculated using the polynomial shown in Equation 1, the determinant of Equation 3 is given in Equation 2 below.

는 입력 바이트를 의미하고

는 출력 바이트를 의미한다.here,

Means input byte

Is the output byte.

By calculating Equation 3 above, Equation 4 can be obtained.

)에 대하여 {02} 곱셈연산 및 {03} 곱셈연산을 한 다음 배타적 논리합(XOR) 연산을 하면 믹스컬럼블록의 출력 바이트(

)를 만들 수 있다. 여기서, {02}, {03}은 16진수 값을 의미한다.In Equation 4 above, each input byte (

) And the exclusive OR (XOR) operation with {02} multiplication and {03} multiplication, then the output byte (

) Can be made. Here, {02} and {03} mean hexadecimal values.

In this case, referring to the {02} multiplication operation in Equation 4, a modulo operation is performed by using the polynomial of Equation 5 below instead of simply performing arithmetic multiplication of '2'.

Referring to the calculation as an embodiment, it is calculated as shown in Equation 6 below.

At this time, the modulo operation using the polynomial of Equation 5 to the result of Equation 6 is as follows.

modulo

modulo

As shown in Equation 7, the modulo operation completes the {02} multiplication operation.

In this case, rather than performing the {02} multiplication operation as described above, the {02} multiplication operation shifts the input byte 1 bit to the left to obtain a multiplication value. XOR) operation can be performed.

Here, since the polynomial for modulo operation of Equation 5 is an eighth order polynomial, if the most significant bit of the input byte is '0', it is not necessary to perform the modulo operation. The exclusive OR is performed only when the most significant bit is '1'.

When the most significant bit is '1', the most significant bit of the {11D} XOR operation is always '0', so only the {1D} exclusive OR (XOR) operation is performed on the left 1-bit shift result without the need for 9-bit operations.

That is, the multiplication operation may be performed with a mux for selecting an output value according to the shift register, one 8-bit exclusive OR operation, and the most significant bit of the input byte.

{02} 연산과 동일하고 {01} 곱셈연산은 입력 바이트와 동일하다. 즉 {03} 곱셈연산은 입력 바이트와 {02} 곱셈연산을 배타적 논리합(XOR) 연산하면 된다.Also, the {03} multiplication operation is {01}

Same as {02} operation, and the {01} multiplication operation is equivalent to the input byte. That is, the {03} multiplication operation is performed by performing an exclusive OR on the input byte and the {02} multiplication operation.

Therefore, for the {03} multiplication operation, an exclusive OR is performed by using the {01} and {02} multiplication results.

Next, a mix column block device and a multiplication operation method using the same according to an embodiment of the present invention to which the above description is applied will be described in detail with reference to the accompanying drawings.

First, the configuration of the mix column block device is as follows.

3 is a hardware configuration diagram of a mix column block device according to an embodiment of the present invention.

According to FIG. 3, the mix column block device 200 includes a storage unit 210, a first multiplication operation unit 220, a second multiplication operation unit 230, and an exclusive OR operation unit 240.

The storage unit 210 stores the first input module 212, the second storage module 214, the third storage module 216, and the fourth storage byte by dividing the 32-bit input data into 8-bit units. 4 storage module 218.

)를 저장하고, 제2 저장 모듈(214)은 두번째 입력 바이트(

)를 저장하고, 제3 저장 모듈(216)은 세번째 입력 바이트(

)를 저장하고, 제4 저장 모듈(218)은 네번째 입력 바이트(

)를 저장한다.Here, the first storage module 212 is the first input byte (

), And the second storage module 214 stores the second input byte (

), And the third storage module 216 stores the third input byte (

), And the fourth storage module 218 stores the fourth input byte (

Save).

The first multiplication operation block 220 may include a first multiplication operation module 222 and a second multiplication operation module that perform {01} and {02} multiplication operations on respective input bytes output from the storage unit 210. 224, a third multiplication module 226, and a fourth multiplication module 228.

)에 대한 {01} 곱셈연산을 수행하는 {01} 곱셈연산 블록 및 {02} 곱셈연산을 수행하는 {02} 곱셈연산 블록을 포함한다. In this case, the first multiplication operation module 222 receives the first input byte (received from the first storage module 212).

{01} multiplication block for performing {01} multiplication and {02} multiplication block for performing {02} multiplication.

In this case, the {01} multiplication block is the same as the xt0_0 block shown in FIG. 3 and the {02} multiplication block is the same as the xt2_0 block.

)에 대한 {01} 곱셈연산을 수행하는 {01} 곱셈연산 블록(또는 xt0_1 블록) 및 {02} 곱셈연산을 수행하는 {02} 곱셈연산 블록(또는 xt2_1 블록)을 포함한다.The second multiplication module 224 receives a second input byte (received from the second storage module 214).

{01} multiplication block (or xt0_1 block) for performing {01} multiplication, and {02} multiplication block (or xt2_1 block) for performing {02} multiplication.

)에 대한 {01} 곱셈연산을 수행하는 {01} 곱셈연산 블록(또는 xt0_2 블록) 및 {02} 곱셈연산을 수행하는 {02} 곱셈연산 블록(또는 xt2_2 블록)을 포함한다.The third multiplication module 226 receives the third input byte (received from the third storage module 216).

{01} multiplication block (or xt0_2 block) for performing {01} multiplication, and {02} multiplication block (or xt2_2 block) for performing {02} multiplication.

)에 대한 {01} 곱셈연산을 수행하는 {01} 곱셈연산 블록(또는 xt0_3 블록) 및 {02} 곱셈연산을 수행하는 {02} 곱셈연산 블록(또는 xt2_3 블록)을 포함한 다.The fourth multiplication module 228 receives the fourth input byte (received from the fourth storage module 218).

{01} multiplication block (or xt0_3 block) for performing {01} multiplication, and {02} multiplication block (or xt2_3 block) for performing {02} multiplication.

The second multiplication operation block 230 uses the {01}, {02} multiplication operations output from the first multiplication operation block 220 to perform the {01}, {02} and {03} multiplication operations. And a fifth multiplication module 232, a sixth multiplication module 234, a seventh multiplication module 236, and an eighth multiplication module 238.

The fifth multiplication module 232 performs {01}, {02} and {03} multiplication operations using the {01} multiplication result and the {02} multiplication result received from the first multiplication calculation module 222. Multiplication blocks (or xt0_0 blocks, xt2_0 blocks, and xt3_0 blocks, respectively) to perform.

The sixth multiplication module 234 performs {01}, {02} and {03} multiplication operations using the {01} multiplication result and the {02} multiplication result received from the second multiplication module 224. Multiplication blocks (or xt0_1 blocks, xt2_1 blocks, and xt3_1 blocks, respectively).

The seventh multiplication module 236 performs {01}, {02} and {03} multiplication operations using the {01} multiplication result and the {02} multiplication result received from the third multiplication module 226. Multiplication blocks (or xt0_2 blocks, xt2_2 blocks, and xt3_2 blocks, respectively) to perform.

The eighth multiplication module 238 performs {01}, {02} and {03} multiplication operations using the {01} multiplication result and the {02} multiplication result received from the fourth multiplication module 228. Multiplication blocks (or xt0_3 blocks, xt2_3 blocks, and xt3_3 blocks, respectively) to perform.

)(242, 244, 246, 248)를 출력한다.The exclusive OR operation 240 performs an exclusive OR operation on the result of performing each of the {01}, {02}, and {03} multiplication operations received from the second multiplication operation block 230, and outputs each of the output bytes. (

) 242, 244, 246, 248.

FIG. 4 is a diagram for describing {01} and {02} multiplication operations of the first multiplication block unit 220 according to an embodiment of the present invention. In particular, the first multiplication operation module 222 is shown in detail. to be.

)를 입력받아 xt2_0 블록(222b)으로 전달하고, 제2 곱셈연산 블록부(230)의 xt0_0 블록(232a)에게 전달한다.According to FIG. 4, the xt0_0 block 222a receives the first input byte (from the first storage module 212).

) Is received and transferred to the xt2_0 block 222b and delivered to the xt0_0 block 232a of the second multiplication operation block 230.

The xt2_0 block 222b transfers the {02} multiplication operation result to the xt2_0 block 232b of the second multiplication operation block unit 230.

At this time, the xt0_0 block 222a of the first multiplication operation unit 220 and the xt0_0 block 232a of the second multiplication operation unit 230 have the same value. The xt2_0 block 222b of the first multiplication operation unit 220 and the xt2_0 block 232b of the second multiplication operation unit 230 have the same value. Thus, they can be used as common registers.

5 is a diagram illustrating in detail the configuration of a {02} multiplication block according to an embodiment of the present invention, and the configuration of the xt2_0 block, xt2_1 block, xt2_2 block, and xt2_3 block of FIG. 3 corresponds to this.

According to FIG. 5, the {02} multiplication block includes a first storage register 310, a shift register 320, a second storage register 330, an exclusive-OR operator 340, and a mux 350.

The first storage register 310 is a means for storing an input value of a byte unit and transferring it to the shift register. In this case, as shown in FIG. 3, the input value in bytes is an input byte transmitted from the {01} multiplication block.

The shift register 320 shifts the input byte received from the first storage register 310 to the left by one bit and outputs the shifted bit. This allows you to compute a multiplication value for the input byte.

The second storage register 330 stores the hexadecimal value {1D} for modulo operation and outputs it to the exclusive-OR operator 340.

The exclusive OR operator 340 receives the input byte shifted from the shift register 320 and the hexadecimal value {1D} from the second storage register 330 to perform an exclusive OR operation.

The mux 350 receives the most significant bit of the input byte stored in the first storage register 310 as a control bit and receives a value output from the shift register 320 and the exclusive OR operator 340, respectively. If the most significant bit of the input byte is '0', the value output from the shift register 320 is output. If the most significant bit is '1', the value output from the exclusive OR operator 340 is output.

FIG. 6 is a diagram for describing a {03} multiplication operation according to an embodiment of the present invention, and the configuration of the xt3_0 block, xt3_1 block, xt3_2 block, and xt3_3 block of FIG. 3 corresponds to this.

According to FIG. 6, a block performing a {03} multiplication operation completes a {03} multiplication operation by performing an exclusive OR operation on the {01} and {02} multiplication results.

That is, the xt3_0 block 232d receives the value input to the xt0_0 block 232a, that is, the {01} multiplication result and the xt2_0 block 232b, that is, the exclusive OR operation result for the {02} multiplication operation result. Output as a result of multiplication operation.

7 is a view showing in detail the configuration of the exclusive OR operation unit of the mix column block device according to an embodiment of the present invention.

According to FIG. 7, an exclusive OR operation is performed on the results of the {01}, {02}, and {03} multiplication operations of the exclusive OR operation unit 230 to output an output byte.

)에 대한 믹스컬럼전환한 값을 의미하는 제1 출력 바이트(

)를 출력하는 제1 출력부(242)는 제2 곱셈연산 블록부(230)의 xt0_2 블록, xt0_3 블록, xt2_0 블록 및 xt3_1 블록의 출력 값들에 대한 배타적 논리합 연산을 수행한 결과 값이다.First input byte (

The first output byte (meaning the mixed column transition value for)

) Is a result of performing an exclusive OR operation on the output values of the xt0_2 block, the xt0_3 block, the xt2_0 block, and the xt3_1 block of the second multiplication operation block unit 230.

)에 대한 믹스컬럼전환한 값을 의미하는 제2 출력 바이트(

)를 출력하는 제2 출력부(244)는 제2 곱셈연산 블록부(230)의 xt0_0 블록, xt0_3 블록, xt2_1 블록 및 xt3_2 블록의 출력 값들에 대한 배타적 논리합 연산을 수행한 결과 값이다.Second input byte (

Second output byte (meaning the mixed column switching value for)

) Is a result of performing an exclusive OR operation on the output values of the xt0_0 block, xt0_3 block, xt2_1 block, and xt3_2 block of the second multiplication operation block unit 230.

)에 대한 믹스컬럼전환한 값을 의미하는 제3 출력 바이트(

)를 출력하는 제3 출력부(246)는 제2 곱셈연산 블록부(230)의 xt0_0 블록, xt0_1 블록, xt2_1 블록 및 xt3_2 블록의 출력 값들에 대한 배타적 논리합 연산을 수행한 결과 값이다.Third input byte (

Third output byte (meaning the mixed column switching value for)

) Is a result of performing an exclusive OR operation on the output values of the xt0_0 block, xt0_1 block, xt2_1 block, and xt3_2 block of the second multiplication operation block 230.

)에 대한 믹스컬럼전환한 값을 의미하는 제4 출력 바이트(

)를 출력하는 제4 출력부(248)는 제2 곱셈연산 블록부(230)의 xt0_1 블록, xt0_2 블록, xt2_3 블록 및 xt3_0 블록의 출력 값들에 대한 배타적 논리합 연산을 수행한 결과 값이다.Fourth input byte (

The fourth output byte (

) Is a result of performing an exclusive OR operation on the output values of the xt0_1 block, the xt0_2 block, the xt2_3 block, and the xt3_0 block of the second multiplication operation block unit 230.

Now, the multiplication process using the above-described mixed column block apparatus will be described.

8 is a flowchart illustrating a multiplication operation of the mixed column block device according to an embodiment of the present invention.

According to FIG. 8, the mix column block device stores data input in units of bits in units of bytes (S101).

Next, hexadecimal values {01} and {02} multiplication operations are performed on the input data in units of bytes stored in the step S101 (S103).

Next, {01}, {02} and {03} multiplication operations are performed using the {01} and {02} multiplication values performed in step S103 (S105).

Next, an exclusive OR operation is performed on the {01}, {02}, and {03} multiplication values performed in step S105 (S107).

Next, the exclusive OR operation performed in the step S107 is output as input data in bytes, that is, an output byte for the input byte (S109).

9 is a flowchart illustrating a multiplication operation of the {02} multiplication unit of the mix column block device according to an embodiment of the present invention.

According to FIG. 9, when the data of a byte unit is input (S201), the {02} multiplication block shifts it 1 bit to the left (S203).

Next, an exclusive OR operation is performed on the input data shifted in the step S203 and the stored hexadecimal value {1D} (S205).

Next, a value to be output is selected from the input data shifted in the step S203 and the exclusive OR operation performed in the step S205 by using the most significant bit of the input byte input in the step S201 (S207). ).

Next, the value selected in step S207 is output (S209).

FIG. 10 is a diagram for describing a {03} multiplication process of a mix column block device according to an embodiment of the present invention in detail.

According to FIG. 10, the {03} multiplication block receives {01} multiplication values and {02} multiplication values (S301 and S303) and performs an exclusive OR operation on them (S305).

The result of performing the exclusive OR operation in step S305 is output as a result of the {03} multiplication operation (S307).

11 to 14 are views for explaining the output byte operation process of the mixed column block device according to an embodiment of the present invention.

First, FIG. 11 is a diagram illustrating a process of calculating an inverse mix column block converted output byte for a first input byte.

According to FIG. 11, the exclusive OR operation unit 240 performs a {01} multiplication operation on the third input byte, a {01} multiplication operation on the fourth input byte, and a first input byte from the second multiplication operation block unit 230. A multiplication result for {01} and a multiplication result for {03} for the second input byte are received (S401, S403, S405, and S407), and an exclusive OR operation is performed on them (S409).

The result of performing the exclusive OR operation in step S409 is output as an output byte for the first input byte (S411).

12 is a diagram illustrating a process of calculating an inverse mix column block converted output byte for a second input byte.

According to FIG. 12, the exclusive-OR operation unit 240 performs a {01} multiplication operation on the first input byte, a {01} multiplication operation on the fourth input byte, and a second input byte from the second multiplication operation block unit 230. A multiplication result for {02} and a multiplication result for {03} for the third input byte are received (S501, S503, S505, and S507) and an exclusive OR operation is performed on the multiplication result (S509).

The result of performing the exclusive OR operation in step S509 is output as an output byte for the second input byte (S511).

FIG. 13 is a diagram illustrating a process of calculating an inverse mix column block converted output byte for a third input byte.

According to FIG. 13, the exclusive OR operation unit 240 performs a {01} multiplication operation on the first input byte, a {01} multiplication operation on the second input byte, and a second input byte from the second multiplication operation block 230. A multiplication result of {02} and a {03} multiplication result of the third input byte are received (S601, S603, S605, and S607), and an exclusive OR operation is performed on them (S609).

The result of performing the exclusive OR operation in step S609 is output as an output byte for the third input byte (S611).

14 is a diagram illustrating a process of calculating an inverse mix column block converted output byte for a fourth input byte.

According to FIG. 14, the exclusive OR operation 240 performs the {01} multiplication operation on the second input byte from the second multiplication operation block unit 230, and performs the {01} multiplication operation on the third input byte. As a result, the result of performing the {02} multiplication operation on the fourth input byte and the result of performing the {03} multiplication operation on the first input byte is received (S701, S703, S705, and S707) and an exclusive OR operation is performed on them. It performs (S709).

The result of performing the exclusive OR operation in step S709 is output as an output byte for the fourth input byte (S711).

As described above, the exclusive OR operation according to the contents described with reference to FIGS. 11 to 14 is the same as that of Equation 4 below.

는 xt0_0와 같고

,

,

는 각각 xt0_1, xt0_2, xt0_3와 같고, 수학식 4의 (

) 곱셈연산 결과는 xt2_0와 같고 수학식 4의 (

), (

), (

) 곱셈연산 결과는 각각 xt2_1, xt2_2, xt2_3와 같고, 수학식 4의 (

) 곱셈연산 결과는 xt3_0와 같고 수학식 4의 (

), (

), (

) 곱셈연산 결과는 각각 xt3_1, xt3_2, xt3_3와 같다.Of equation (4)

Is equal to xt0_0

,

,

Are equal to xt0_1, xt0_2, and xt0_3, respectively,

) The multiplication result is the same as xt2_0 and

), (

), (

) The multiplication result is the same as xt2_1, xt2_2, and xt2_3, respectively.

) The multiplication result is the same as xt3_0 and

), (

), (

) The multiplication result is equal to xt3_1, xt3_2, and xt3_3, respectively.

This can be summarized as in Equation 8 below.

The embodiments of the present invention described above are not implemented only through the apparatus and the method, but may be implemented through a program for realizing a function corresponding to the configuration of the embodiment of the present invention or a recording medium on which the program is recorded. Implementation may be easily implemented by those skilled in the art from the description of the above-described embodiments.

The scope of the present invention is not limited to the above-described embodiments, but various modifications and improvements of those skilled in the art using the basic concept of the present invention as defined in the following claims are also within the scope of the present invention.

As described above, according to the exemplary embodiment of the present invention, hardware resources may be used less than that of the conventional multiplier, thereby providing an effect applicable to a small portable device.

Claims (12)

In the MixColums block device, which performs a round operation of an advanced encryption standard (AES) block cipher, A storage unit for storing input data in units of bits and outputting the stored input bytes; A first multiplication block block configured to perform a multiplication operation of {01} and {02}, which are hexadecimal values, of the input byte received from the storage unit; A second hexadecimal value {01}, {02} and {03} that are multiplied by a result of performing the {01} and {02} multiplication operations received from the first multiplication block unit; Multiplication operation block portion; And An exclusive OR operation unit configured to output an output byte for the input byte by performing an exclusive OR operation on the result of performing the {01}, {02} and {03} multiplication operations received from the second multiplication operation block unit. Mix column block device comprising a. The method of claim 1, The first multiplication operation block unit, A {01} multiplication block configured to receive the input byte from the storage and output the received byte; And A {02} multiplication block that receives a value output by the {01} multiplication block and outputs a result of performing {02} multiplication Mix column block device comprising a. The method of claim 2, The {02} multiplication block, A first storage register for storing an input value in bytes; A shift register which receives an input byte from the first storage register and shifts it by 1 bit to the left; A second storage register for storing the hexadecimal value {1D}; An exclusive OR operator which receives a value output from the shift register and a value stored in the second storage register and performs an exclusive OR operation on the input values; And A mux for selecting a value to be output from among the input values by receiving the most significant bit of the input byte received from the first storage register as a control bit and receiving a value output from the shift register and a value output from the exclusive OR operator. Mix column block device comprising a. The method of claim 3, The first multiplication operation block unit, And a multiplication module configured to perform a multiplication operation of {01} and {02} with respect to a plurality of input bytes input from the storage unit. Mix column block device. The method according to any one of claims 1 to 4, The second multiplication operation block unit, A {01} multiplication block receiving and outputting the {01} multiplication result of the first multiplication block unit; A {02} multiplication block receiving and outputting the {02} multiplication result of the first multiplication block unit; And A {03} multiplication block that receives the {01} multiplication result and the {02} multiplication result and performs an exclusive OR operation on them to output a {03} multiplication result Mix column block device comprising a. The method of claim 5, The second multiplication operation block unit, A plurality of multiplication modules comprising the {01} multiplication block, the {02} multiplication block and the {03} multiplication block, and performing the {01}, {02} and {03} multiplication operations; Mix column block device, characterized in that. The method of claim 6, The exclusive OR operation unit, Computes the output byte for the input byte that divides the input data in 32-bit units into bytes, Take the result of the {02} multiplication operation for the first input byte, the {03} multiplication result for the second input byte, the {01} multiplication result for the third input byte, and the {01} multicept operation for the fourth input byte A first output unit configured to calculate a result of performing an exclusive OR operation on these data as an output byte for the first input byte; Take the result of the {01} multiplication operation for the first input byte, the {02} multiplication result for the first input byte, the {03} multiplication result for the third input byte, and the {01} multicept operation result for the fourth input byte A second output unit configured to calculate a result of performing an exclusive OR operation on the output bytes as output bytes for the second input bytes; Take the result of the {01} multiplication operation for the first input byte, the {01} multiplication result for the second input byte, the {02} multiplication result for the third input byte, and the {03} multicept operation result for the fourth input byte. A third output unit configured to calculate a result of performing an exclusive OR operation on them as an output byte for the third input byte; And Take the result of the {03} multiplication operation for the first input byte, the {01} multiplication result for the second input byte, the {01} multiplication result for the third input byte, and the {02} multicept operation for the fourth input byte Fourth output unit for calculating the result of performing an exclusive OR operation on them as an output byte for the fourth input byte Mix column block device comprising a. In the multiplication operation of a mixed column block performing a round operation of the AES block cipher, Performing a hexadecimal value {01} and {02} multiplication on the input byte; Performing multiplication operations of hexadecimal values {01}, {02} and {03} using the results of performing the {01} and {02} multiplication operations; Performing an exclusive OR operation on the result of performing the {01}, {02}, and {03} multiplication operations; And Outputting a result of performing the exclusive OR operation as an output byte for the input byte Multiplication operation method of the mix column block comprising a. The method of claim 8, Performing the {01} and {02} multiplication operation, A {01} multiplication operation for receiving and outputting the input byte; And A {02} multiplication operation step of performing a {02} multiplication operation using the {01} multiplication operation result Multiplication operation method of the mix column block comprising a. The method of claim 9, Performing the {01}, {02} and {03} multiplication operation, A {01} multiplication operation step of receiving the {01} multiplication result and outputting the result; A {02} multiplication operation step of receiving the {02} multiplication result and outputting the result; And A {03} multiplication operation step of receiving the {01} multiplication operation result and the {02} multiplication operation result and performing an exclusive OR operation on the {03} multiplication operation Multiplication operation method of the mix column block comprising a. The method according to any one of claims 8 to 10, The {02} multiplication operation step, Outputting the input byte by one bit to the left; Performing an exclusive OR operation on the shifted output value and the hexadecimal value {1D} and outputting the result; And Selecting a value to be output from the shifted output value using the most significant bit of the input byte and the output value by performing the exclusive OR operation; Multiplication operation method of the mix column block comprising a. The method of claim 11, The performing of the exclusive OR operation may include: Computes the output byte for the input byte that divides the input data in 32-bit units into bytes, Take the result of the {02} multiplication operation for the first input byte, the {03} multiplication result for the second input byte, the {01} multiplication result for the third input byte, and the {01} multicept operation for the fourth input byte Computing the result of performing the exclusive OR operation on them as an output byte for the first input byte; Take the result of the {01} multiplication operation for the first input byte, the {02} multiplication result for the first input byte, the {03} multiplication result for the third input byte, and the {01} multicept operation result for the fourth input byte Computing the result of performing the exclusive OR operation on them as an output byte for the second input byte; Take the result of the {01} multiplication operation for the first input byte, the {01} multiplication result for the second input byte, the {02} multiplication result for the third input byte, and the {03} multicept operation result for the fourth input byte. Computing the result of performing the exclusive OR operation on them as an output byte for the third input byte; And Take the result of the {03} multiplication operation for the first input byte, the {01} multiplication result for the second input byte, the {01} multiplication result for the third input byte, and the {02} multicept operation for the fourth input byte Computing the result of performing the exclusive OR on these as an output byte for the fourth input byte. Multiplication operation method of the mix column block comprising a.

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