KR100618828B1 - Semiconductor memory devices and operating methods that are configured to output data bits at a lower rate in a test mode of operation - Google Patents

Abstract

Semiconductor devices include a memory cell array that outputs data bits in parallel at a first data rate. An output circuit outputs the data bits serially to the external terminal at the first data rate in the normal mode and serially outputs the data bits to the external terminal at a second data rate lower than the first data rate in the test mode. Accordingly, in the test mode, the memory cell array may operate at the first data rate while the output circuit may output data to the external terminal at the second data rate lower than the first data rate.

Description

Semiconductor memory devices and operating methods that are configured to output data bits at a lower rate in a test mode of operation}

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a timing diagram of operations performed by conventional DDR and SDR memory devices.

2 is a block diagram illustrating a memory device and an operating method according to an embodiment of the present invention.

3 is a block diagram illustrating a memory device and an operating method according to another exemplary embodiment of the present invention.

4 is a circuit diagram of a multiplexer used in the embodiment of FIG.

5 and 6 are timing diagrams of operations performed in the embodiments of FIGS. 3 and 4.

7 is a block diagram illustrating a memory device and an operation method according to another exemplary embodiment of the present invention.

8 is a circuit diagram of a multiplexer used in the embodiment of FIG.

9 is a circuit diagram of an output buffer used in the embodiment of FIG.

10 is a timing diagram of operations performed by the embodiments of FIGS. 7 to 9.

11 is a block diagram illustrating a memory device and an operating method according to another exemplary embodiment of the present invention.

12 is a circuit diagram of an output buffer used in the embodiment of FIG.

FIG. 13 is a timing diagram performed by the embodiments of FIGS. 11 and 12.

14 is a block diagram illustrating a memory device and an operation method according to another exemplary embodiment of the present invention.

15A and 15B are block diagrams of divider circuits used in the embodiment of FIG.

16 is a timing diagram of operations performed by the embodiments of FIGS. 14, 15A, and 15B.

17 is a flowchart of operations performed in accordance with various embodiments of the present invention.

The present invention relates to a semiconductor memory device, and more particularly to a circuit and a method for testing a semiconductor memory device.

Semiconductor memory devices are used in many applications and the most widely used memory device is DRAM. Synchronous DRAM (SDRAM) is designed to write and read data in synchronization with the rising edge or falling edge of the clock signal. In particular, dual data rate (DDR) SDRAMs operate at higher frequencies than conventional SDRAMs (called Single Data Rate (SDR) SDRAMs) by writing and reading data in response to both rising and falling edges of the clock signal. It is designed to be. The term "data rate" herein refers to the number of bits transferred by the memory device to the external input / output terminal or from the external input / output terminal to the inside of the memory device in one clock cycle.

1 is a timing diagram comparing the operation of a conventional SDR SDRAM and a conventional DDR SDRAM. These SDRAMs all have a burst length of 4 and a column address strobe (CAS) latency of 2. Therefore, as shown in FIG. 1, for an SDRAM having a BL of 4 and a CL of 2, 4-bit data Q1-Q3 are read in response to the read command R, and each bit of the data Q1-Q3 is clocked. Output is in response to the rising edge of CLK. Similarly, 4-bit data is sequentially input in response to the rising edge of the clock CLK in response to the write command (W).

In contrast, for the DDR SDRAM as shown in Fig. 1, the stored data Q0-Q3 is output from the memory device in response to the rising and falling edges of the data strobe signal DQS. The data strobe signal DQS is generated from the clock signal CLK. In addition, in response to the write command, data D0-D3 are written into the memory device in response to the rising and falling edges of the DQS, so a double data rate is obtained. Design and operation of SDRAM, including SDR SDRAM and DDR SDRAM, are well known to those skilled in the art, and thus detailed descriptions thereof are omitted herein.

Due to the high data rate, it can be difficult to test high frequency memory devices such as DDR SDRAM. In addition, testing high frequency memory devices such as DDR SDRAM using low frequency test equipment designed to test SDR SDRAM can be particularly challenging. For example, US Pat. No. 5,933,379 discloses "Method and Circuit for Testing a Semiconductor Memory Device Operating at High Frequency." As disclosed in US Pat. No. 5,933,379, a circuit for testing a semiconductor memory device includes a latency controller for controlling the latency of an external clock signal, an internal column address generator for generating a column address signal, and a mode register for generating a mode signal. do. The circuit for testing the semiconductor memory device may further include a column address decoder for decoding an output address signal of the internal column address generator, a memory cell for storing data, and data input / output of the memory cell according to an output signal of the latency controller. An input / output control unit for controlling, and a data input buffer and a data output buffer. In addition, a frequency multiplier for generating an internal clock signal having a frequency corresponding to n times the frequency of the external clock signal is further provided. By the above mentioned improvements, conventional test equipment can be used to test high frequency memory devices.

U.S. Patent 6,163,491 discloses "Synchronous semiconductor memory device which can be inspected even with low speed tester." As disclosed in US Pat. No. 6,163,491, a prefetch selector in which a synchronous semiconductor memory device receives first and second data read from first and second memory cells corresponding to even and odd addresses, respectively; Equipped. The prefetch selector sequentially outputs the first and second data to the data input / output terminal within one cycle of a clock cycle during normal operation. The prefetch selector determines whether the first data and the second data match in the test mode, and outputs the determination result to the data input / output terminal within one period of the clock period.

Finally, US Pat. No. 6,212,113 discloses a "Semiconductor memory device input circuit." US Patent 6,212,113 discloses a DDR memory device configured to be tested by a general memory test device. The DDR memory device includes a DDR input circuit, an SDR input circuit, a word line control circuit, a bit line control circuit, and a memory cell array. Normal write operations can be performed by selecting a DDR input circuit and test write operations can be performed by selecting an SDR input circuit. This configuration allows the DDR memory device to be tested with a typical SDR memory test device.

In addition, high frequency memory devices have a relatively small valid data window margin caused by manufacturing process changes, making it difficult to test high frequency memory devices such as DDR SDRAM. Therefore, although high frequency memory devices such as DDR SDRAM can be tested with high frequency test equipment for DDR SDRAM, it is difficult to test a plurality of DDR SDRAM devices in parallel.

Accordingly, an aspect of the present invention is to provide a semiconductor memory device and an operation method for outputting data bits at a lower rate in a test mode in order to extend an effective output data window in a test mode.

SUMMARY Embodiments of the present invention provide a semiconductor memory device having a memory cell array configured to output a plurality of data bits in parallel at a first data rate. An output circuit outputs the plurality of data bits serially to the external terminal at the first data rate in normal mode and serially outputs the plurality of data bits to the external terminal at a second data rate lower than the first data rate in test mode. Is configured to output.

In one embodiment, the memory cell array is responsive to a clock signal having a rising edge and a falling edge, and the first data rate is generated in response to both the rising and falling edges of the clock signal and the second data rate. Is generated in response to only one of the rising edge and the falling edge of the clock signal. In another embodiment, the memory cell array is configured to output the plurality of data bits in parallel at the first data rate onto corresponding plurality of first data lines, the output circuit corresponding in the normal mode. Output a plurality of data bits in series to the external terminal at the first data rate using a plurality of second data lines, and in the test mode, at the second data rate using the plurality of second data lines. And serially output the plurality of data bits to the external terminal.

In one embodiment, the output circuit duplicates the first portion of the plurality of data bits in the test mode to output the duplicated first portion in series to the external terminal at the second data rate and to provide the plurality of data. Duplicate a second portion of bits to output the duplicated second portion serially to the external terminal at the second data rate. In particular, in some of these embodiments, the memory cell array is configured to output the plurality of data bits in parallel at the first data rate onto corresponding plurality of first data lines, wherein the output circuit And a multiplexer for multiplexing read data on the first data lines onto second data lines, and an output buffer for serially outputting data on the second data lines to the external terminal.

In some of these embodiments the multiplexer connects each first data line to each second data line in the normal mode and each even first data line in each even mode in the first test mode of the test mode. And connect each odd first data line to each odd second data line in a second test mode of the test mode. In some embodiments, the multiplexer may include a first switch connecting each even-numbered first data line to each even-numbered second data line in the first test mode, and each odd-numbered first in the second test mode. A second switch connecting one data line to each odd second data line, and connecting each odd second data line to each neighboring even second data line in the first and second test modes An equalization circuit is provided. A mode register set may also be further provided for generating first and second test mode signals in response to a plurality of command signals and for placing the multiplexer in the first and second test modes of the test mode.

In another embodiment, the multiplexer connects each first data line to a respective second data line in the normal mode and connects each first data line to each first in the first test mode of the test mode. Connect with two data lines and in the second test mode of the test mode, cross-couple each odd and even first data lines to respective even and odd second data lines, respectively. . In these embodiments, the output buffer responds to the first internal clock signal generated in response to the rising edge of the clock signal and the second internal clock signal generated in response to the falling edge of the clock signal in the normal mode. And respond to only one of the first internal clock signal and the second internal clock signal in the first and second test modes of the test mode.

In these embodiments, the multiplexer may include: a first switch connecting each first data line to each second data line in the first test mode, and each odd and even number in the second test mode; And a second switch for cross connecting the first data line to each of the even and odd second data lines. In one embodiment, the output buffer further comprises a plurality of registers storing read data on each first data line, each associated with a pair of neighboring registers, and a first neighboring register in response to a first clock signal. A plurality of latches for latching data output from the second latch and latching data output from a second neighboring register in response to a second clock signal, and responding to the latches, wherein the first and second internal clocks are in the normal mode. And a parallel-to serial converter that responds to signals and during the first and second test modes only responds to one of the first and second internal clock signals.

In another embodiment, the output circuit is configured to respond to a first internal clock signal generated in response to a rising edge of the clock signal and a second internal clock signal generated in response to a falling edge of the clock signal in the normal mode. And in the test mode, respond to the first internal clock signal and the second internal clock signal alternately. In particular embodiments, the memory cell array outputs the plurality of data bits in parallel at the first data rate onto corresponding plurality of first data lines, and the output circuit serializes data to the external terminal. It has an output buffer to output to.

In one embodiment, the output buffer in response to the first internal clock signal generated in response to the rising edge of the clock signal and the second internal clock signal generated in response to the falling edge of the clock signal in the normal mode. In the first test mode of the test mode, only one of the first internal clock signal and the second internal clock signal is responsive, and in the second test mode of the test mode, the other of the first internal clock signal and the second internal clock signal is different. Answer only one. In one embodiment the output buffer is associated with a plurality of registers storing read data on each first data line, and a pair of neighboring registers each, the first neighboring register in response to a first clock signal. And a plurality of latches for latching the data output from the second latch and latching the data output from the second neighboring register in response to the second clock signal. And in response to the latches, in the normal mode, in response to the first and second internal clock signals, and during the first test mode, respond only to one of the first and second internal clock signals and to the second test. During the mode, a parallel-to serial converter may be further provided that responds to only one of the first and second internal clock signals.

In example embodiments, the output circuit may include a first internal clock signal generated in response to a rising edge of the clock signal and a second internal clock signal generated in response to a falling edge of the clock signal in the normal mode. And the divided first internal clock signal generated from the first internal clock signal and the divided second internal clock signal generated from the second internal clock signal in the test mode. The frequency of the divided first internal clock signal and the divided second internal clock signal is half the frequency of the first internal clock signal and the second internal clock signal, respectively.

In addition, a first division circuit for generating the divided first internal clock signal in response to the rising edge of the clock signal and the test mode selection signal, and the divided edge in response to the falling edge of the clock signal and the test mode selection signal. A second division circuit for generating a second internal clock signal may be further provided. In one embodiment, the first division circuit includes a first divider responsive to the rising edge of the clock signal and the test mode signal, and the second division circuit includes a falling edge of the clock signal and the test mode signal. And a second divider responsive to and a second delay element responsive to the second divider.

Embodiments of the present invention for achieving the above technical problem provide a method for operating a semiconductor device having a memory cell array for outputting a plurality of data bits in parallel at a first data rate. According to one embodiment, the plurality of data bits are output in series from the memory cell array to an external terminal at the first data rate in a normal mode. In the test mode, the plurality of data bits are serially output from the memory cell array to the external terminal at a second data rate lower than the first data rate.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 is a block diagram illustrating a memory device and an operating method according to an embodiment of the present invention.

As shown in FIG. 2, the memory device 200 includes a memory cell array 211 configured to output a plurality of data bits in parallel at a first data rate DR1. Since the design of the memory cell array 211 is well known to those skilled in the art, a detailed description thereof will be omitted.

Referring to FIG. 2, the output circuit 213 outputs the plurality of data bits serially to the external terminal 217 at the first data rate in the normal mode and is lower than the first data rate DR1 in the test mode. And outputs the plurality of data bits serially to the external terminal 217 at a data rate DR2. Meanwhile, it will be apparent to those skilled in the art that the plurality of memory cell arrays 211, the plurality of output circuits 213, and / or the plurality of external terminals 217 may be provided in one memory device 200.

The memory cell array 211 is configured to output a plurality of data bits in parallel at the first data rate DR1 onto the corresponding plurality of first data lines 212. Therefore, one first data line 212 is allocated to each bit output in parallel from the memory cell array 211. The output circuit 213 also outputs the plurality of data bits serially to the external terminal 217 at the first data rate in the normal mode using the corresponding plurality of second data lines 214. In mode, the plurality of data bits are serially output to the external terminal 217 at the second data rate lower than the first data rate. For example, four first data lines 212 and four second data lines 214 may be used.

3 is a block diagram illustrating a memory device and an operation method according to another exemplary embodiment of the present invention. Referring to FIG. 3, the output circuit 313 replicates a first portion of a plurality of data bits output from the memory cell array 211 in parallel, thereby exerting an external terminal at the second data rate in the test mode. 217, serially output the first portion of the plurality of data bits. The output circuit 313 also duplicates the second portion of the plurality of data bits output from the memory cell array 211 in parallel and thereby the plurality of data bits to the external terminal 217 at a second data rate in test mode. Configured to output a second portion of the serial.

In particular, as shown in FIG. 3, the memory cell array 211 is configured to output a plurality of data bits in parallel at a first data rate onto corresponding plurality of first data lines 212. In FIG. 3, the first data lines 212 are represented as RDIO_0 to RDIO_3. However, fewer or more first data lines 212 may be used. In addition, as shown in FIG. 3, the output circuit 313 is a multiplexer configured to multiplex read data on the first data lines 212 onto a corresponding plurality of second data lines DO_0 to DO_3. 313a). The output circuit 313 also has an output buffer 313b configured to serially output data on the second data lines DO_0 to DO_3 to the external terminal 217. Although only four second data lines 214 are shown in FIG. 3, fewer or more second data lines may be used.

The multiplexer 313a is configured to connect each first data line RDIO_0 to RDIO_3 to each second data line DO_0 to DO_3 in the normal mode (@NORMAL). In the first test mode (@TEST MODE1), the multiplexer 313a selects each even-numbered first data lines RDIO_0 and RDIO_2 to each even-numbered second data lines DO_0 and DO_2 and each neighboring odd number. The second data lines DO_1 and DO_3 are connected to each other. In the second test mode (@TEST MODE2), the multiplexer 313a selects each of the odd first data lines RDIO_1 and RDIO_3 and each of the odd second data lines DO_1 and DO_3 and each of the neighboring even numbers. The second data lines DO_0 and DO_2 are connected to each other. Although only two test modes have been described here, it is obvious that more test modes can be configured to be supported.

Therefore, in the normal mode, the second data lines DO_0 to DO_3 to which the first data lines RDIO_0 to RDIO_3 correspond to output data from the output buffer 313 at the first data rate corresponding to the data rate of the DDR SDRAM. ) During the first test mode, data of even-numbered first data lines RDIO_0 and RDIO_2 are copied onto even-numbered and odd-numbered second data lines DO_0-DO_3. Thus, this data is provided to the output buffer 313b in a duplicated form, thereby outputting to the external terminal 217 at a second data rate corresponding to the SDR SDRAM data rate. The second data rate is lower than the first data rate. Finally, in the second test mode, the data of the odd first data lines RDIO_1 and RDIO_3 are copied onto the odd and even second data lines DO_0-DO_3 so that the data is first data. The second data rate is lower than the rate provided to the output buffer 313b. Therefore, in the test mode, the data window of the output data DOUT of the output buffer 313b is expanded in comparison with the data window of the data read out from the memory cell array 211. Therefore, because the data window has been extended, DDR SDRAM can be tested by DDR SDRAM test equipment and / or multiple SDR SDRAM test equipment.

The mode register set (MRS) 315 generates first and second test mode signals TM1 and TM2 in response to the plurality of command signals and causing the multiplexer 313a to be placed in the first and second test modes. . The command signals include a low address strobe signal RASB, a column address strobe signal CASB, a write enable signal WEB, and address signals. Since the MRS 315 is included in the memory device 300 according to an embodiment of the present invention, testing may be performed after packaging.

4 is a circuit diagram of a multiplexer used in the embodiment of FIG. As shown in FIG. 4, the multiplexer 313a connects each of the even-numbered first data lines RDIO_0 and RDIO_2 to each of the even-numbered second data lines DO_0 and DO_2 in the first test mode TM1. The first switch 420 is configured to be. The second switch 430 is configured to connect each of the odd first data lines RDIO_1 and RDIO_3 to each of the odd second data lines DO_1 and DO_3 in the second test mode TM2. The equalization circuit 440 is configured to connect each odd second data line DO_1, DO_3 to each neighboring even second data line DO_0, DO_2 in the first and second test modes. Therefore, the first read data RDIO_0 and RDIO_2 read from the memory cell array 211 on the first data lines 212 are disposed on the second data lines 214 in response to the first test mode signal TM1. The data is transmitted as the second read data DO_0 and DO_2, respectively. At the same time, the equalization circuit 440 is activated such that each pair of even / odd second read data DO_0 / 1, DO_2 / 3 is maintained at the same level, while receiving the second test mode signal TM2. 2 switch 430 is deactivated. The odd-numbered read data RDIO_1 and RDIO_3 may also be processed similarly to the above, and thus the valid data window of the output data DOUT may be twice as large as in the normal mode. In the normal mode, the equalization circuit 440 is deactivated.

5 is a timing diagram of a normal mode and a test mode for reading data from a memory device according to the embodiments of FIGS. 3 and 4. As shown in FIG. 5, in the normal mode, the read data D0-D3 have a valid data window W1 and are transmitted to the external terminal DOUT in response to rising and falling edges of the clock signal CLK. In addition, the even-numbered and odd-numbered data DO_0 / 2 and DO_1 / 3 have an extended data window W2 in the test mode and are respectively transmitted to the external terminal DOUT in response to the rising edge of the external clock signal CLK.

6 is a detailed timing diagram illustrating operations performed by output circuits according to the embodiments of FIGS. 3-5. As illustrated in FIG. 6, the first internal clock signal CDQ_F is generated in response to the rising edge of the clock signal CLK. The second internal clock signal CDQ_S is generated in response to the falling edge of the clock signal CLK. In the normal mode, the output data D0-D3 may receive the external terminal DOUT in response to the first internal clock signal CDQ_F and the second internal clock signal CDQ_S corresponding to the rising and falling edges of the clock signal CLK. Is delivered. In the first test mode, the output data D0 and D2 are passed to the external terminal DOUT with an extended data window because the even and odd data are kept at the same level. Similar operations are provided for the output data D1 and D3 in the second test mode.

7 to 10 illustrate memory devices and operating methods according to other embodiments of the present invention. In these embodiments, the memory cell array 211 responds to a clock signal CLK having a rising edge and a falling edge. The output circuit 733 is connected to the first internal clock signal CDQ_F generated in response to the rising edge of the clock signal CLK and the second internal clock signal CDQ_S generated in response to the falling edge of the clock signal in the normal mode. Answer. However, in the test mode, the output circuit only responds to either the first internal clock signal or the second internal clock signal. Therefore, the data bits may be output at a second data rate lower than the first data rate in the test mode.

In particular in these embodiments, the output circuit 733 has a multiplexer 733a configured to connect each first data line 212 to each second data line 214 in a normal mode (@NORMAL). do. In the first test mode (@TEST MODE1), each first data line 212 is connected to each second data line 214. Finally, in the second test mode (@TEST MODE2), each of the odd-numbered and even-numbered first data lines 212 is cross-connected to each of the even-numbered and odd-numbered second data lines 214.

The output circuit 733 also includes an output buffer 733b. The output buffer 733b receives the first internal clock signal CDQ_F generated in response to the rising edge of the clock signal CLK and the second internal clock signal generated in response to the falling edge of the clock signal CLK in the normal mode. CDQ_S). In the test mode, that is, in the first and second test modes, the output buffer 733b only responds to one of the first internal clock signal CDQ_F and the second internal clock signal CDQ_S. In some embodiments, as shown in FIG. 7, the output buffer 733b responds only to the first internal clock signal CDQ_F in the test mode and the second internal clock signal CDQ_S is disabled.

7 shows how the valid data window of the output data DOUT of the output buffer 733b is extended by a predetermined value. The valid data window of the output data DOUT is set to the valid data window of the read data RDIO_0-RDIO_3 output from the memory cell array 211 by disabling the second internal clock signal CDQ_S in the test mode. Twice as much. Therefore, the output buffer 733b is not operated by the second internal clock signal CDQ_S such that the read data DO_0-DO_3 have an extended valid data window and are output to the external terminal 217.

8 is a circuit diagram of a multiplexer used in the embodiment of FIG. As shown in FIG. 8, the multiplexer 733a connects respective first data lines RDIO_0-RDIO_3 to respective second data lines DO_0-DO_3 in the normal mode and the first test mode TM1. The first switch 820 is configured to be. The second switch 830 is configured to cross connect respective odd and even first data lines to respective even and odd second data lines in the second test mode TM2. Therefore, the first read data RDIO_0-RDIO_3 on the first data lines 212 read from the memory cell array 211 responds to the first test mode signal TM1 to the second data lines 214 and DO_0-. Each to DO_3). In addition, each of the first read data RDIO_0-RDIO_3 on the first data lines 212 read from the memory cell array 211 may be adjacent to the second data lines TM2 in response to the second test mode signal TM2. Are passed to (214, DO_1 / DO_0, DO_3 / DO_2), respectively.

9 is a circuit diagram of an output buffer used in the embodiment of FIG. As shown in FIG. 9, the output buffer 733b includes a corresponding plurality of registers 910a-910d, each of which is configured to store read data on each first data line 212. . Latch 920a is associated with two neighboring registers 910a / 910b and latch 920b is associated with two neighboring registers 910c / 910d. Each latch 920a and 920b latches data output from the first neighboring registers 910a and 910c in response to the first internal clock signals 1st FCLK and 2nd FCLK, and the second internal clock signals 1st SCLK, 2nd SCLK) to latch data output from the second neighboring registers 910b and 910d. A parallel-to serial converter, which consists of a multiplexer 930, responds to latches 920a and 920b and, in the normal mode, to first and second internal clock signals. The multiplexer 930 only responds to one of the first and second internal clock signals during the first and second test modes.

More specifically, the second read data DO_0-DO_3 on the second data lines 214 are transferred to the registers 910a-910d in parallel in response to the internal clock signal INTCLK. The data DO_0 and DO_1 stored in the registers 910a and 910b are sequentially transferred to the first latch 920a in response to the occurrence of the first rising and first falling clocks 1st FCLK and 1st SCLK. On the other hand, the data DO_2 and DO_3 stored in the registers 910c and 910d are sequentially transferred to the second latch 920b in response to the occurrence of the second rising and falling clocks 2nd FCLK and 2nd SCLK in the normal mode. Delivered. Therefore, the data DO_0-DO_3 are output to the external terminal 217 in response to the first and second internal clock signals CDQ_F and CDQ_S sequentially activated in the normal mode. However, in the test mode, the data DO_0 and DO_1 stored in the two registers 910a and 910b sequentially move to the first latch 920a in response to the occurrence of the first rising and falling clocks 1st FCLK and 1st SCLK. Although only the first internal clock signal CDQ_F is activated, only the data DO_0 is transmitted to the external terminal 217 with a second data rate lower than the first data rate. In addition, even though the data DO_2 and DO_3 stored in the two registers 910c and 910d are sequentially transferred to the second latch 920b in response to the occurrence of the second rising and second falling clocks 2nd FCLK and 2nd SCLK, Only data DO_2 is transferred to external terminal 217 with a second data rate lower than the first data rate. That is, the data DO_0 is output until the next rising clock CDQ_F for the data DO_2 is input. Therefore, the valid data window is expanded.

Each of the first read data RDIO_1 and 3 is transferred to the second read data DO_0 and 2 in the second test mode TM2. Data DO_0,2 is then passed to external terminal 217 with an extended data window. Therefore, both data RDIO_1-RDIO_3 can be output to the outside in both test modes TM1 and TM2. 9 also shows a logic circuit 940 that can be used to disable the falling clock CDQ_S during the first and second test modes TM1 and TM2.

FIG. 10 is a timing diagram illustrating generation of output data during the normal mode and the test mode in the embodiments of FIGS. 7 to 9. As shown in FIG. 10, during the normal mode, the output circuit 733 responds to the falling edge of the first internal clock signal CDQ_F and the clock signal CLK generated in response to the rising edge of the clock signal CLK. In response to the generated second internal clock signal CDQ_S, a plurality of data bits D0 through D3 are serially output to the external terminal 217 at the first data rate. During the test mode, as shown in FIG. 10, the output circuit 733 responds to only one of the first internal clock signal CDQ_F and the second internal clock signal CDQ_S. Here, a case in which the first internal clock signal CDQ_F is responded to is illustrated. During the first test mode, data on even-numbered second data lines DO_0 and DO_2 are output at a second data rate lower than the first data rate. Although not shown in FIG. 10, the same operations are performed in the second test mode except that data on odd-numbered second data lines DO_1 and DO_3 are transferred to even-numbered test lines. Therefore, except that data D1 and D3 are output, the operation of the second test mode is the same as that of the first test mode.

11-13 illustrate memory devices and operating methods according to other embodiments of the present invention. In these embodiments, the output circuit may include a first internal clock signal CDQ_F and a second internal signal generated in response to a falling edge of the clock signal CLK in response to the rising edge of the clock signal CLK in the normal operation mode. Respond to the clock signal CDQ_S. The output circuit alternately responds to the first internal clock signal and the second internal clock signal in the test mode. In particular, referring to FIG. 11, the memory cell array 211 is configured to output a plurality of data bits in parallel on the corresponding plurality of first data lines 212 at a first data rate. The output circuit has an output buffer 1143 configured to output data in series to the external terminal 217.

In particular, referring to FIG. 11, the memory cell array 211 responds to a clock signal having rising edges and falling edges. The output buffer 1143 may include the first internal clock signal CDQ_F and the second internal clock signal CLK generated in response to the rising edge of the clock signal CLK during the normal mode. CDQ_S). In the first test mode TM1, the output buffer 1143 responds to only one of the first internal clock signal CDQ_F and the second internal clock signal CDQ_S. Here, a case in which the first internal clock signal CDQ_F is responded to is illustrated. In the second test mode TM2, the output buffer 1143 only responds to the other of the first internal clock signal CDQ_F and the second internal clock signal CDQ_S. Here, a case in which the second internal clock signal CDQ_S is responded to is illustrated.

Therefore, in FIG. 11, the valid data window of the output data DOUT of the output buffer 1143 may be extended by alternately disabling the first internal clock signal CDQ_F and the second internal clock signal CDQ_S in the test mode. . In some embodiments, the first internal clock signal CDQ_F is disabled in the second test mode, and the second internal clock signal CDQ_S is disabled in the first test mode. Therefore, the read data can be output with an extended window.

12 is a circuit diagram of the output buffer of FIG. As shown in FIG. 12, the output buffer 1143 has a plurality of registers 1210a-1210d configured to store read data on the first data lines. The latch 1220a is associated with two neighboring registers 1210a / 1210b and the latch 1220b is associated with two neighboring registers 1210c / 1210d. The latch 1220a is configured to latch data output from the first neighboring registers 1210a and 1210b in response to the first rising and first falling clock signals 1st FCLK and 1st SCLK. The latch 1220b is configured to latch data output from the second neighboring registers 1210c and 1210d in response to the second rising and second falling clock signals 2nd FCLK and 2nd SCLK. Parallel-to-serial converter 1230 responds to latches 1220a and 1220b in normal mode and to first and second internal clock signals CDQ_F and CDQ_S. The parallel-to-serial converter 1230 responds to only one of the first and second internal clock signals during the first test mode TM1 and to the other of the first and second internal clock signals during the second test mode TM2. Only responds. FIG. 12 shows logic circuits 1230 and 1250 configured to disable the first internal clock signal CDQ_F in the second test mode and to disable the second internal clock signal CDQ_S in the first test mode. It is.

FIG. 13 is a timing diagram performed in the embodiments of FIGS. 11 and 12. As shown in FIG. 13, in the normal mode, the output circuit responds to the first and second internal clock signals CDQ_F 'and CDQ_S'. The first internal clock signal CDQ_F or CDQ_F 'responds to the rising edge of the clock signal CLK and the second internal clock signal CDQ_S or CDQ_S' responds to the falling edge of the clock signal CLK. In the first test mode, the second internal clock signal CDQ_S 'is disabled and the output circuit responds only to the first internal clock signal CDQ_F'. In the second test mode, the output circuit only responds to the second internal clock signal CDQ_S '. Therefore, as shown in FIG. 12, the data DQ_0 and DQ_2 stored in the registers 1210a and 1210b are transferred to the latches 1220a and 1220b in response to the first and second rising clock signals 1st FCLK and 2nd FCLK. Delivered. Thereafter, the data DQ_0 is output until the next rise of the first internal clock signal CDQ_F ', which is the point at which the data DO_2 is output. In the second test mode, the odd data DO_1 and DO_3 stored in the registers 1210b and 1210d are transferred to the latches 1220a and 1220b in response to the first and second falling clock signals 1st SCLK and 2nd SCLK. Delivered. Therefore, the data DO_1 is output until the next rise of the second internal clock signal CDQ_S ', which is the point at which the data DO_3 is output. Therefore, the valid data window for odd data and even data is expanded.

14-16 are block diagrams illustrating memory devices and operating methods according to example embodiments. In these embodiments, the output circuit may include a first internal clock signal CDQ_F and a second internal signal generated in response to the falling edge of the clock signal CLK generated in response to the rising edge of the clock signal CLK in the normal mode. Respond to the clock signal CDQ_S. In the test mode, the output circuit divides the divided first internal clock signal CDQ_F ′ generated from the first internal clock signal CDQ_F and the divided second internal clock signal generated from the second internal clock signal CDQ_S. Answer (CDQ_S '). In some embodiments, the frequency of the divided first internal clock signal and the divided second internal clock signal is half the frequency of the first internal clock signal and the second internal clock signal.

In particular, as shown in FIG. 14, in some embodiments a First In First Out (FIFO) register 1460 is used to store data on the first data lines 212. The output buffer 1463 responds to the first and second internal clock signals CDQ_F and CDQ_S during the normal mode. However, during the test mode TM, the output buffer 1463 responds to the divided first internal clock signal CDQ_F 'and the divided second internal clock signal CDQ_S'. Therefore, the frequency of the clock can be divided, for example, in half in test mode.

Therefore, the valid data window of the output data DOUT of the output buffer 1463 can be extended by dividing the frequencies of the internal clock signals CDQ_F and CDQ_S in the test mode. That is, the frequencies of the internal clock signals CDQ_F and CDQ_S may be divided into low frequencies in response to the test mode signal TM. The test mode signal TM may be generated from the mode register set MRS that receives the plurality of command signals RASB, CASB, and WEB and address signals. Therefore, the data window of the output data can be expanded during the test mode.

15A and 15B are block diagrams of division circuits used to generate internal clock signals divided from internal clock signals during a test mode. In particular, as shown in FIG. 15A, the first division circuit 1500a generates the divided first internal clock signal CDQ_F ′ in response to the first internal clock signal CDQ_F and the test mode selection signal TM. It is composed. As shown in FIG. 15B, the second division circuit 1500b is configured to generate the divided second internal clock signal CDQ_S ′ in response to the second internal clock signal CDQ_S and the test mode selection signal TM. do.

In particular, as shown in FIG. 15A, in some embodiments, first divider circuit 1500a includes a first divider 1510 responsive to the rising edge of the clock signal and the test mode signal. Also, in some embodiments, the second divider 1500b includes a second divider 1520 responsive to the falling edge of the clock signal and a delay 1530 responsive to the second divider 1520. . The delay unit 1530 is provided between the divided first internal clock signal CDQ_F 'and the divided second internal clock signal CDQ_S' such that the output data is output from the external terminal 217 with an extended valid data window. It is used to increase the time interval of rising edge of.

16 is a timing diagram of operations in accordance with the embodiments of FIGS. 14, 15A, and 15B. 14, 15A, and 15B, data RDIO_0-RDIO_3 are stored in FIFO register 1460 and then transferred to output buffer 1463 in response to an internal clock signal. Thereafter, all data in the output buffer 1463 are output to the outside in response to the first and second internal clock signals CDQ_F and CDQ_S in the normal mode. In the test mode, the output buffer 1463 outputs the read data D0-D3 to the outside in response to the divided first and second internal clock signals CDQ_F 'and CDQ_S'. As a result, the valid data window can be expanded. Therefore, in the test mode, the memory cell array may operate at full speed as in the normal mode, while the output buffer may operate at half the operating speed of the memory cell array.

17 is a flowchart of operations performed in accordance with various embodiments of the present invention. These operations may be performed using any of the embodiments of FIGS. 2-16 described above. As shown in FIG. 17, when a normal mode is selected in block 1710, a plurality of data bits are output in series from a memory cell array to an external terminal at a first data rate in block 1720. When the test mode is selected in block 1730, a plurality of data bits are output from the memory cell array to the external terminal at a second data rate lower than the first data rate in block 1740. Such operations may be performed using the embodiments of FIGS. 2, 3-6, 7-10, 11-13, and / or 14-16 in accordance with various embodiments of the invention described above.

The best embodiment has been disclosed in the drawings and specification above. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the semiconductor memory device and the operating method according to the present invention can extend the effective output data window in the test mode by outputting data bits at a lower rate than the normal mode in the test mode. Therefore, there is an advantage in that accurate testing is possible when testing a semiconductor memory device.

Claims (32)

A memory cell array outputting a plurality of data bits in parallel at a first data rate; And An output for serially outputting the plurality of data bits to an external terminal at the first data rate in a normal mode and an output for serially outputting the plurality of data bits to the external terminal at a second data rate lower than the first data rate in a test mode With a circuit, The output circuit, in the test mode, replicates the first portion of the plurality of data bits to output the replicated first portion serially to the external terminal at the second data rate and to output the plurality of data bits. And duplicating the second portion and outputting the duplicated second portion in series to the external terminal at the second data rate. The memory cell array of claim 1, wherein the memory cell array responds to a clock signal having a rising edge and a falling edge, Wherein the first data rate is generated in response to both the rising edge and the falling edge of the clock signal, and the second data rate is generated in response to only one of the rising edge and the falling edge of the clock signal. . The memory cell array of claim 1, wherein the memory cell array outputs the plurality of data bits in parallel at the first data rate onto a corresponding plurality of first data lines. The output circuit outputs the plurality of data bits in series to the external terminal at the first data rate using a plurality of corresponding second data lines in the normal mode, and in the test mode, the plurality of second data lines. And outputting the plurality of data bits in series to the external terminal at the second data rate. delete The memory cell array of claim 1, wherein the memory cell array responds to a clock signal having a rising edge and a falling edge, The output circuit is configured to respond to a first internal clock signal generated in response to a rising edge of the clock signal in the normal mode and a second internal clock signal generated in response to a falling edge of the clock signal in the normal mode, and in the test mode. And responding to only one of the first internal clock signal and the second internal clock signal. The memory cell array of claim 1, wherein the memory cell array responds to a clock signal having a rising edge and a falling edge, The output circuit is configured to respond to a first internal clock signal generated in response to a rising edge of the clock signal in the normal mode and a second internal clock signal generated in response to a falling edge of the clock signal in the normal mode, and in the test mode. And an internal clock signal and an internal clock signal. The memory cell array of claim 1, wherein the memory cell array responds to a clock signal having a rising edge and a falling edge, The output circuit is configured to respond to a first internal clock signal generated in response to a rising edge of the clock signal in the normal mode and a second internal clock signal generated in response to a falling edge of the clock signal in the normal mode, and in the test mode. And a first divided internal clock signal generated from the first internal clock signal and a second divided internal clock signal generated from the second internal clock signal. The memory cell array of claim 1, wherein the memory cell array outputs the plurality of data bits in parallel at the first data rate onto a corresponding plurality of first data lines. The output circuit may include a multiplexer multiplexing read data on the first data lines onto a corresponding plurality of second data lines, and an output buffer serially outputting data on the second data lines to the external terminal. And a semiconductor device. The method of claim 8, wherein the multiplexer connects each first data line to each second data line in the normal mode, and each even first data line to each even number in the first test mode of the test mode. And connecting each odd first data line to each odd second data line in a second test mode of the test mode. A memory cell array configured to output a plurality of data bits in parallel on the corresponding plurality of first data lines at a first data rate; Outputting the plurality of data bits serially to the external terminal at the first data rate in the normal mode, and outputting the plurality of data bits to the external terminal serially at the second data rate lower than the first data rate in the test mode. And a multiplexer for multiplexing read data on the first data lines onto a corresponding plurality of second data lines, and an output buffer for serially outputting data on the second data lines to the external terminal. Circuit; And A mode register set responsive to a plurality of command signals and generating first and second test mode signals to place the multiplexer in the first and second test modes of the test mode, The multiplexer connects each first data line to each second data line in the normal mode and each even first data line to each even second data line in the first test mode of the test mode. Connect each odd first data line to each odd second data line in the second test mode of the test mode, and the multiplexer each even first data in the first test mode. A first switch connecting a line to each even second data line, a second switch connecting each odd first data line to each odd second data line in the second test mode, and the first switch In the first and second test modes, connect each odd second data line to each neighboring even second data line. A semiconductor device comprising the equalization circuit. The method of claim 9, And a mode register set responsive to a plurality of command signals and generating first and second test mode signals for placing said multiplexer in said first and second test modes of said test mode. Device. A memory cell array configured to output a plurality of data bits in parallel on the corresponding plurality of first data lines at a first data rate; Outputting the plurality of data bits serially to the external terminal at the first data rate in the normal mode, and outputting the plurality of data bits to the external terminal serially at the second data rate lower than the first data rate in the test mode. And a multiplexer for multiplexing read data on the first data lines onto a corresponding plurality of second data lines, and an output buffer for serially outputting data on the second data lines to the external terminal. Circuit; And A mode register set for generating a first and second test mode signals in response to a plurality of command signals and for placing the multiplexer in the first and second test modes of the test mode, The multiplexer connects each first data line to each second data line in the normal mode, and connects each first data line to each second data line in the first test mode of the test mode. And in the second test mode of the test mode, cross-couple each odd-numbered and even-numbered first data line to each even-numbered and odd-numbered second data line. The memory cell array of claim 12, wherein the memory cell array is responsive to a clock signal having a rising edge and a falling edge. The output buffer in response to the first internal clock signal generated in response to the rising edge of the clock signal and the second internal clock signal generated in response to the falling edge of the clock signal in the normal mode and the first mode of the test mode. And in the first and second test modes, respond to only one of the first internal clock signal and the second internal clock signal. The method of claim 12, wherein the multiplexer, A first switch connecting each first data line to each second data line in the first test mode; And And a second switch for cross-connecting each odd-numbered and even-numbered first data line to each even-numbered and odd-numbered second data line in the second test mode. The method of claim 13, wherein the output buffer, A plurality of registers for storing read data on each first data line; A plurality of latches each associated with a pair of neighboring registers, latching data output from the first neighboring register in response to the first clock signal and latching data output from the second neighboring register in response to the second clock signal field; And In response to the latches, responding to the first and second internal clock signals in the normal mode and responding to only one of the first and second internal clock signals during the first and second test modes. A semiconductor device comprising a parallel-to serial converter. The memory cell array of claim 1, wherein the memory cell array outputs the plurality of data bits in parallel at the first data rate onto a corresponding plurality of first data lines. And the output circuit comprises an output buffer for serially outputting data to the external terminal. 17. The memory cell of claim 16, wherein the memory cell array is responsive to a clock signal having a rising edge and a falling edge, The output circuit is configured to respond to a first internal clock signal generated in response to a rising edge of the clock signal and a second internal clock signal generated in response to a falling edge of the clock signal in the normal mode, and to generate a first test signal in the test mode. In a test mode, only one of the first internal clock signal and the second internal clock signal may be responded to, and in the second test mode of the test mode, only one of the first internal clock signal and the second internal clock signal may be responded to. A semiconductor device. The method of claim 17, wherein the output buffer, A plurality of registers for storing read data on each first data line; A plurality of latches each associated with a pair of neighboring registers, latching data output from the first neighboring register in response to the first clock signal and latching data output from the second neighboring register in response to the second clock signal field; And In response to the latches, in the normal mode, in response to the first and second internal clock signals, and in response to only one of the first and second internal clock signals during the first test mode; And a parallel-to serial converter which responds only to the other one of said first and second internal clock signals. The method of claim 17, And a mode register set for generating first and second test mode signals in response to a plurality of command signals and for placing the output buffer in the first and second test modes of the test mode. Semiconductor device. 17. The memory cell of claim 16, wherein the memory cell array is responsive to a clock signal having a rising edge and a falling edge, The output buffer is divided in the test mode in response to the first internal clock signal generated in response to the rising edge of the clock signal and the second internal clock signal generated in response to the falling edge of the clock signal in the normal mode. And responding to the first internal clock signal and the divided second internal clock signal. The semiconductor of claim 20, wherein a frequency of the divided first internal clock signal and the divided second internal clock signal is half of a frequency of the first internal clock signal and the second internal clock signal, respectively. Device. The method of claim 20, And a mode register set responsive to a plurality of command signals and generating a test mode signal for placing said output buffer in said test mode. The method of claim 20, A first division circuit configured to generate the divided first internal clock signals in response to a rising edge of the clock signal and a test mode selection signal; And And a second division circuit configured to generate the divided second internal clock signal in response to a falling edge of the clock signal and the test mode selection signal. 24. The method of claim 23, wherein the first division circuit includes a first divider responsive to the rising edge of the clock signal and the test mode signal, And the second division circuit includes a second divider responsive to the falling edge of the clock signal and the test mode signal, and a second delay element responsive to the second divider. A method of operating a semiconductor device having a memory cell array that outputs a plurality of data bits in parallel at a first data rate, the method comprising: Outputting the plurality of data bits serially from the memory cell array to an external terminal at the first data rate in a normal mode; And In the test mode, outputting the plurality of data bits in series from the memory cell array to the external terminal at a second data rate lower than the first data rate; In the test mode, outputting the plurality of data bits in series may include: Replicating a first portion of the plurality of data bits output from the memory cell array in parallel and outputting the duplicated first portion serially to the external terminal at the second data rate; And Duplicating a second portion of the plurality of data bits and outputting the duplicated second portion serially to the external terminal at the second data rate. 26. The method of claim 25, wherein outputting the plurality of data bits in series in the normal mode comprises: responsive to rising and falling edges of a clock signal from the memory cell array at the first data rate in the normal mode. Outputting the plurality of data bits in series to an external terminal, The outputting of the plurality of data bits in series in the test mode may include: in response to only one of the rising edge and the falling edge of the clock signal, the memory at the second data rate lower than the first data rate in the test mode. And outputting the plurality of data bits in series from a cell array to the external terminal. delete 27. The memory cell of claim 25, wherein the memory cell array is responsive to a clock signal having a rising edge and a falling edge, The outputting of the plurality of data bits in series in the normal mode may include a first internal clock signal generated in response to a rising edge of the clock signal and a second internal clock signal generated in response to a falling edge of the clock signal. In response, outputting the plurality of data bits in series from the memory cell array to the external terminal at the first data rate; The outputting of the plurality of data bits in series in the test mode may include: responsive to only one of the first internal clock signal and the second internal clock signal, at the second data rate lower than the first data rate. Outputting the plurality of data bits in series from a cell array to the external terminal. 27. The memory cell of claim 25, wherein the memory cell array is responsive to a clock signal having a rising edge and a falling edge, The outputting of the plurality of data bits in series in the normal mode may include a first internal clock signal generated in response to a rising edge of the clock signal and a second internal clock signal generated in response to a falling edge of the clock signal. In response, outputting the plurality of data bits in series from the memory cell array to the external terminal at the first data rate; The outputting of the plurality of data bits in series in the test mode may include alternately responding to the first internal clock signal and the second internal clock signal, and the memory at the second data rate lower than the first data rate. Outputting the plurality of data bits in series from a cell array to the external terminal. 27. The memory cell of claim 25, wherein the memory cell array is responsive to a clock signal having a rising edge and a falling edge, The outputting of the plurality of data bits in series in the normal mode may include a first internal clock signal generated in response to a rising edge of the clock signal and a second internal clock signal generated in response to a falling edge of the clock signal. In response, outputting the plurality of data bits in series from the memory cell array to the external terminal at the first data rate; In the test mode, outputting the plurality of data bits in series may include: a divided first internal clock signal generated from the first internal clock signal and a divided second internal clock signal generated from the second internal clock signal. In response, outputting the plurality of data bits in series from the memory cell array to the external terminal at the second data rate lower than the first data rate. 27. The memory device of claim 25, wherein the memory cell array outputs the plurality of data bits in parallel at the first data rate onto corresponding plurality of first data lines and the data on the plurality of first data lines correspond to each other. Transferred onto a plurality of second data lines, Outputting the plurality of data bits serially in the normal mode comprises connecting each first data line to each second data line in the normal mode, In the test mode, outputting the plurality of data bits in series may include connecting each even-numbered first data line to each even-numbered second data line in the first test mode of the test mode, and Connecting each odd first data line to each odd second data line in a second test mode of the test mode. 27. The memory device of claim 25, wherein the memory cell array outputs the plurality of data bits in parallel at the first data rate onto corresponding plurality of first data lines and the data on the plurality of first data lines correspond to each other. Transferred onto a plurality of second data lines, Outputting the plurality of data bits serially in the normal mode comprises connecting each first data line to each second data line in the normal mode, Outputting the plurality of data bits serially in the test mode comprises connecting each first data line to a respective second data line in a first test mode of the test mode, and Connecting each odd-numbered and even-numbered first data line to each even-numbered and odd-numbered second data line in a two-test mode.

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