KR100438808B1 - Operator for processing digital signal with low power consumption by using probability distribution of input digital signals - Google Patents

Abstract

PURPOSE: An operator for processing a digital signal with low power consumption by using probability distribution of input digital signals is provided to output a previously calculated value in case of a predetermined signal by detecting that the input digital signal is the specified signal having a high probability after analyzing the digital input signal. CONSTITUTION: An external input part(10) receives and temporarily stores the digital data. A specified signal detector(12) detects the specified signal by receiving the digital data output from the external input part and outputs a detection result. An internal input part(14) outputs the digital data inputted by responding to the detection result. An operation part(16) receives/operates the data output from the internal input part. An external output part(18) selectively outputs the temporarily stored output of the operation tool or a value corresponding to the specified input as an operation result of the digital data by responding to the detection result.

Description

Low Power Consumption Unit for Digital Signal Processing

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computing device, and more particularly, to a low power consumption computing device for digital signal processing which reduces power consumption by using a probability distribution of an input digital signal in the field of digital signal processing.

In the age of multimedia, power consumption has become a very important item in the field of digital signal processing. This is also important for heat generation and system stability. And many systems grow in size, with hundreds of multipliers. In addition, due to the mobility and portability of electronic devices, such digital signal processing systems are required to operate at a low power consumption and to be used longer with a single battery. In places such as mobile communication, low power consumption is more important than anything.

Conventionally, arithmetic units store a digital input in response to a clock signal and calculate it randomly. However, since it does not consider the probability distribution of the digital input signal at all, in some systems where a specific digital input pattern is used very often, power is wasted by performing the same operation for the same input every time, and the operation execution speed is slowed. There was this.

In addition, since a conventional computing device uses a synchronization circuit for synchronizing the input and output parts, if the input changes when the computing device does not need to operate, a part of the input circuit operates to consume power without need. There is a problem. The synchronization circuit will be described later in more detail.

The technical problem to be achieved by the present invention is a low power consumption computing device for digital signal processing by analyzing the digital input signal to be calculated to detect whether a specific signal having a high probability frequency, and outputs a pre-calculated value in the case of a specific signal To provide.

Another object of the present invention is to provide a low power consumption type computing device for digital signal processing having a pipeline structure.

1 is a block diagram of a computing device according to the present invention.

2 is a circuit diagram of a conventional external input unit.

3 is a circuit diagram of a preferred embodiment of the external input unit according to the present invention.

4 is a block diagram of a computing device according to the present invention having a two-stage pipeline structure.

5 is a circuit diagram of a conventional pipelined 16-bit multiplier used for IDCT.

6 is a circuit diagram of a preferred embodiment of a low power consumption type computing device according to the present invention for performing multiplication.

7 is a block diagram of a preferred embodiment of the present invention of a low power consumption type computing device using an asynchronous specific signal detector.

FIG. 8 is a circuit diagram of a preferred embodiment according to the present invention of the X-th specific signal detecting unit shown in FIG. 7.

FIG. 9 is a circuit diagram of a preferred embodiment of the present invention of the external output shown in FIG. 1 or 7 used for inverse quantization of ADPCM.

FIG. 10 is a diagram illustrating probability distributions of input values, output values, and input values of an inverse quantizer for an ADPCM.

In order to achieve the above object, a low power consumption type computing device for digital signal processing according to the present invention includes an external input means for inputting and temporarily storing digital data and outputting a stored signal, and the digital data output from the external input means. A specific signal sensing means for detecting a specific input by inputting a and outputting a detected result, an internal input means for outputting the digital data input in response to the detected result from the external input means, and the internal input; Arithmetic means for inputting and calculating data output from the means and output of the temporarily stored arithmetic means, or selectively outputting a value corresponding to the specific input as a calculated result of the digital data in response to the detected result It is preferable that it is comprised by the external output means.

In order to achieve the above object, a low power consumption type computing device for digital signal processing according to the present invention includes an external input means for inputting and temporarily storing digital data and outputting a stored signal, and the digital output from the external input means. Specific signal sensing means for inputting data to detect a specific input and outputting a detected result, first internal input means for outputting the digital data input in response to the detected result from the external input means; First calculation means for inputting and calculating data output from the first internal input means, first delay means for outputting the sensed result after a delay, and second to N (where N is a positive integer of 2 or more) ) Data input from internal input means, second to N delay means, second to N calculation means and the Nth calculation means, And an external output means for selectively outputting a value corresponding to a predetermined input to the calculated result value of the digital data in response to the output of the N-th delay means, wherein the N-th internal input means is N-1 operations. Outputting the input data in response to the output of the N-th delay means from the means, the N-th calculating means inputs and outputs data output from the N-th internal input means, and the N-th delay means is the N-th delay means. It is preferable to output the output of one delay means after a delay.

Hereinafter, the configuration and operation of a low power consumption type computing device for digital signal processing according to the present invention will be described with reference to the accompanying drawings.

1 is a block diagram of an arithmetic device according to the present invention, and includes an external input unit 10, a specific signal detection unit 12, an internal input unit 14, an operation unit 16, and an external output unit 18.

The external input unit 10 shown in FIG. 1 inputs and temporarily stores digital data through the input terminal IN, and outputs the stored signals to the specific signal detection unit 12 and the internal input unit 14. The specific signal detector 12 detects whether the digital data input from the external input unit 10 is a specific input, and outputs the detected result as a control signal of the internal input unit 14 and the external output unit 18. The internal input unit 14 outputs the input digital data to the operation unit 16 in response to the result detected by the external input unit 10 or maintains the previous output value. That is, the value of the data output to the calculator 16 by the internal input unit 14 changes in response to the detected result.

The calculation unit 16 calculates data input from the internal input unit 14, and outputs the calculated value to the external output unit 18. The external output unit 18 outputs a calculated value input from the calculator 16 or a pre-computed value corresponding to a specific input in response to the detected result and optionally through the output terminal OUT as a calculated result of digital data. Output

For example, many matrix multiplications are performed in the Inverse Discrete Consine Transform (IDCT) in the field of video signal reproduction such as a moving picture expert group (MPEG). Here, many operations are multiplied by '0', and if the operation is performed using a conventional multiplier, many circuit nodes perform an operation, which causes a lot of power consumption.

However, a case where such a multiplication operation is performed by the computing device according to the present invention will be described as follows.

The specific signal detector 12 shown in FIG. 1 inputs data temporarily stored in the external input unit 10 through the input terminal 1N to input a specific input (for example, in the case of IDCT, the specific input is '0'). If it is a specific input, the internal input unit 14 is controlled so that the data output from the internal input unit 14 to the calculation unit 16 is not changed, and a pre-calculated result value corresponding to the specific input is output. The external output unit 18 is controlled to be output through the terminal OUT. Therefore, there is no dynamic power consumption at the calculating section 16 at all.

In the case of MPEG, when looking at the input of IDCT, more than 30% has a specific input '0' and in many cases 50%, the power consumption can be considerably reduced by using the computing device according to the present invention. have. For example, since the value of the signal lines in the calculator 16 does not change, it is possible to considerably reduce power consumption when the calculator 16 is configured in CMOS. This is because the power consumption of the CMOS circuit is most of the dynamic power consumption that occurs when the value of the signal changes. In addition, by detecting a specific input to generate a corresponding output quickly, the average performance of the system is improved.

2 is a circuit diagram of a conventional external input unit 10. In the related art, digital data is input through the input terminal IN using a synchronous method. That is, the MUX 20 selectively outputs the data input through the input terminal IN and the output of the D flip-flop 22 in response to an enable signal ENABLE enabled at a "high" logic level when a calculation is required. And a D flip-flop that clocks the clock signal CLOCK, inputs the signal output from the MUX 20, and inputs the data D to output the positive output Q to the MUX 20 and the corresponding unit through the output terminal OUT. 22).

Therefore, even when the operation is not actually required, that is, when the enable signal ENABLE is at a "low" logic level, power consumption occurs because the clock changes values of several nodes. In addition, the capacitance of the input portion by the MUX 20 increases, resulting in increased power consumption.

FIG. 3 is a circuit diagram of a preferred embodiment of the external input unit 10 according to the present invention. When an operation is required, a logic product of an enable signal ENABLE and a clock signal CLOCK, which are enabled at a "high" logic level, is output. The input signal of the AND gate 40 and the AND gate 40 is clocked, the digital data input through the input terminal IN is inputted, and the constant output Q is output to the specific signal detection unit 12 through the output terminal OUT. And a D flip-flop 42 which outputs to the internal input unit 14.

When the external input unit 10 adopting the gated clock method shown in FIG. 3 is used, the clock signal of the D flip-flop 42 is always input only when the enable signal ENABLE is '1'. As a result, the current flows less at the time when no operation is required, thereby reducing power consumption and reducing the size of the circuit since the MUX 20 is not required.

Hereinafter, with reference to the accompanying drawings, the operation and configuration of a low power consumption type computing device having a two-stage pipeline structure according to the present invention will be described as follows.

4 is a block diagram of a computing device according to the present invention having a two-stage pipeline structure, wherein the external input unit 60, the specific signal detection unit 62, the first internal input unit 64, the first operation unit 66, The first delay unit 68, the second internal input unit 70, the second operation unit 72, the second delay unit 74 and the external output unit 76.

The external input unit 60 shown in FIG. 4 inputs and temporarily stores digital data through the input terminal IN, and outputs the stored signal to the specific signal detection unit 62 and the first internal input unit 64. The specific signal detection unit 62 performs the same operation as the specific signal detection unit 12 shown in FIG. 1, inputs digital data output from the external input unit 60, and detects whether the specific signal is input. Is output to the first internal input unit 64 and the first delay unit 68.

The first internal input unit 64 outputs the input digital data to the first operation unit 66 in response to the result detected by the external input unit 60, and the first operation unit 66 from the first internal input unit 64. Performs a function of inputting and outputting data.

Meanwhile, the first delay unit 68 outputs the detected result to the second internal input unit 70 and the second delay unit 74 after a delay by a predetermined clock period, and the second delay unit 74 receives the first delay. The detected result delayed by the predetermined clock period by the unit 68 is again outputted to the external output unit 76 after the delayed by the predetermined clock period. At this time, the delay time by the predetermined clock period of each delay unit should be at least greater than the computation time of each operation unit.

The second internal input unit 70 outputs data calculated by the first operation unit 66 input in response to the output of the first delay unit 68 to the second operation unit 72, and the second operation unit 72 The input data is calculated and output to the external output unit 76.

The external output unit 76 performs the same operation as the external output unit 18 shown in FIG. That is, in response to the detected data delayed by the second delay unit 74 by a predetermined clock period, the data input from the second operation unit 72 or the value corresponding to the specific input may be selectively calculated as the calculated result value of the digital data. Output through output terminal OUT.

In the above, the low power consumption computing device having a two-stage pipeline structure has been described, but the low power consumption computing device according to the present invention may be implemented in a multi-stage pipeline structure. For example, a low power consumption computing device having a three-stage pipeline structure includes a third internal input unit (not shown) and a third operation unit (not shown) connected in series between the second operation unit 72 and the external output unit 76. The third delay unit may be connected between the second delay unit 74 and the external output unit 76.

FIG. 5 is a circuit diagram of a conventional pipeline 16-bit multiplier used in IDCT and has a four-stage pipeline structure. The multiplexers and multiple D flip-flops constituting the input unit 80 and the operation unit 84 are shown in FIG. , A plurality of D flip-flops constituting the output unit 86 and five flip-flops constituting the state signal generator 88.

The multiplier shown in FIG. 5 functions to multiply the data input through the input terminals INA and INB and output the result through the output terminal OUT1. To this end, each multiplexer of the input unit 80 selectively outputs data input through the input terminal INA or INB and data input from the corresponding D flip-flop to the corresponding D flip-flop in response to the ENABLE signal. The input unit 80 inputs data and outputs the data to the operation unit 84, and the operation unit 84 multiplies the data input from the input unit 80. The multiplied data is output to the corresponding flip-flop of the output unit 86, and the data stored in the flip-flop is output through the output terminal OUT1. At this time, the state signal generating unit 88 outputs a state signal indicating whether the data output through the output terminal OUT1 is the calculated final result value through the output terminal OUT2.

FIG. 6 is a circuit diagram of a preferred embodiment of a low power consumption computing device according to the present invention for performing multiplication, and has a four-stage pipeline structure and includes a plurality of flip-flops and gates constituting an external input unit 100. A calculation unit including gates and flip-flops, first, second, third and fourth delay means 103, 104, 106 and 110 constituting the specific signal detector 102, and an internal input unit (not shown) 108 and the flip-flops and the gates constituting the external output 112. Here, the calculation unit 108 includes at least one internal input unit and as many calculators. In addition, the type of register used flip-flop rather than latch. In addition, the number of stages was set to 4 to operate at the maximum 100MHz or more.

The computing device shown in FIG. 6 is a pipeline multiplier for detecting a specific input '0', and if any operand of two data input to the external input unit 100 is '0', the multiplication result is '0'. do. When the enable signal ENABLE and the clock signal CLOCK are both '1', the external input unit 100 inputs two numbers to be multiplied through the input terminals INA and INB, respectively. If any one of the two inputted data is '0', the specific signal detector 102 outputs a control signal having a "low" logic level to an internal input unit (not shown) of the calculator 108 so that the operator does not operate. do. In the calculator 108, since the input value of the calculator does not change, the calculator will not operate, and as a result, the power consumption will be reduced. In the external output 112, the output signal '0' for a specific input is output terminal OUT1. Is output via For this purpose, as shown in FIG. 6, the output of the specific signal detecting unit 102 is connected to the reset terminal of the corresponding flip-flop of the external output unit 112.

On the other hand, a valid signal indicating whether or not the signal output through the output terminal OUT1 is a valid signal is output through the output terminal OUT2. Unlike the arithmetic device shown in FIG. 5, the arithmetic device shown in FIG. 6 uses a gated clock and has a specific signal detector 102 that detects a specific input '0'.

When the configuration and operation of the internal arithmetic units of the arithmetic unit shown in FIG. 5 and the internal arithmetic units of the arithmetic unit shown in FIG. 6 are the same, comparing the two arithmetic units, the circuit size is larger than that of the arithmetic unit shown in FIG. There are few arithmetic units according to the present invention shown in FIG. 6 because the multiplexer portion of the input portion is simplified by adopting a gated clock scheme. In addition, if the two multipliers are compared for each of the four cases where data is input as follows,

Case 1. When there is no '0' in two input data, the conventional computing device or the computing device according to the present invention operates in the same manner, and the power consumption is similar. That is, the computing device performing the multiplication function according to the present invention shows a slight power increase of about 2% in the control part. However, this is negligible, and in general, rarely '0' is never input in IDCT.

Case 2. If none of the two input data is '0', but the operation is required or not required, the computational device according to the present invention uses a gated clock method, which reduces the power consumption by about 15%. There was. This is a case where the computing device operates about 80%, but in most cases the operating time of the computing device is less than 10% compared to the system operating time. Therefore, higher power consumption reduction can be expected in practical cases.

Case 3. When the probability that at least one of the two input data is '0' is 100%, the power consumption of the computing device according to the present invention is reduced by about 80% compared to the conventional computing device. That is, when at least one of the two input data is '0', it is shown that the power consumption of 80% can be reduced as compared with otherwise.

Case 4. When the probability that at least one of the two input data is '0' is about 26%, the computing device according to the present invention has a power consumption reduction of about 26%. In case 3, multiplying 80% by 26% is expected to reduce power consumption by about 20%, but the power consumption is reduced by 26% due to the gated clock method of the input.

The reduction in power consumption described above is expected to decrease even more when considering that 40% of the input data is '0' in the case of an IDCT in an MPEG or other image compression application field.

Applicant compared the computing device shown in FIG. 5 with the computing device shown in FIG. 6 as shown in Table 1 under the following conditions.

As a condition, the computing devices used were a 16-bit × 16-bit multiplier with a four-stage pipeline structure, a simulation frequency of 50 MHz, an operating condition of 5 volts, and a design library using TGC2000 (Texas Instrument 0.65 μm CMOS GateArray). The method adopted the gate level simulation method.

division Conventional multiplier Multiplier of the Invention Remarks Gates 4630 4559 98.47% Power consumption (case 1) 114.9298 yen 117.2804㎽ 102.06% Power consumption (case 2) 102.1868㎽ 87.1953㎽ 85.33% Power consumption (case 3) 64.4483 yen 13.4930 yen 20.94% Power consumption (case 4) 93.7079㎽ 69.7808㎽ 74.47%

Here, remarks represent the percentage obtained by dividing the corresponding value of the computing device of the present invention by the corresponding value of the conventional computing device.

Meanwhile, the specific signal detector 12 illustrated in FIG. 1 may detect whether the digital input signal input from the external input unit 10 is a specific signal by using a self-timed method as follows.

FIG. 7 is a block diagram of a preferred embodiment of the present invention of a low power consumption type computing device using an asynchronous specific signal detector, comprising: an external input 140 comprising an AND gate 160 and a D flip-flop 162; The specific signal detecting unit 142, the internal input unit 144, and the calculating unit 146 including the first to N-th sub-specific signal detecting units 164, 166,..., And 170 and the AND gate 168. And an external output unit 148 and an AND gate 150.

The external input unit 140 shown in FIG. 7 is a collection of circuits shown in FIG. That is, the AND gate 160 corresponding to the AND gate 40 and the D flip-flop 162 corresponding to the D flip-flop 42 are used to input digital data by a gated method.

X (1≤X≤N) sub-specific signal detection unit of the first to Nth (where N is an integer greater than or equal to 1) sub-specific signal detection units 164, ... 166 of the specific signal detection unit 142. In response to the output of the AND gate 160, the digital data inputted from the external input unit 140 is logically combined corresponding to the corresponding specific input among the N specific input (s), and the results of the logical combination X are obtained. The detection result Ax and the X-th detection end signal Cx are output. Herein, the X-th detected result indicates whether the sensed digital data is a specific signal. If the detected digital data is not a specific signal, the result is '1' and has a value of '0' when the detection or the end of detection is not performed. The X-th detection end signal indicates whether the sensing of whether the digital data is a specific signal has ended.

At this time, the first to Nth detected results output from the first to Nth specific signal detection units 164,..., And 166 are output to the external output unit 148. Meanwhile, the AND gate 168 ANDs the first to N-th sensing termination signals, and outputs the result of the AND to the N + 1 sub-specific signal detecting unit 170. The N + 1th sub-signal detecting unit 170 logically combines the first through Nth sensed results in response to the output of the AND gate 168, and generates the N + 1th sensed result of the logic combination. The result is output to the internal input unit 144 and the external output unit 148 as the result A _{N + 1} . At this time, the internal input unit 144 inputs the digital data output from the external input unit 140 in response to the N + 1 detected result A _{N + 1} , and outputs the input data to the operation unit 146. . Therefore, it is possible to prevent the internal input unit 14 from receiving the digital data from the external input unit 10 in a situation in which the result detected by the specific signal detection unit 12 due to a malfunction is incorrectly output.

On the other hand, the external output unit 148 detects the results A1, ... A _N and A _{N + 1 that} are calculated by the operation unit 146 or the first to N + 1th detection values corresponding to a specific input. Outputs selectively through the output terminal OUT.

As described above, when there are a plurality of specific signals to be sensed and the calculation values for each of the plurality of specific signals are all different, the plurality of sub-specific signals are detected by the specific signal detector 142 as shown in FIG. 7. There are wealth. However, even if there are a plurality of specific signals to be detected, if the operation values for the plurality of specific signals are the same or if there is only one specific signal to be detected, there is only one sub-specific signal detection unit in the specific signal detection unit 142. At this time, one sub-specific signal detection unit detects the result of the logical combination of the digital data input from the external input unit 140 corresponding to the specific input in an asynchronous manner in response to the output of the AND gate 160. As a result, it is output to the internal input unit 144 and the external output unit 148.

FIG. 8 is a circuit diagram of an exemplary embodiment according to the present invention of the X-th specific signal detecting unit shown in FIG. 7, wherein the PMOS transistors P1 and P2, the NMOS transistor N1, the NAND gate 188, the first and A differential series voltage switch logic (DCVSL) 180 and an AND gate 182 constituted of the second logic combination units 184 and 186.

DCVSL illustrated in FIG. 8 is described on pages 26 to 28 of a book published under the title 'SYNCHRONIZATION DESIGN FOR DIGITAL SYSTEMS' by 'Teresa H. Meng' of Stanford University.

That is, the PMOS transistors P1 and P2 shown in FIG. 8 are turned on / off in response to the enable signal ENA, which is an output of the AND gate 160 shown in FIG. 7, and the NMOS transistor N1 is initially initialized. It is turned on / off when the PMOS transistors P1 and P2 are turned on / off in response to an enable signal ENA input at a “low” logic level in the state. The NAND gate 188 inverts ANDs the outputs of the first and second logic combination units 184 and 186, and outputs the result of the inversion AND operation as the X sense termination signal Cx. The AND gate 182 logically multiplies the output of the first logic combiner 184 by the output of the second logic combiner 186 and outputs the result of the X sensed result Ax. Meanwhile, the first and second logic combination units 184 and 186 are enabled in response to the enable signal ENA, so that n-bit digital data Dn. Output from the external input unit 140 shown in FIG. 7 is output. ..D ₁ ) is combined according to the specific signal and outputs the result of logical combination. Here, the logical combination results of the first logical combination unit 184 and the second logical combination unit 186 are in complementary relation with each other.

Meanwhile, the external output unit 18 or 148 illustrated in FIG. 1 or 7 may output a value calculated in advance under the control of the specific signal detector 12 or 142, or may be calculated by inputting from the calculation unit 16 or 146. In order to output the value in response to the sensed result, flip-flops that are set or reset asynchronously are used as in the example described below.

For example, assuming that the apparatus shown in FIG. 7 is used for an inverse quantizer of adaptive differential pulse code modulation (ADPCM), the operation of the computing device according to the present invention will be described as follows. Explain together.

FIG. 9 is a circuit diagram of a preferred embodiment of the present invention of the external output unit 18 or 148 shown in FIG. 1 or FIG. 7 used in the inverse quantization unit of the ADPCM. The logical product 190 and the first through P ( Where P is the number of bits of the arithmetic value for a particular input) flip-flops 192, 194, ..., 196, 198, 200 and 202.

10 is a diagram illustrating probability distributions of input / output values and input values of an inverse quantization unit (not shown) for ADPCM, where I represents an input value, and DQS and DQLN are differential quantization code bits (DQS: sign) as output values. a bit of quantized difference signal and a normalized quantized difference signal (DQLN).

I shown in FIG. 10 is a signal output from an adaptive quantizer of ADPCM, and DQS and DQLN are signals output from an adaptive predictor of ADPCM. Here, the DQS can be directly obtained from the most significant bit of the input I, and the DQLN can be obtained using the arithmetic unit shown in FIG. To this end, the specific signal detector 142 of the computing device illustrated in FIG. 7 detects whether digital data '0001', '1110', and '1111' having a high probability frequency are input among the digital inputs I. At this time, since the calculation value of the specific signal '0001' or '1110' is the same, it is detected by one sub-specific signal detection unit. That is, in order to detect whether the digital data input from the external input unit 140 is '0001' or '1110', the first sub-specific signal detecting unit 164 performs a logical operation as shown in Equation 1 shown in FIG. 8. Perform asynchronously with the circuit.

f1 = a'b'c'd + abcd '

Here, f1 is a logical combination expression of the first sub-signal detection unit 164, and is performed in the first logical combination unit 184 shown in FIG. 8, where abcd represents each bit of the input I, and ' Indicates. F1 is '1' if the digital data is a specific signal, or '0'. In addition, the first detected result A1 becomes '1' if it is not a specific signal, and otherwise becomes '0'.

Similarly, the second sub-signal detection unit asynchronously performs a logical operation as shown in Equation 2 to detect whether the digital data is '1111'.

f2 = abcd

Here, f2 represents a logical combination expression of the second sub specific signal detection unit.

In addition, the third sub-signal detecting unit may use Equation 1 and Equation 3 to detect whether the first and second sensed results A1 and A2, which are outputs of the first and second sub-signal detecting units, are '11'. Unlike Equation 2, the logical operation shown in Equation 3 is performed asynchronously.

Here, f3 represents a logical combination equation of the third sub-signal detecting unit. In Equation 3, when the signal is not a specific signal, that is, when A1A2 is '11', the value of f3 becomes '0'. When the previous detection is completed and f3 becomes '0', A3 becomes '1'.

As a result, the first, second, and third sensed results A1, A2, and A3 sensed by the above-described logic expressions are transferred from the specific signal detector 142 to the external output unit 148 and the internal input units 144. Is output. Then, when the digital data is a specific signal, the external output shown in Fig. 9 outputs the positive outputs of each flip-flop set or reset signal in response to the first, second or third sensed result A1, A2 or A3. Outputs through the output terminal OUT as an operation value corresponding to a specific input. Therefore, when the apparatus shown in FIG. 7 inputs the digital data of '1111', the external output unit shown in FIG. 9 outputs the DQLN of '1000_0000_0000' through the output terminal OUT, and the digital data of '0001' or '1110'. Inputs the DQLN of '0000_0000_0100' through the output terminal OUT.

However, if the digital data is not a specific signal, the flip-flops of the external output unit shown in FIG. 9 output the result calculated by the operation unit 16 or 146 input through the data input terminal D to the output of the AND gate 190. In response, output through the output terminal OUT. Here, the AND gate 190 represents the AND gate 150 illustrated in FIG. 7. The AND gate 190 performs an AND operation on the clock signal CLOCK and the output enable signal OUTPUT ENABLE, and the result of the AND operation is used as a clock signal of each flip-flop. Output

As described above, the low power consumption type computing device for digital signal processing according to the present invention analyzes an input signal of a system or algorithm to be used, calculates a value of a specific signal that is input a lot, and when the specific signal is input. By outputting the pre-calculated value so that the computing device does not need to operate, power consumption can be minimized, and a specific input can be detected and output can be immediately output, improving the average execution speed of the system. The higher the average execution speed, the more the asynchronous method detects a specific signal, thereby minimizing the additional delay caused by a specific signal detection unit and prevents malfunction due to impulsive noise.

Claims (7)

External input means for inputting and temporarily storing digital data and outputting a stored signal; Specific signal sensing means for inputting the digital data outputted from the external input means to detect a specific input, and outputting the detected result; Internal input means for outputting the digital data input in response to the sensed result from the external input means; Calculation means for inputting and calculating data output from said internal input means; And And an external output means for selectively outputting the temporarily stored output means or the value corresponding to the specific input as the calculated result value of the digital data in response to the detected result. Low power consumption computing unit for processing. The method of claim 1, wherein the external input means First AND product for ANDing and outputting the enable signal and the clock signal; And And a D flip-flop for clock input of the output of the first AND function, data input of the digital data, and output of the digital data at a constant output. . The method of claim 2, wherein the specific signal detecting means Logically combining the digital data input from the external input means corresponding to the specific input in a self-timed response in response to the output of the first AND product, and performing the logical combination results as the sensed result. A low power consumption type computing device for digital signal processing comprising a sub specific signal sensing means for outputting. The method of claim 2, wherein the specific signal detecting means Each of the digital inputs input from the external input means in a self-timed manner in response to the output of the first AND product, wherein N specific input (s) First to N-th sub-specifics for performing a logical combination corresponding to a corresponding specific input among the two, and outputting the logical combination results as one of the first to Nth sensed results and one of the first to Nth sense termination signals. Signal sensing means; Second logical AND means for ANDing and outputting the first to Nth sensing termination signals; And N + 1 sub-specification for logically combining the first through Nth sensed results in response to the output of the second AND product and outputting the result of the logical combination as an N + 1 sensed result With signal sensing means, The first through N + 1 sensed results are output to the external output means as the sensed result, and the N + 1 sensed result is output to the internal input means as the sensed result. Low power consumption computing unit for digital signal processing. The method of claim 3, wherein the external output means And flip-flops corresponding to the number of bits of the value corresponding to the specific input, The set or reset terminal of each flip-flop is connected to the sensed result corresponding to a value corresponding to the particular input, wherein each flip-flop is a data input of an output of the computing means, and the first AND function And a signal output from the flop flips is a result of the calculation of the digital data. The method of claim 4, wherein the external output means And flip-flops corresponding to the number of bits of the value corresponding to the specific input, The set or reset terminal of each flip-flop is connected to one of the first through N + 1 sensed results corresponding to the value corresponding to the particular input, and each flip-flop is configured to output the output of the computing means. And inputting data, clocking the output of the first AND product, and outputting the signals from the flop flips are the calculated results of the digital data. External input means for inputting and temporarily storing digital data and outputting a stored signal; Specific signal sensing means for inputting the digital data outputted from the external input means to detect a specific input, and outputting the detected result; First internal input means for outputting the digital data input in response to the sensed result from the external input means; First calculation means for inputting and operating data output from said first internal input means; First delay means for outputting the detected result after a delay; Second through N (where N is a positive integer of 2 or more) internal input means; Second to N delay means; Second to N calculation means; And And external output means for selectively outputting data input from said N-th calculating means or a value corresponding to said specific input as a calculated result of said digital data in response to the output of said N-th delay means, The N-th internal input means outputs data input from the N-th operation means in response to the output of the N-th delay means, and the N-th operation means inputs the data output from the N-th internal input means. And the N-th delay means outputs the output of the N-th delay means after a delay.

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