KR100336756B1 - Clock dividing circuit - Google Patents

Abstract

The present invention relates to a clock divider circuit, and in the prior art, an odd divided circuit cannot be output using an even divider circuit, and the odd divider circuit has a different circuit configuration according to the division ratio of the divided clocks. However, there is a problem in that there is no compatibility and expandability between odd and even division circuits. Accordingly, the present invention has been made to solve the above-mentioned problems, and outputs the divided clock divided by the enable signal at the division ratio selected by the division ratio selection signal and the duty of the division clock. A clock division and duty controller for controlling the ratio to 50%; Provides a clock division circuit composed of a duty clock generator for outputting a 50% duty ratio of the divided clock by the duty ratio control signal of the clock division and the duty controller to sequentially output the state in the clock division by the division ratio selection signal. After the even and odd divisions, the duty ratio of the clock is increased to 50% and outputted, thereby improving the compatibility and expandability of the division circuit.

Description

Clock Division Circuits {CLOCK DIVIDING CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock divider circuit, in particular, in a clock divider circuit for dividing an input clock to a desired clock, a clock divider for increasing the number of states to divide into a clock having a 50% duty ratio regardless of even or odd division. It is about a circuit.

FIG. 1 is an even-dividing circuit diagram using a conventional flip-flop. As shown in FIG. 1, a power supply voltage VDD is commonly applied to two input terminals J and K, and an edge is inputted by a clock clock CLK_In of the clock terminal CLK. A first JK flip-flop 10 that operates as a trigger flip-flop and is reset by a reset signal Reset applied to the inverse; The power supply voltage VDD is commonly applied to the two input terminals J and K, respectively, and is sequentially operated by receiving the output clocks Q1, Q2 and Q3 of the previous stage as the clock terminal CLK, and inverting them. The second, third, and fourth JK flip-flops 11, 12, and 13 are reset by the reset signal Reset. Referring to FIG. Will be explained.

First, the plurality of JK flip-flops 10 to 13 receive the power supply voltage VDD from two input terminals J and K, respectively, and output the output clock Q at the rising edge of the clock applied to the clock terminal CLK. It operates as an edge trigger flip-flop that inverts the level of.

Therefore, when the input clock CLK_In applied to the clock stage as shown in FIG. 2A is divided by the first J flip-flop 10 and outputted as shown in FIG. 2B, the first J The second J-K flip-flop 11 receives the output clock Q1 divided by two from the K flip-flop 10 and divides it again and outputs it to the output clock Q2 as shown in FIG. The third JK flip-flop 12, which receives the output clock Q2 divided by the second JK flip-flop 11, divides it again into two output clocks Q3 as shown in FIG. The fourth JK flip-flop 13 receives the output clock Q3 divided by the third JK flip-flop 12 and divides it again into the output clock CLK_OUT. The output will be as shown in 2 (e).

In addition, FIG. 3 is a conventional three-dividing circuit diagram, which includes an exclusive OR gate XOR for receiving an input clock CLK_In and a feedback output CLK_OUT and outputting an exclusive OR operation on the input clock CLK_OUT; The power supply voltage VDD is commonly applied to both input terminals J and K, and is operated by the output signal Y1 of the exclusive OR gate XOR applied to the clock terminal CLK and inverted. A first JK flip-flop 20 which is reset by a reset); The second J operated by the inverted output clock Y2 of the first JK flip-flop 10 applied to the two inputs J and K and commonly applied to the clock terminal CLK. K flip-flop 21, which is described with reference to Figure 4 attached to the operation process according to the prior art configured as described above.

First, the exclusive OR gate XOR, which has received the high potential input clock CLK_In and the low potential output clock CLK_OUT, outputs a high potential, thereby inverting the clock Y2 in the first JK flip-flop 20. The second JK flip-flop 21 outputs a low potential because the output is at a low potential.

When the input clock CLK_In transitions from a high potential to a low potential (B), a low potential is output from the exclusive logic sum gate XOR, and the low potential output signal Y1 of the exclusive logic sum gate XOR is output. As the first JK flip-flop 20 applied to the clock terminal CLK maintains the low potential that is the previous state, the second JK flip-flop 21 also maintains the previous state.

When the input clock CLK_In transitions from a low potential to a high potential (C), the exclusive OR gate XOR outputs a high potential, thereby inverting the clock Y2 in the first JK flip-flop 20. The second JK flip-flop 21 receives the high potential and outputs the output clock CLK_OUT at high potential.

In this case, since the low potential is output from the exclusive OR gate XOR receiving the high potential output clock CLK_OUT, the first and second JK flip-flops 20 and 21 maintain the previous state. do.

When the input clock CLK_In transitions from a high potential to a low potential (D), the exclusive OR gate XOR outputs a high potential, whereby the first JK flip-flop 20 is an inverted clock Y2. ) And outputs a low potential, and the second JK flip-flop 21 maintains its previous state.

In addition, when the input clock CLK_In transitions from a low potential to a high potential (E), since the low potential is output from the exclusive OR gate XOR, the first and second JK flip-flops 20 received therefrom. 21) will remain the previous state.

When the input clock CLK_In transitions from a high potential to a low potential (F), the exclusive OR gate XOR outputs a high potential, and the first JK flip-flop 20 is an inverted clock Y2. The high potential is output to the second JK flip-flop 21, thereby outputting a low potential.

In this case, since the low potential is output from the exclusive OR gate XOR receiving the low potential output clock CLK_OUT, the first and second JK flip-flops 20 and 21 maintain the previous state. do.

As described above, in the prior art, even-numbered divided clocks cannot be outputted, and odd-numbered divided circuits have different circuit configurations depending on the division ratios of the divided clocks. There is a problem in that there is no compatibility and extensibility between frequency division circuits.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and provides a clock divider circuit which increases the number of states to divide the clock with 50% duty ratio regardless of even or odd division. There is a purpose.

1 is a distribution circuit diagram using a conventional flip-flop.

FIG. 2 is a diagram illustrating each sub clock timing of FIG. 1. FIG.

3 is a conventional three-division circuit diagram.

4 is a sub-clock timing diagram of FIG.

5 is a block diagram showing the configuration of a clock divider circuit of the present invention;

FIG. 6 is a block diagram showing the configuration of a clock division and duty ratio controller in FIG. 5; FIG.

7 is a block diagram showing the configuration of a duty clock generator in FIG.

8 is a block diagram showing the configuration of a clock divider in FIG.

FIG. 9 is a circuit diagram illustrating an exemplary configuration of a duty ratio controller in FIG. 6. FIG.

FIG. 10 is a circuit diagram illustrating an example configuration of a duty generator in FIG. 7; FIG.

FIG. 11 is a state diagram illustrating an operation of a clock divider in FIG. 6. FIG.

FIG. 12 is a diagram of sub-clock waveforms during odd division of FIG. 5; FIG.

FIG. 13 is a diagram of each sub-clock waveform at the time of even division of FIG. 5; FIG.

*** Description of the symbols for the main parts of the drawings ***

100: clock division and duty ratio controller 110: clock divider

111: state conversion unit 112: control unit

113: output unit 120: duty ratio controller

200: duty clock generator 210: duty generator

211: flip-flop 220: multiplexer

I1: Inverter AND1, AND2: Logic gate

The configuration of the present invention for achieving the above object outputs the divided clock divided by the enable signal at the division ratio selected by the division ratio selection signal, and controls the duty ratio of the division clock to 50%. A clock division and duty ratio controller; And a duty clock generator configured to output 50% of the duty ratio of the divided clock by the duty ratio control signal of the clock division and the duty ratio controller.

Hereinafter, with reference to the accompanying drawings, the operation and effect of an embodiment of the present invention will be described in detail.

FIG. 5 is a block diagram showing the configuration of a clock divider circuit of the present invention. As shown in FIG. 5, the input clock CLK_In is enabled by the division ratio select signal EO. A clock division and duty controller 100 for outputting the divided division clock CLK_Div and controlling the duty ratio of the division clock CLK_Div to 50%; The duty cycle generator 200 outputs 50% of the duty ratio of the frequency division clock CLK_Div by the duty cycle control signal DGE of the clock division and the duty controller 100.

The clock division and duty ratio controller 100 is enabled by the enable signal EN to divide the input clock CLK_In at the division ratio selected by the division ratio selection signal DO, as shown in FIG. 6. A clock divider 110 for outputting one divided clock CLK_Div; The duty ratio controller 120 outputs a duty ratio control signal DGE such that the duty ratio of the clock divided by the clock divider 110 is 50% by the division ratio selection signal EO and the enable signal EN. ).

In addition, the duty clock generator 200 includes an inverter I1 for inverting and outputting the input clock CLK_In as shown in FIG. 7; A logic AND gate AND1 for receiving the clock division CLK_Div and the duty ratio control signal DGE of the clock division and duty ratio controller 200 and performing an AND operation on the clock division and outputting a reset duty Reset_Duty; A duty generator (210) which is enabled by the reset duty (Reset_Duty) and receives an input clock (CLK_InBar) inverted by the inverter (I1) to make the duty ratio of the divided clock (CLK_Div) 50%; The multiplexer 220 selects the divided clock CLK_Div and the output signal CLK_Duty of the duty generator 210 by the duty ratio control signal DGE and outputs the output signal CLK_OUT to the output clock CLK_OUT.

As shown in FIG. 8, the clock divider 110 is enabled by the enable signal EN to convert the state signal State to the first state S1 by the initial state transition signal FSC. A state conversion unit 111 for increasing and outputting the state of the state signal State by 1 at the rising edge of the input clock CLK_In by the state conversion signal SC; A controller 112 for receiving the enable signal EN, the division ratio selection signal EO, and a state signal State to control an operation of the state conversion unit 111; And an output unit 113 that is enabled by the enable signal EN and outputs a divided clock CLK_Div by the division ratio selection signal EO and the state signal State.

In addition, the duty ratio controller 120 and the duty generator 210 receive an AND and perform an AND operation on the division ratio selection signal EO and the enable signal EN, as shown in FIGS. 9 and 10, respectively. Enabled by the reset duty Reset_Duty of the gate AND2 and the inverted reset stage, and the inverted input clock CLK_InBar applied to the clock stage CLK as the power supply voltage VDD is applied to the input terminal D. With reference to FIGS. 11 to 13 attached to the operation process according to the present invention configured as the flip-flop 211 that is configured as described above in detail.

First, when the odd division is to be performed, when the enable signal EN and the division ratio selection signal EO are applied to the clock division and duty controller 100 at high potential as shown in FIGS. 12B and 12C, The AND gate of the duty ratio controller 120 receiving the high potential enable signal EN and the division ratio select signal EO receives the duty ratio control signal DGE from FIG. Output at high potential as well.

The controller 112 in the clock divider 110 that receives the high potential enable signal EN outputs an initial state conversion signal FSC to the state conversion unit 111. The converting unit 111 initializes the state signal State from the state S0 to the state S1 at the initial rising edge of the input clock CLK_In, and shows the state of the state converting unit 111. The output unit 113 receiving the state signal State outputs the divided clock CLK_Div at a high potential.

The AND gate AND1 receiving the high potential division clock CLK_Div and the high potential duty ratio control signal DGE of the clock divider 110 outputs a reset duty Dut with a high potential and an input clock. The inverter I1 that receives the input of CLK_In inverts it and outputs it.

The de-flop 211 in the duty generator 210 enabled by the reset duty Reset_Duty of the inverting reset stage is applied to the clock stage CLK as the power supply voltage VDD is applied to the input terminal D. The multiplexer 220 which outputs a high potential at the rising edge of the inverted input clock CLK_InBar, and receives the high potential duty ratio control signal DGE, outputs the output clock CLK_OUT of the duty generator 210. Output the high potential output signal CLK_Duty.

In addition, the control unit 112 in the clock divider 110 outputs a state conversion signal SC to the state conversion unit 111, and the state conversion unit 111 that receives the state conversion signal SC receives the input clock CLK_In. At the next rising edge of, the state signal State is increased to state S2, and the output unit 113 outputs the divided clock CLK_Div at high potential.

Accordingly, the duty clock generator 200 receiving the high potential divided clock CLK_Div and the duty control signal DGE outputs the output signal CLK_OUT at high potential.

Accordingly, the state converting unit 111 that receives the state converting signal SC of the control unit 112 in the clock divider 110 states the state signal State at the rising edge of the input clock CLK_In. In order to sequentially increase from S3 to state Sn + 1, at this time, the output unit 113 continuously outputs the divided clock CLK_Div at a high potential, so that the duty clock generator 200 outputs the output signal CLK_OUT. Keep) at high potential.

In addition, when the state conversion unit 111 receives the state conversion signal SC of the control unit 112 in the clock divider 110, the state signal State is increased to state Sn + 2 and output. The output unit 113 receiving the input outputs the divided clock CLK_Div at a low potential.

Accordingly, the AND gate in the duty clock generator 200 receiving the low potential division clock CLK_Div outputs a reset duty Reset_Duty at a low potential, and the D in the duty generator 210 receives the low potential. Flip-flop 211 is reset to output a low potential.

Accordingly, the multiplexer 220 receiving the high potential duty ratio control signal DGE outputs the low potential output signal CLK_Duty of the duty generator 210 to the output clock CLK_OUT.

Accordingly, the state converting unit 111 that receives the state converting signal SC of the control unit 112 in the clock divider 110 states the state signal State at the rising edge of the input clock CLK_In. It sequentially increases from (S3) to state (S2n + 1) and outputs it.

The output unit 113 receiving the state signal State continuously outputs the divided clock CLK_Div at a low potential, and the duty clock generator 200 receiving the state signal outputs the output signal CLK_OUT at a low potential. Keep it.

In addition, if the enable signal EN is continuously applied, the controller 112 in the clock divider 110 outputs an initial state conversion signal FSC to the state conversion unit 111 and receives the input state. The conversion unit 111 initializes the state signal State to the state S1 at the first rising edge of the input clock CLK_In, and the output unit 113 receiving the state signal State receives the divided clock CLK_Div. Prints back to high potential.

Accordingly, a high potential reset duty (DRESET_Duty) is output from an AND gate of the duty clock generator 200 receiving the high potential divided clock CLK_Div and the duty control signal DGE, and the inverted reset stage is outputted. The de-flip flop 211 in the duty generator 210 is applied to output a high potential at the rising edge of the inverted input clock CLK_InBar applied to the clock stage CLK, and the high potential duty ratio control signal ( The multiplexer 220 receiving the DGE outputs the high potential output signal CLK_Duty of the duty generator 210 to the output clock CLK_OUT.

Accordingly, the duty clock generator 200 which receives the division clock CLK_Div and the duty ratio control signal DGE from the clock division and duty ratio controller 100 as shown in FIGS. As shown in (i), the output clock CLK_OUT with an odd division of the input clock CLK_In is output.

When the even division is to be performed, the enable signal EN and the division ratio selection signal EO are set to a high potential and a low potential as shown in FIGS. 13B and 13C by the clock division and the duty controller 100, respectively. When applied, the AND gate AND2 in the duty ratio controller 120 receiving the high potential enable signal EN and the low potential division ratio selection signal EO receives the duty ratio control signal DGE as shown in FIG. 13. Output at low potential as in (e).

The controller 112 in the clock divider 110 that receives the high potential enable signal EN outputs an initial state conversion signal FSC to the state conversion unit 111. The converter 111 initializes and outputs the state signal State to the state S1 at the first rising edge of the input clock CLK_In, and outputs the state signal State of the state converter 111. 113 outputs the divided clock CLK_Div at high potential.

In addition, the AND gate AND1 receiving the high potential division clock CLK_Div and the low potential duty ratio control signal DGE of the clock divider 110 outputs a reset duty Reset_Duty at a low potential and an input clock. The inverter I1 that receives the input of CLK_In inverts it and outputs it.

The de-flip flop 211 in the duty generator 210 receiving the low potential reset duty Reset_Duty as an inverting reset stage is disabled, thereby outputting a low potential, and outputting the low potential duty ratio control signal DGE. The input multiplexer 220 outputs the high potential output signal CLK_Div of the clock divider 110 to the output clock CLK_OUT.

The state converting unit 111, which receives the state converting signal SC of the control unit 112 in the clock divider 110, states the state signal State at the rising edge of the input clock CLK_In. The output unit 113 sequentially increases and outputs the signal from the state S1 to the state Sn, and the output unit 113 continuously receives the divided clock CLK_Div at a high potential.

In addition, the duty clock generator 200 receiving the high potential divided clock CLK_Div and the low potential duty ratio control signal DGE of the clock divider 110 is an output signal CLK_OUT. Continue to print CLK_Div).

In addition, when the state conversion unit 111 receives the state conversion signal SC of the control unit 112 in the clock divider 110, the state signal State is increased to state Sn + 1 and output. The output unit 113 receiving the input outputs the divided clock CLK_Div at a low potential.

Accordingly, the AND gate AND1 receiving the low potential division clock CLK_Div and the low potential duty ratio control signal DGE of the clock divider 110 outputs the reset duty Reset_Duty at a low potential, and inverts it. The flip-flop 211 input to the reset terminal is disabled to output a low potential, and the multiplexer 220 receiving the low potential duty ratio control signal DGE to the selection terminal SEL is an output clock ( The low potential output signal CLK_Div of the clock divider 110 is output to CLK_OUT.

In addition, the state converting unit 111 that receives the state converting signal SC of the control unit 112 in the clock divider 110 states the state signal State at the rising edge of the input clock CLK_In. It sequentially increases from (Sn + 1) to state (S2n) and outputs it. The output unit 113 receiving the input continuously outputs the divided clock CLK_Div at a low potential.

In addition, the duty clock generator 200 receiving the low potential division clock CLK_Div and the low potential duty ratio control signal DGE of the clock division unit 110 may output the low division frequency clock as the output signal CLK_OUT. Continue to print CLK_Div).

In addition, if the enable signal EN is continuously applied, the controller 112 in the clock divider 110 outputs an initial state conversion signal FSC to the state conversion unit 111 and receives the input state. The conversion unit 111 initializes the state signal State to the state S1 at the first rising edge of the input clock CLK_In, and the output unit 113 receiving the state signal State receives the divided clock CLK_Div. Prints back to high potential.

Accordingly, since the low potential is output from the AND gate of the duty clock generator 200 receiving the high potential divided clock CLK_Div and the low potential duty control signal DGE, the low potential is applied to the inverting reset stage. The de-flip flop 211 is reset to output a low potential, and the high potential of the duty generator 210 is output from the multiplexer 220 that receives the low potential duty ratio control signal DGE to an output clock CLK_OUT. The output signal CLK_Duty is selected and output.

That is, the duty clock generator 200 which receives the divided clock CLK_Div and the duty ratio control signal DGE from the clock division and duty ratio controller 100 as shown in FIGS. As shown in (i) of FIG. 13, the output clock CLK_OUT with an even division of the input clock CLK_In is output.

As described in detail above, the present invention sequentially increases the number of states of the state signal in the clock divider by the division ratio selection signal, and outputs the duty ratio of the divided clock to 50% after even and odd divisions. There is an effect of improving the compatibility and expandability of the frequency divider circuit.

Claims (7)

A clock divider for dividing the input clock by the enable signal at the division ratio selected by the division ratio selection signal; A duty ratio controller for outputting a duty ratio control signal such that the duty ratio of the clock divided in the clock divider is 50% by the division ratio selection signal and the enable signal; An inverter for inverting and outputting an input clock; An AND gate receiving the divided clock of the clock divider and a duty ratio control signal of a duty ratio controller and performing an AND operation to output a reset duty; A duty generator enabled by the reset duty of the AND gate and receiving an input clock inverted by the inverter to make the duty ratio of the divided clock to be 50%; And a multiplexer which selects the divided clock and the output signal of the duty generator by the duty ratio control signal and outputs them to an output clock. delete The clock divider of claim 1, wherein the clock divider is enabled by an enable signal to initialize the state signal to the first state by the initial state change signal, and then, at the rising edge of the input clock by the state change signal. A state conversion unit for increasing the state by one and outputting the state; A control unit which receives the enable signal, the division ratio selection signal and the state signal and controls the operation of the state conversion unit; And an output unit that is enabled by the enable signal and outputs a divided clock by the division ratio selection signal and a status signal. The method of claim 3, wherein the control unit sequentially divides the state of the state signal in the state conversion unit to S _{2n + 1} when the division ratio selection signal is high potential, and divides the odd _number . And a clock divider circuit configured to incrementally increase even-numbered division. 2. The clock divider circuit of claim 1, wherein the duty ratio controller comprises an AND gate for receiving a division ratio selection signal and an enable signal. delete 2. The duty cycle generator of claim 1, wherein the duty generator is configured by a de-flop that is enabled by a reset duty of an inverting reset stage and operated by an inverted input clock applied to a clock stage as a power supply voltage is applied to the input stage. Clock division circuit.