KR100210394B1 - Multi-value logic data transmitting system - Google Patents

Abstract

The present invention, the first to sixth comparison means (10 to 15); First to sixth signal generating means (16 to 21) for outputting predetermined multi-valued logic data to the system clock input from the system control section by the comparison signal from the comparing means (10 to 15); First, second and third multiplexers (22, 23, 24) for selectively outputting multi-valued logic data from the signal generating means (16 to 21) by the carry signal from the carry signal generating means (30); A first orifice (25) for outputting a predetermined signal by the multi-valued logic data signal from the first, second and third signal generating means (16, 17, 18); Synchronizing signal generating means (26) for outputting a synchronizing signal according to the output signal from the orifice (25); A second orifice 27 for outputting the synchronization signal from the synchronization signal generation means 26 and the synchronization signal from the delay means 28; A third orifice (29) for outputting a predetermined signal by the multivalued logic data signal from said fourth, fifth and sixth signal generating means (19, 20, 21); A carry signal generating means (30) for outputting a carry signal by the output signal from the third orifice (29); And a delay means (28) for delaying a predetermined clock delay of the synchronization signal from the synchronization signal generation means (26) by the output signal from the carry signal generation means (30).

Description

A system for transmitting the multiple-valued logic data

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multivalued logical data transmission system, and in particular, converts binary logic data from a system based on binary encoding into multivalued logical data, and then transmits data using a synchronization signal and a carry signal. The present invention relates to a multi-value logical data transmission system in which the number of lines is further reduced to reduce the complexity of internal wiring and to speed up data processing.

1 is a view schematically illustrating a concept of a general binary logic data transmission system, wherein predetermined 16-value data, for example, 302121 ₁₆ is transmitted to a binary logic data reception system from a binary logic data transmission system to binary data 1100000010000100100001 ₂ As shown in FIG. 1, the data bus between the binary logical data transfer systems requires 22 data lines. In addition, when several types of modules are connected to the data line, the circuit between the binary logic systems becomes more complicated.

As described above, when data is transmitted using binary logic between conventional binary logic transmission systems, input / output circuits and internal wiring become complicated, and data processing functions and processing speeds of a predetermined area are deteriorated. There was this.

Accordingly, the present invention is to solve the above problems, by converting the binary logic data from the system based on the binary encoding into multi-valued logical data, and then transmitting data using the synchronization signal and the carry signal. It is an object of the present invention to provide a multi-value logical data transmission system in which the number of lines is further reduced, the complexity of internal wiring is reduced, and the data processing speed can be increased.

According to the present invention for achieving the object described above, when binary logic data is input from a binary logic system, first to sixth comparisons outputting a comparison signal with respect to the binary data in comparison with the set reference value signal. Means; First to sixth signal generating means for outputting predetermined multi-valued logic data to the system clock input from the system control section by the comparison signal from the comparing means; First, second and third multiplexers for selectively outputting multivalued logic data from the signal generating means by the carry signal from the carry signal generating means; A first orifice outputting a predetermined signal by the multivalued logic data signal from said first, second and third signal generating means; Synchronizing signal generating means for outputting a synchronizing signal by an output signal from the orifice; A second orifice for outputting a synchronization signal from the synchronization signal generating means and a synchronization signal from the delay means; A third orifice outputting a predetermined signal by the multivalued logic data signal from said fourth, fifth and sixth signal generating means; Carry signal generating means for outputting a carry signal by the output signal from the third orifice; And a delay means 28 for delaying the synchronization signal from the synchronization signal generation means by a predetermined clock by the output signal from the carry signal generation means.

According to the present invention configured as described above, the number of data lines is further increased by converting binary logic data from a system based on binary coding into multivalued logic data and then transferring data using a synchronization signal and a carry signal. As a result, the data processing speed is increased, and the complexity of the input / output circuit and the internal wiring can be reduced.

1 is a view schematically showing a concept of a general binary logic data transmission system;

2 is a diagram schematically illustrating a concept of a multi-valued logical data transmission system;

3 is a detailed block diagram of a multi-value logical data transmission system according to the present invention;

4 is a view showing an operation waveform diagram for explaining the operation of the multi-value logical data transmission system according to the present invention.

Explanation of symbols on the main parts of the drawings

10,11,12: first, second and third comparators,

15,16,17: first, second and third signal generator,

20 to 25: first to sixth delay elements, 26 to an oragate,

27: synchronization signal output unit, 50: multi-value logical data transmission system,

51: multi-valued logical data receiving system, 100: binary data transmission system,

101: binary logic data receiving system.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

On the other hand, multiple-valued logic is a current binary digital integrated circuit in such a manner that a digital system is constructed from an algorithm based on multivalued coding for a current binary digital system, such as an information system based on binary coding. It is possible to realize new hardware that overcomes the limitations.

Therefore, multi-value logic can increase the integration density and reduce the complexity of internal wiring while reducing the complexity of input and output. In addition, the complexity of the hardware can be reduced by increasing the data processing function and the storage density of a certain area, and by reducing the number of modules of the system hardware amount while facilitating mutual conversion with external signals.

Further, the processing time can be increased by reducing the number of steps of serial connection and the number of repetitions of operations, and the practical use of a quaternary mask ROM having such a feature, a dynamic RAM, a 32-bit multiplier, and the like are continuously studied. In addition, if there is general use with current binary logic, high speed and chip area can be reduced, and mixed with binary logic by multi-valued logic operation without modification of existing circuit that is composed of binary system. Done.

On the other hand, multivalued logic is an extension of the binary logic that is widely used in all fields of information and communication systems, and the binary circuit recognizes and processes only logic 0 and logic 1 according to high and low voltage or current flow. In multi-valued logic, the circuit processes various logic values, such as 0, 1, 2, or 3, depending on the magnitude of the voltage, the strength of the current, and the amount of charge.

The multi-value logic circuit can be divided into a voltage mode in which information is expressed in magnitude and polarity of a voltage, and a current mode in which information is expressed in magnitude and direction of a current, and a charge mode in which information is expressed by an amount of charge.

2 is a diagram schematically illustrating the concept of a multi-valued logical data transmission system. First, the multi-valued logic in the present embodiment will be described with reference to 16-valued logic. Therefore, in the case where it is desired to transfer predetermined data, for example, data of 302121 ₁₆ from the 16-value logical data transmission system to the 16-value logical data reception system, as shown in Fig. 2, the data bus between the 16-value logical data transmission system has five data lines. Only need.

As described above, in the case of transferring data using the 16-value logic between the 16-value logic data transmission systems, the input / output circuit and the internal wiring are simple as described above, and the data processing function and processing speed for a certain area are improved. Will be.

3 is a detailed block diagram of a multi-valued logical data transmission system according to the present invention, wherein the multi-valued logic data transmission system includes first to sixth comparators 10 to 15; First to sixth signal generators 16 to 21; First, second and third multiplexers 22, 23 and 24; First, second and third orifices 25, 27, 29; First and second synchronization signal generators (26, 30); 16 clock delay elements 28.

On the other hand, when a predetermined binary signal of the nine binary signals is input to the first to sixth comparators 10 to 15, respectively, the first to sixth comparators 10 to 15 are set to a reference value signal and a binary value to be input. When the signals are compared and match the set signals, the comparison signals for the corresponding binary signals are output to the first to sixth signal generators 16 to 21, respectively.

In addition, the first to sixth signal generators 16 to 21 have a predetermined multi-value for the system clock input from a system controller (not shown) by the comparison signals from the first to sixth comparators 10 to 15. The logical data is output as, for example, 16-value logical data.

Thereafter, 16-value logic data, for example, 16 ⁰ digit data, from the first signal generator 16 is transmitted to the multi-value logic data receiving system 51 through the first multiplexer 22, and the second signal generator ( 16-value logical data from 17), for example, 16 ^one- digit data, is transmitted to the multi-value logical data receiving system 51 through the second multiplexer 23, and 16-value logical data from the third signal generator 18. For example, 16 ^two digits of data are transmitted to the multivalued logical data receiving system 51 through the third multiplexer 24.

The output signals from the first, second and third signal generators 16, 17, and 18 are input to the synchronization signal generator 26 via the first or gate 25, and then the synchronization signal generator. The synchronization signal from (26) is transmitted to the multi-value logical data receiving system 51 through the second orifice 27.

At the same time, 16-value logic data from the fourth signal generator 19, for example, 16 ^3- digit data, is input to the first multiplexer 22, and 16-value logic data from the fifth signal generator 20, For example, 16 ⁴ digits of data are input to the second multiplexer 23, and 16-value logic data from the sixth signal generator 21, for example, 16 ⁵ digits of data, are input to the third multiplexer 24.

In addition, the output signals from the fourth, fifth and sixth signal generators 19, 20, and 21 are input to the carry signal generator 30 via the third orifice 29, and then the carry signal generator A carry signal from 30 is transmitted to the multivalued logic data receiving system 51, and at the same time the carry signal is transmitted to the 16 clock delay elements 28 (16D) and the first, second and third multiplexers 22. , 23, 24).

Thereafter, the first, second and third multiplexers 22, 23, and 24 are configured to output the fourth, fifth and sixth signal generators 19, 20, and 21 by an output signal from the carry signal generator 30. 16 ³ , 16 ⁴ , and 16 ⁵ digits of data are transmitted to the multi-value logical data receiving system 51. In addition, after the 16 clock delay element 28 delays 16 clocks of the synchronous signal input from the synchronous signal generator 26 by the carry signal from the carry signal generator 30, the second oracle 27 is delayed. Will be entered. Accordingly, the second orifice 27 transmits the synchronization signal from the synchronization signal generator 27 and the synchronization signal delayed by 16 clocks to the multi-value logic data receiving system 51.

4 is an operation waveform diagram for explaining the operation of the multi-value logical data transmission system according to the present invention. In this case, when data is to be transmitted by 16-value logic, one data is transmitted per 16 system clocks. . Therefore, if a carry signal for starting transmission of data is output from a system control unit (not shown) when a predetermined 16-value logical data, for example, 302121 _{16 is} to be transmitted, 16 ⁰ , 16 ¹ , 16 ^2- digit data, 121 is After that, 16 ³ , 16 ⁴ , 16 ⁵ digits of data, for example, 203, which is delayed by 16 clocks by the carry signal, is output.

Thereafter, the multi-value logic data receiving system 51 receives the synchronization signal, the carry signal, and the 16-value logic data from the multi-value logic data transmission system 50 and converts the binary data into binary data. In this way, when the binary logic data is converted into 16-value logic data and transmitted, only one synchronization signal line, a carry signal line, and three 16-value logic data lines are required, respectively, thereby reducing the data line.

On the other hand, the reference numerals written in the components of the claims of the present application to facilitate the understanding of the present invention, and are not written in the intention to limit the technical scope of the present invention to the embodiments shown in the drawings. Further, various modifications can be made without departing from the scope of the invention.

As described above, according to the present invention, the number of data lines is converted by converting binary logic data from a system based on binary coding into multivalued logic data and then transferring data using a synchronization signal and a carry signal. This further reduces the data processing speed, and reduces the complexity of the input / output circuit and the internal wiring.

Claims (6)

First to sixth comparison means (10 to 15) for outputting a comparison signal for the corresponding binary logic data when the binary logic data is input from the binary logic system; First to sixth signal generating means (16 to 21) for outputting predetermined multi-valued logic data to the system clock input from the system control section by the comparison signal from the comparing means (10 to 15); First, second and third multiplexers (22, 23, 24) for selectively outputting multi-valued logic data from the signal generating means (16 to 21) by the carry signal from the carry signal generating means (30); A first orifice (25) for outputting a predetermined signal by the multi-valued logic data signal from the first, second and third signal generating means (16, 17, 18); Synchronizing signal generating means (26) for outputting a synchronizing signal according to the output signal from the orifice (25); A second orifice 27 for outputting the synchronization signal from the synchronization signal generation means 26 and the synchronization signal from the delay means 28; A third orifice (29) for outputting a predetermined signal by the multivalued logic data signal from said fourth, fifth and sixth signal generating means (19, 20, 21); A carry signal generating means (30) for outputting a carry signal by the output signal from the third orifice (29); And a delay means (28) for delaying a predetermined clock delay of the synchronization signal from said synchronization signal generation means (26) by the output signal from said carry signal generation means (30). 2. The apparatus of claim 1, wherein the first, second and third multiplexers 22, 23 and 24 respectively comprise first and fourth signaling means 16 and 19 and second and fifth signaling means 17, respectively. 20), multi-valued logic data transmission system, characterized in that selectively outputting the multi-valued logic data from the third and sixth signal generating means (18, 21), respectively. The multi-value logical data transmission system according to claim 1, wherein the multi-value logical data transmission system converts binary logic data into 16-value logical data and transmits the converted binary data. The synchronization signal generating means (26) according to claim 1, wherein the synchronization signal generating means (26) outputs 16 ⁰ , 16 ¹ , 16 ^2- digit data from the first, second, and third signal generators (16, 17, 18). A multivalued logic data transmission system, wherein a synchronization signal of a clock is generated. The method of claim 1, wherein the carry signal generating means 30 is 1 when 16 ³ , 16 ⁴ , 16 ⁵ digits of data are output from the fourth, fifth and sixth signal generators 19, 20, 21. A multivalued logic data transmission system, wherein a carry signal of a clock is generated. 2. A multivalued logic data transfer system as claimed in claim 1, wherein said delay means (28) delays the synchronization signal from said synchronization signal generating means (26) by 16 clocks.