JPWO2004036416A1 - Processor having multi-bank register and method for controlling processor - Google Patents

Abstract

It is an object of the present invention to make it difficult for stalls to occur in pipeline processing by handling many registers without increasing the instruction length. The processor (100) accesses from the instruction decoder, the arithmetic unit (12), the memory access means (13, etc.) for inputting / outputting data to / from the external memory (19), and the arithmetic unit and the memory access means A plurality of register banks (11) each having a possible register, a register bank designation control signal from the instruction decoder based on a register bank designation instruction, and which of the register banks the operator accesses; Bank switching means for controlling which of the register banks the memory access means accesses. A multiprocessor system using the processor (100) and a method for controlling the processor (100) are also provided.

Description

  The present invention relates to the architecture of a processor such as a CPU (Central Processing Unit) or DSP (Digital Signal Processor) that is an arithmetic unit of a computer device, and more particularly to a microprocessor that implements an instruction set architecture and a control method thereof.

Background Art Processors used in various devices, particularly microprocessors, have been improved in arithmetic processing capability by techniques such as increasing the clock frequency against the background of recent advances in semiconductor microfabrication technology. On the other hand, the transfer speed between the external memory that functions as the main memory and the processor is also improved by using various technologies, but there are physical restrictions such as the number of connection pins and memory response speed, and the processor The performance has not been caught up. For this reason, the processor consumes an extra number of clocks (usually called latency) when accessing the memory compared to accessing the internal register. In order to bridge such a data transfer bandwidth gap between the internal bus of the processor and the bus between the memories, a cache memory is often used in recent processors.
A multiprocessor system is known as a technique for obtaining a high arithmetic processing capacity as a whole by operating a plurality of processors in a coordinated manner. In this multiprocessor system, in order to link the operations of the processors, it is necessary to guarantee coherency (consistency) in data between cache memories built in the processors.
In the case of constructing a multiprocessor system by a plurality of processors each having a cache memory, a method for guaranteeing the above coherency by snooping (bus snooping) in which other processors monitor access to the memory of each processor is known. Yes. However, this snooping has the effect of reducing the data transfer bandwidth of the bus between the processor and the memory. Therefore, even if a multiprocessor system is used, it is difficult to improve the calculation performance of the entire system in proportion to the number of processors used.
In a multiprocessor system, there is a method of guaranteeing data coherency by using a shared memory system in which memories are shared among processors. However, in the shared memory system, the data transfer bandwidth of the bus between the shared memory and the processor becomes a factor that limits the performance of the multiprocessor system.
As a technique for improving the processing capability of a single processor using parallel processing, methods such as a super pipeline, a super scaler, and a VLIW (Very Long Instruction Word) are known. A super pipeline and a super scaler are techniques for improving arithmetic processing capability by performing parallel processing at an implementation level. VLIW is a technique for improving the arithmetic processing capability by performing parallel processing at the instruction level in a processor having a plurality of arithmetic units inside. In any of the parallel processing methods, since the program that is originally sequentially executed is processed in parallel, it is inevitable that the dependency relationship from the viewpoints of instructions, operands, and control is unavoidable. For example, there is a strong dependency between a load instruction that is a data transfer instruction from a memory to a register and an arithmetic instruction that uses the register loaded with the data as an operand. This load instruction accompanies access to the external memory when there is no data to be loaded into the cache (when a cache miss occurs). As in this example, the aforementioned dependencies can be associated with large latencies. In that case, there is a problem that the instruction execution pipeline is stalled and the arithmetic performance inherent in parallel processing cannot be obtained.
In order to solve this parallel processing problem, dynamic scheduling using a reordering buffer that dynamically schedules instructions to be executed may be used. However, even in this case, the effect is generally limited to a range of 10 or more instructions. Therefore, when a cache miss occurs, the instruction execution pipeline cannot fill the stall, and the advantage of parallel processing is not fully exhibited. In addition, the dynamic scheduling has a problem that the hardware is complicated and the circuit scale becomes enormous.
Variables necessary for the processor to execute the desired software are placed in registers within the processor or memory on the system. Access to the memory is slower than access to the register, not only in the case of the cache miss described above, but also in the case where there is a variable that accesses the cache memory.
Although the number of variables required for one program depends on the program, it is generally several tens to one hundred and several tens. In a conventional processor, there are many examples in which 8 to 32 registers are mounted due to restrictions on physical implementation and instruction length on an instruction set architecture for operating the processor. For example, in the case of a two-operand instruction set architecture that uses 32 registers and two computation targets, among the bits that make up one instruction, 5 bits are specified for each register and operand, for a total of 10 bits. I need. Similarly, in the case of 3 operands using 32 registers and storing the operation result in a register different from the operation target, a total of 15 bits are required to specify the operand. The instruction length is obtained by adding a bit indicating an operation code indicating the type of operation.
Here, as the instruction length increases, it is necessary to increase both the memory size for the program and the bus bandwidth used for executing the program between the memory and the processor. Therefore, in general, from the viewpoint of implementation inside the processor, it is effective to shorten the instruction length in order to improve the calculation performance.
On the other hand, increasing the number of registers makes it possible to reduce access to the cache memory and external memory. Furthermore, since load instructions and store instructions for transferring data between the external memory and the register can be reduced, the number of program steps is reduced. For these reasons, if the number of registers that can be handled is increased, it is possible to prevent a decrease in calculation performance, but the instruction length becomes long to specify the registers.
In an actual processor architecture, the instruction length is appropriately set in consideration of these conflicting relations and the purpose of use. Typically, when the number of registers is set small, the instruction length is 16 bits, and when the number of registers is set large, the instruction length is 32 bits.
Further, “register renaming” is known as a technique for increasing the number of virtual registers while keeping the number of registers on the instruction set.
Further, for example, Patent Document 1 discloses a technique for switching each register for the purpose of effective use of registers.
Patent Document 1: Japanese Patent Laid-Open No. 7-84785

The present invention provides a processor architecture that can suppress the occurrence of latency due to memory access while shortening the instruction length as much as possible to improve operation performance when used alone. The problem is to solve at least some of them.
In addition, the present invention provides a processor architecture capable of preventing a decrease in data transfer bandwidth between a processor and a memory due to snooping while guaranteeing memory coherency even in a multiprocessor configuration. Thus, it is an object to solve at least some of the above problems.

In the present invention, the registers in the processor are configured in a plurality of register banks. Then, the processor architecture is realized by realizing a mechanism in which an arithmetic device and a memory access device provided in the processor are dynamically connected to different register banks. In general, in the present invention, by using a register bank switch means and a register bank specifying instruction such as a register bank setting instruction or a register bank setting modification instruction, a large number of instructions with a short instruction length such as 16 bits can be obtained. It makes it possible to handle registers.
Specifically, according to the present invention, an instruction decoder that decodes an instruction including a register bank designation instruction and a normal instruction to generate a control signal, and an arithmetic operation that performs arithmetic processing based on the control signal from the instruction decoder A memory access means for inputting / outputting data to / from an external memory based on a signal from the computing unit, and a plurality of register banks each having a register accessible from the computing unit and the memory access means, Bank switching means controlled by a register bank designation control signal generated by the instruction decoder based on the register bank designation instruction, determining which register bank the computing unit accesses, and the memory access means And bank switch means for determining which register bank is to be accessed. The link designation instruction is an instruction to switch the register bank assigned to the register used by the operand in order to execute the normal instruction after the register bank designation instruction using the operand by controlling the bank switch means. A processor having a multi-bank register is provided.
The instruction decoder receives and decodes an instruction fetched from an instruction storage device provided outside the processor, and generates a control signal. The memory access means is means for providing access to an external memory, and provides memory and processor access by means well known in the art such as an external bus, cache memory, address generator, etc., and transfers data. Can be any technique possible. The memory access means provides access to the processor registers and external memory.
Each register bank includes a plurality of registers organized in a bank of appropriate units. Each register bank is distinguished by a bank identifier, such as a number with an appropriate number of bits. Since a processor including a plurality of register banks is used in the present invention, a bank identifier and a register address are designated to specify an arbitrary register. However, in each instruction executed by this processor, as will be described in detail later, by using a bank setting instruction or a bank setting modification instruction for switching banks, in other instructions (ordinary instructions), There is no need to specify a bank identifier.
The register bank designation instruction includes a bank identifier that explicitly designates a bank in some form. For example, the register bank designation instruction is an instruction having a bank identifier that designates a source operand or destination operand bank of an operand having two operands as an operand (referred to as “bank setting instruction” in this specification). Can do. This register bank specification instruction does not specify only individual registers, such as those with general-purpose registers, but specifies register bank allocation for each operand position, such as a source operand and destination operand used with an opcode. It can be. This register bank designation command is operated by the instruction decoder as a register bank designation control signal to operate the arithmetic unit.
Of the instructions executed by the processor, instructions other than the register bank designation instruction do not include a bank identifier. Such an instruction is called a “normal instruction” in distinction from a register bank designation instruction. Regular instructions can use operands. The operand of a normal instruction executed by this processor can basically be assumed to be assigned a register bank explicitly specified by a register bank specifying instruction until the instruction is reached. . For example, bank 0 is assigned to the source operand, bank 3 is assigned to the destination operand, and so on. For this reason, the instruction length of a normal instruction does not need to be particularly long just because a register bank is used.
This register bank assignment is realized by bank switch means. The bank switch means is controlled by a register bank designation control instruction based on the register bank designation instruction. This bank switch means is, for example, a register that designates a bank of source operands and destination operands used for all subsequent instructions. This designation may be changed for each operand, or may be the same. Note that the operation of the bank switch means when the register bank designation instruction is not explicitly included can be based on an appropriate default value. Further, the register bank designation instruction is not limited to an instruction that designates a register bank in a subroutine unit.
When a plurality of register banks are used by performing switching by an additional instruction as necessary as in the present invention, a large number of registers can be used while keeping the instruction length used for a normal instruction short. . Since a large number of registers can be used in this way, it is possible to suppress the frequency of memory access using the locality of data, as has been done with a cache memory. In addition, the transfer bandwidth can be made larger in the register than in the cache memory. The more registers are used, the faster calculation is possible than when the cache memory is heavily used.
In the present invention, the bank switch means is controlled by the register bank designation control signal, determines whether the arithmetic unit accesses any of the register banks, and the memory access means uses any one of the other registers. Access to the bank is determined, and simultaneous access to the register by the arithmetic unit and access to the register by the memory access means can be made possible.
With this configuration, a register bank different from the register bank connected to the arithmetic device can be connected to the memory access device. If comprised in this way, it will become possible to perform the data transfer between a memory and a register | resistor by an arithmetic instruction and a memory access instruction in parallel. During the processing of an operation that uses a register in a register bank, the processor reads data from the memory for another register bank, or stores the data in the register bank where the operation results are stored in the memory. It can be done explicitly from the software. As a result, it is possible to easily suppress a decrease in the processing performance of the processor due to a pipeline stall caused by data dependency between the load instruction and the operation instruction with a simple hardware configuration. Note that the memory access means can provide access to the external memory and the register based on an instruction from the instruction decoder.
In the processor of the present invention, the register bank setting instruction is a register bank setting modification instruction, and the register bank setting modification instruction is usually immediately after the register bank setting modification instruction by controlling the bank switch means. In order to execute the instruction using the operand, it is possible to change the register bank assigned to the register for the operand of the normal instruction immediately after the instruction.
In this case, the register bank assigned to the register for the operand of only the instruction immediately following the register bank setting modification instruction is switched. In other words, the register bank setting modification instruction is an instruction for designating a register bank having a modification effect that affects only the immediately following instruction. This register bank setting modification instruction is also called a register bank setting prefix. The register bank setting modification instruction allows the register bank to be flexibly specified in the program, and the degree of programming can be secured while suppressing the instruction length.
In the present invention, when the register bank setting modification instruction is immediately before, the instruction length is extended from the instruction length of a normal instruction, and the register bank setting modification instruction and the immediately following normal instruction are extended. One instruction having an instruction length can be obtained. Here, when the register bank designation instruction is a register bank setting modification instruction, the register bank setting modification instruction and a normal instruction are combined to form a unit of the instruction. A register bank setting modification instruction alone is not a unit. This is because the register bank setting modification instruction modifies the register for the operand of the normal instruction immediately after it, and is not an executable instruction by itself.
Extending the instruction length is an instruction set architecture that allows the operation of the instruction immediately after the register bank setting modification instruction to be modified and executed according to the register bank setting modification instruction as an executable instruction. Or a decoder capable of decoding such an instruction set architecture, not merely changing the instruction delimitation formally. Also, it does not directly correspond to describing the assembler code in one line.
In these processors according to the present invention, the register bank specifying instruction is a register bank setting instruction. In an ordinary instruction after the register bank setting instruction, the operand is not required to be explicitly specified. The register bank assignment based on the register bank designation instruction can be applied to the register to be used. The register bank setting instruction is a kind of register bank designation instruction, and designates allocation of a bank of operands in a subsequent normal instruction. In the normal instruction after that, the register bank assigned by the register bank setting instruction is used without particularly specifying the register bank.
When such a register bank setting instruction is used, the instruction length of a normal instruction is set to a short instruction length similar to a processor architecture in which the register is not configured in the register bank, and the register bank setting instruction is used as necessary. be able to. This makes it possible to handle a large number of registers while keeping the average instruction length of the entire program composed of a plurality of instructions short.
As another aspect of the present invention, there is provided a multiprocessor system comprising at least an instruction storage means, a first processor, a second processor, and an external memory, wherein the first processor and the second processor The processor decodes an instruction including a register bank designation instruction from the instruction storage means and a normal instruction to generate a control signal, and performs arithmetic processing based on the control signal from the instruction decoder A plurality of register banks each comprising a computing unit, memory access means for inputting / outputting data to / from the external memory based on a signal of the computing unit, and a register accessible from the computing unit and the memory access means And a register bank designation control signal generated by the instruction decoder based on the register bank designation instruction. Bank switch means for determining which register bank the arithmetic unit accesses, and bank switch means for determining which register bank the memory access means accesses. The designated instruction is an instruction to switch a register bank to be assigned to a register used by the operand in order to execute a normal instruction after the register bank designated instruction by using the operand by controlling the bank switch means. A multiprocessor system is provided in which the external memory is connected so as to be accessible from both the memory access means of the first processor and the memory access means of the second processor.
This external memory is accessed by at least two processors included in the multiprocessor system. Thereby, for example, a multiprocessor system having an SMP (Symmetrical Multiprocessor) configuration, and a multiprocessor configuration in which a CPU core and a DSP core are linked can be realized. With this feature, it is possible to use a register bank in each processor constituting the multiprocessor system. It is possible to compensate for gaps in the data transfer bandwidth caused by the bus between the processor and the memory with a large number of local registers. Further, since the registers of each bank can be observed and controlled from software, there is no problem of data coherency. Thus, the data transfer bandwidth of the bus between the processor and the memory is not lost due to snooping. For this reason, it is possible to increase the number of processors in the SMP configuration to improve the calculation performance, and it is possible to increase the capability of the cooperative processing between the DSP and the CPU incorporating the specific purpose signal processing calculation circuit.
In such a multiprocessor system, the bank switch means is controlled by the register bank designation control signal, determines which of the register banks the arithmetic unit accesses, and which of the other memory access means It is determined whether to access the register bank, and simultaneous access to the register by the computing unit and access to the register by the memory access means can be performed.
Using simultaneous access not only improves the processing capability of each processor constituting a multiprocessor system, but also results from data transfer between processors, which is often a problem when performing arithmetic processing in cooperation with multiple processors. Stalls are reduced.
In the present invention, in such a multiprocessor system, in the external memory, at least a part of a memory area accessed by the first processor and a memory area accessed by the second processor are shared. Can be.
Even when so-called shared memory is used, by increasing the number of registers, data transfer required between the processor and memory can be reduced with the same effect as data caching using data locality. Can do. Thereby, even when the shared memory is used in the multiprocessor system, the calculation performance is improved as compared with the case where the memory bank is not used.
As another aspect of the present invention, an instruction decoder that decodes an instruction including a register bank designation instruction and a normal instruction to generate a control signal, and an arithmetic unit that performs arithmetic processing based on the control signal from the instruction decoder A memory access means for inputting / outputting data to / from an external memory based on a signal from the computing unit, a plurality of register banks each having a register accessible from the computing unit and the memory access means, A processor control method comprising an arithmetic unit and bank switch means for determining which register bank each memory access means accesses, wherein the instruction decoder controls register bank designation based on the register bank designation instruction A signal generating step and the bank switch operation by the register bank designation control signal. Switching which register bank is assigned to a register used by an operand of a normal instruction after the register bank designation instruction, and controlling which register bank the computing unit accesses; By controlling the bank switch means by means of a designation control signal, the register bank assigned to the register used by the operand is switched to control which register bank the memory access means accesses; and the normal instruction There is provided a method of controlling a processor having a multi-bank register including executing with an operand.
The processor according to the present invention switches the register bank accessed by the arithmetic unit or the memory access means by the register bank designation control signal, and executes the instruction. In order to appropriately perform this, a control method including the above steps can be performed. As a result, the register bank assigned to the register of the operand of the subsequent instruction is determined, so that it is possible to handle a large number of registers while keeping the instruction length short by such a control method.
Note that the above steps need not necessarily be performed in this order. As a result of the sequence of each instruction of the program, it can be executed in various orders. Further, there may be steps performed simultaneously, or the execution frequency of each step may be greatly different.
In this control method, the step of executing the normal instruction using an operand includes: an access to a register of a certain register bank by the arithmetic unit; and an access to a register of another register bank by the memory access means. Can be included at the same time.
When accessing a certain register bank, the memory access means can access another register bank. Both of these accesses are included in the instruction execution step. The range of this execution step can be determined by time, for example, from the first clock required to execute a normal instruction to the last clock in units of clocks at which the processor operates. Within this range, the arithmetic unit and the memory access means can access the registers used by each of the separate register banks in parallel. In a conventional processor, it is necessary to use a multi-port register file in order for the arithmetic unit to access a register and to access a memory in parallel. However, by dividing the register, which is a feature of the present invention, into banks, it is possible to access in parallel in this way using a normal register file. As a result, it is possible to perform other operations even during the time when the latency of memory access temporarily stops execution of instructions, and the processing capacity is improved. Also, the frequency and time of pipeline processing stalls are reduced.
In the processor control method of the present invention, the register bank designation instruction is a register bank setting modification instruction, and the register bank setting modification instruction is immediately after the register bank setting modification instruction by controlling the bank switch means. In order to execute the normal instruction in the instruction using the operand, it is possible to change the register bank assigned to the register of the operand for the operand of the normal instruction immediately after the instruction.
The register bank setting modification instruction is the above-described instruction for designating a register bank having a modification effect that affects only the immediately following instruction. Also in the control method of the processor, it is possible to specify the register bank flexibly in the program by the register bank setting modification instruction, and it is possible to secure the degree of programming freedom while suppressing the instruction length.
In the processor control method of the present invention, when the register bank setting modification instruction is immediately before, the instruction length is extended from the instruction length of a normal instruction, and the register bank setting modification instruction and the normal instruction immediately after May be one instruction having the extended instruction length.
Further, in this control method, the register bank designation instruction is a register bank setting instruction, and in an ordinary instruction after the register bank designation instruction, the operand is not required to be explicitly designated. A control method is provided in which register bank assignment based on the register bank designation instruction is applied to a register to be used.
By having a register bank designation instruction, it is possible to keep a short instruction length without including a bank identifier in a normal instruction. By adjusting the register bank designation instruction to this instruction length, it becomes possible to handle many registers while keeping the maximum instruction length of the entire architecture short.
As another aspect, the processor control method of the present invention can be a control method having a conditional execution switching modification instruction for controlling an operation of whether or not a subsequent instruction is executed depending on a determination condition.
This conditional execution switching modifier instruction is sometimes referred to as a conditional execution prefix. The conditional execution switching modification instruction is a modification instruction (prefix) that can switch whether or not to execute the subsequent instruction according to the determination condition without accompanying a branch instruction. By using this modification instruction, it is possible to reduce the branch of the program itself, and to avoid the stall associated with the branch instruction during parallel processing.
The processor control method of the present invention may be a control method using a register bank designation instruction and the conditional execution switching modification instruction.
Using a combination of the conditional execution prefix and the register bank specification instruction of the present invention, it is possible to write a program that can be processed in parallel with almost no stalls. Can be realized.
Further, in the control method of the present invention, the register bank designation modification instruction and the conditional execution switching modification instruction are decoded by the prefix decoder that prefetches the instruction executed by the instruction decoder, and the prefix decoder generates based on the modification instruction. The decoding operation of the instruction decoder can be changed according to the instruction decoder control signal. Each modification instruction itself does not constitute one instruction that the instruction decoder recognizes as an instruction. If the pre-read modification instruction is combined with the instruction immediately after the modification instruction and the instruction execution step is performed as one instruction, the target operation can be performed without increasing the instruction execution step. This operation can be appropriately executed by using a prefix decoder that prefetches instructions.
Throughout this application, the expression “simultaneous” is used, but this is within the range that can be said to be substantially the same time in a step consisting of a clock unit or several clocks normally used in the computer field. This means that two or more events are occurring or overlapping. Even if it is performed at different timings, the two target events will be performed by the next clock pulse, the two target events will occur from the start to the end of a step, and the target will end It is included that there is an overlap in the period between the events. In this sense, if it is recognized that both events are substantially the same, it is considered to be “simultaneous”.

FIG. 1 is a configuration diagram showing an outline of a processor according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram showing an assembler code including a bank designation instruction according to the embodiment of this invention.
FIG. 3 is an explanatory diagram showing a state of bank switching by the assembler code of FIG.
FIG. 4 is an explanatory diagram showing an implementation example of the bank designation instruction according to the embodiment of the present invention.
FIG. 5 is a functional block level configuration diagram showing the configuration of the instruction fetch stage in the processor configuration example according to the embodiment of the present invention.
FIG. 6 is a functional block level configuration diagram showing the configuration of the instruction decode stage and the instruction execution stage in the processor configuration example according to the embodiment of the present invention.
FIG. 7 is a functional block level configuration diagram showing the configuration of the write-back stage in the processor configuration example according to the embodiment of the present invention.
FIG. 8 is a functional block level configuration diagram showing the configuration of the bank switch means in the processor configuration example according to the embodiment of the present invention.

[Architecture embodiment]
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows an outline of the processor of the present invention. In the present invention, the registers used by the arithmetic unit are grouped into a plurality of units called n register banks from bank 0 to bank n−1, for example. A bank identifier is used to designate which of the register banks. The bank identifier is a number having an appropriate number of bits. For example, the bank identifier has a sufficient number of bits to express n. To specify any register in the processor, a bank identifier and a register address are specified.
The arithmetic unit performs an operation based on an instruction decoded by an instruction decoder (not shown). This command roughly includes two types of commands.
The first type of instruction is an instruction similar to an instruction in a normal processor. For example, instructions well known in the field of processors are included, such as a load instruction (mnemonic: LD) for loading data from an external memory, an addition (ADD) for performing addition, and a subtraction (SUB). In this specification, this instruction is referred to as a “normal instruction”.
The second type of instruction is an instruction for switching the register bank to be accessed. These are instructions unique to the present invention and are called register bank designation instructions. With this instruction, it is possible to determine which register bank is accessed by the arithmetic unit based on a normal instruction thereafter. For example, when the processor architecture uses two operands, it is possible to specify independently which register the first operand and the second operand access. The register bank designation command for switching the register bank is not particularly limited in its format. As an instruction of a normal stored program system, for example, an instruction having an explicit bank identifier as an operand (bank setting instruction) or a prefix (bank setting modification instruction) for switching the bank indicated by the operand of the immediately following instruction You can also.
An example of instructions in the assembler code for switching the bank is shown in FIG. A line 202 is one of bank setting instructions, and is a bank set instruction (mnemonic: BS) for designating a bank to be used in subsequent programs. B0 and B1, which are the first and second operands of the bank set instruction, represent bank 0 and bank 1, respectively. That is, line 202 is an instruction for setting the first operand (destination operand) to “bank 0” and the second operand (source operand) to “bank 1” in subsequent programs. As described above, the bank set instruction exemplified in the row 202 is an instruction constituted by the operation code corresponding to the mnemonic BS and the operand. The bank setting instruction represented by this bank set instruction allocates a register bank until the next bank setting instruction is explicitly specified. Note that it is arbitrary what register bank is set in the instruction line until the bank setting instruction explicitly appears in the program. Not accepting such an instruction because the bank is indefinite, assigning some default value to the bank (for example, all bank 0), processing all banks in parallel, Nation operands and source operands can be assigned separately.
A row 204 in FIG. 2 is a bank setting prefix (mnemonic: BP) that is valid only for the immediately following instruction. The bank setting prefix described in this example includes the bank identifier in the opcode itself, not as an operand. The bank setting prefix “BP10” is an instruction that affects only the following instruction (line 206) immediately after it, and sets the destination operand to bank 1 and the source operand to bank 0. That is, if i and j are subscripts representing bank identifiers, “BPij” sets the destination operand of the subsequent instruction to bank i and the source operand to bank j. Of course, as in the bank set instruction described above, an operation code and an operand representing a bank identifier may be used, and only the instruction line immediately after that may be affected. Since this bank setting prefix affects only the immediately following instruction, the bank assignment specified by the bank setting instruction is overwritten only temporarily. Then, in the instruction line (line 208) where the bank setting prefix does not affect, the designation of the bank designation instruction becomes valid again.
In the bank setting instruction, a register called a bank select register (not shown) that holds the bank setting at that time is prepared, and B0 and B1 can be used as these registers. The value of the bank select register can be referred to by the designation of a program by an explicit instruction. The contents of the back select register may be shared among subroutines as global variables, for example, or may be rewritten for each subroutine as local variables in a subroutine-structured program. If it is a local variable, it can be written and held in any general-purpose register or external memory configured in the memory bank by an appropriate data transfer instruction. The architecture of the present invention can include instructions that implement this transfer.
FIG. 3 schematically shows the operation of the register bank designation instruction in the program shown in FIG. Since the instruction (ADD) in line 206 is affected by the bank setting prefix BP10 in the immediately preceding line 204, R1 in bank 1 is used as the source operand, and R21 in bank 0 is used as the destination operand. The result of the sum of R21 is written back to R21. The instruction (SUB) in line 208 uses R2 in bank 0 as the source operand and R19 in bank 1 as the destination operand, as specified by the bank set instruction in line 202, from R2 to R19. Is subtracted and the result is written back to R19. Line 208 is not affected by the bank setting prefix of line 204. In FIG. 3, the “source register bank” and the “destination register bank” indicating the source operand are shown separately on the left and right of the drawing for the sake of understanding. Can be pointed to.
As described above, it is possible to switch the bank pointed to by the source operand and the destination operand with a small number of instructions in an arbitrary program composed of a sequence of instructions using a bank designation instruction. Further, by using a bank setting prefix or the like that is effective only for the immediately following instruction, it becomes possible to switch banks flexibly.
Moreover, although the case where the operand is two two-operand instructions is taken as an example, only the destination operand can be used when there is only one operand. Similarly, a bank setting instruction and a bank setting prefix can be defined even in a three-operand architecture using three operands.
The banks to be switched in this way are accessed by switching the bank to be accessed from the arithmetic unit in FIG. 1, and the external memory is accessed by the data transfer device 13, the internal bus 14, and the external bus 15 which are memory access means. be able to. The operation of the data transfer device 13 can be changed by a control signal based on a command.
Next, the instruction length of the present invention will be described. Hereinafter, 16 bits may be particularly referred to as one word.
FIG. 4 shows the instruction configuration of the present invention in a bit array. The normal instruction 402 in FIG. 4 is, for example, an instruction such as addition (ADD) or subtraction (SUB) described in FIG. 2, and is a normal instruction previously described as the first type of instruction. 2 corresponds to row 208 in FIG. For example, this instruction 412 is composed of an 8-bit opcode and two 4-bit operands, and has an instruction length of 16 bits.
4 includes a bank setting prefix 414 that is a bank setting modification instruction, and an instruction 415 that follows the bank setting prefix 414. The instruction 415 is a normal instruction. In FIG. 2, the bank setting modification command 404 is represented by two lines, a line 204 and a line 206. The instruction length is 16 bits for both the bank setting prefix 414 and the instruction 415, and the instruction 404 with bank setting modification is 32 bits (2 words) as a whole. Based on the bank setting modification instruction 404, a bank designation instruction is issued by the instruction decoder.
4 is, for example, a 16-bit bank setting instruction 416, and corresponds to the row 202 in FIG. For example, like a normal instruction, it includes a 4-bit bank setting instruction opcode and two 6-bit bank identifier operands each. Based on the bank setting instruction 406, a bank designation instruction is issued by the instruction decoder.
The setting of the instruction length of the bank setting instruction and the bank setting modification instruction as described above is particularly suitable when the operations that do not require the bank specifying instruction occupy the majority. In other words, when a bank designation instruction is issued, the instruction length is increased to 2 words, etc., and usually a short instruction such as 1 word (16 bits) is executed, except when register banks need to be switched. The instruction length can be shortened. As a result, it is possible to handle a large number of registers while enabling the program code to be shortened and the area of the processor to be reduced.
Note that there is no particular limitation as to what bank allocation is performed when any instruction is executed before the bank setting instruction explicitly appears. Do not accept such instructions because the bank is indefinite, assign all banks 0 using default bank assignment, process in parallel for all banks, destination It is possible to assign operands and source operands separately.
The present invention is not limited to the above-described one word and two word instructions. For example, the maximum instruction length can be 3 words. In this case, the second word can be a bank setting prefix and the third word can be a normal instruction, but the first word can be another prefix. As this prefix, for example, a conditional execution prefix can be used. This conditional execution prefix is a prefix that can switch whether or not to execute a subsequent instruction according to a determination condition without accompanying a branch instruction. With this prefix alone, branch instructions can be reduced and stalls associated with branch instructions during parallel processing can be avoided. In addition, when the conditional execution prefix and the register bank designation instruction of the present invention are used in combination, a program that can be processed in parallel with almost no stall can be written, so the processing speed is high while suppressing the instruction length. A processor can be realized. When the maximum instruction length is 2 words or 3 words and the last word is a register setting prefix, it is recognized as a general illegal instruction and is not processed.
As described above, according to the present invention, it is possible to handle a large number of registers by assigning a longer instruction length only to an instruction related to a register designation instruction while keeping the instruction length of the entire program short.
[Processor configuration example]
5 to 8 show a configuration example 101 of a processor that implements the architecture of the present invention for each part of a functional block level configuration diagram. FIG. 5 shows an instruction fetch stage, FIG. 6 shows an instruction decode stage and an instruction execution stage, and FIG. 7 shows a write back stage and a memory access stage included therein.
The instruction fetch stage of FIG. 5 includes an instruction fetch buffer 54 from an instruction storage means (not shown). The instruction fetch unit 52 for loading an instruction and the value of a program counter 58 for counting a program in progress. The fetch address unit 56 generates an address for accessing the instruction storage means.
The instruction decode stage in FIG. 6 decodes the instruction loaded as the instruction fetch buffer 54 into microcode (microinstruction) as a control signal, and decodes the prefix for the main decoder 62. A decoder including a prefix decoder 60 for output. In this configuration example, each instruction having an instruction length of 16 bits is sent to the decoder in units of 96 bits. When the main decoder is decoding an instruction, the instruction following the instruction is decoded by the prefix decoder 60. That is, the prefix decoder 60 pre-reads the instruction in advance, so that the prefix decoder 60 detects whether the instruction includes the prefix. When the prefix decoder 60 detects a prefix, it outputs a control signal to the main decoder 62 according to the contents of the prefix. By this control signal, the main decoder 60 switches the decoding operation for the instruction after the prefix. In this way, the prefix decoder and the main decoder cooperate to realize the prefix operation. If this prefix is the bank setting prefix of the present invention, the main decoder 62 switches the bank of registers used for the operand included in the instruction to be decoded immediately thereafter. As a result, the register holding the bank assignment of the register file (bank select register 66, FIG. 8) is changed. This register becomes the bank switch means of the present invention. As described above, by using the bank setting prefix, the register bank to which the operand of the subsequent instruction points is switched. That is, the prefix decoder and the main decoder can generate a microinstruction to be a bank designation instruction.
When a bank setting instruction such as a bank set instruction is used instead of the bank setting prefix, the bank setting instruction is decoded by the main decoder, the bank select register is rewritten, and the bank assignment of the register file is changed. As a result, the register bank indicated by the destination operand and the source operand in the subsequent instruction is switched.
The instruction decode stage further includes a register file 64 including a plurality of register banks of the present invention. In the present embodiment, the register bank is described as a data processing register arranged in four banks. Each register bank includes 16 data registers having a 64-bit length that can be specified by a 6-bit field in a normal instruction.
As described above, the instruction decode stage includes the bank select register 66 (FIG. 8). This bank select register holds the current bank assignment status by, for example, a bank set instruction.
The instruction execution stage includes a microcode (microinstruction) control device 610 that specifically executes the instruction decoded in the instruction decode stage, an arithmetic logic unit (ALU), a product-sum operation unit (MAU), and a data process. An arithmetic unit 68 including a unit (DPU) is included. The arithmetic unit 68 executes arithmetic processing designated by the immediate value, the register value in one of the register banks, etc. based on the microinstruction, and passes it to the write back stage.
The instruction decode stage and the instruction execution stage further include characteristic elements of the present invention. Source registers SRC0 and SRC1, which are part of the signal 601, and destination registers DST0 and DST1 are used as outputs from the register file. Among these, each port of the register file connected to the registers SRC0 and DST0 is used in a normal processor, and is connected to the arithmetic unit via the registers SRC0 and DST0. On the other hand, the port of the register file connected to the registers SRC1 and DST1 is a characteristic port of the present invention, and is stored in the store instruction execution unit 620 serving as an output to the external memory (not shown) via the registers SRC1 and DST1. It is connected. In this configuration example, two registers SRC1 and DST1 are described, but the present invention only needs to have at least one such register. The store instruction execution device 620 forms part of the memory access device of the present invention in cooperation with a memory output device 74 (FIG. 7) described later. As a result, the arithmetic unit accesses a part of the register banks of the register file having the register bank configuration via the registers SRC0 and DST0. The external memory can be accessed via In the above description, the processor configuration using microinstructions has been described. However, a hardware configuration can also be realized.
The write back stage of FIG. 7 includes a write back device 72 that writes back the output of the computing unit 68 to a register file, and a memory that includes a tristate driver that writes the output of the computing unit 68 as data to an external memory (not shown). The output device 74 has a memory input device 76 that reads data from the external memory and loads it into the register file 64. At this time, since the banks are different, the memory input device 76 can write data to the register file 64 in parallel with the write back stage.
FIG. 8 shows a configuration example of bank switch means not used in FIGS. 5 to 7 but used in the processor of the present invention. The bank switch means of this configuration example includes a bank select register 66, a register SRCB (84) included in an SSR (system status register) 82, which holds a register bank assigned to a source operand register, and a destination And a register DSTB (86) for holding a register bank assigned to the register of the operand. The bank select register 66 is a register ID, which holds a register bank assigned to each register of the source operand and the destination operand in the instruction decode stage. SRCB (84a) and ID. It consists of DSTB (86a).
First, the operation of these bank switch means will be described when the bank designation command is a bank setting command. A register ID directly rewritten from the main decoder 62. SRCB (84a) and ID. DSTB (86a) is rewritten without going through the instruction execution stage. For this reason, these hold the latest register bank and are used at the time of register read. The same register bank assignment is subsequently written to SRCB (84) and DSTB (86) in SSR 82 in the register file of the control register. When operated in this way, the register bank assignment already included in the instruction is reflected at the end of the instruction decode stage, so that the register bank can be assigned in a short time, for example, one clock. The register bank assignment becomes effective, and it is possible to determine for each source operand and destination operand which register bank in the register file 64 is to be accessed. Further, since this is written to the SSR 82 in the register file at the end of the write back stage, it is possible to hold the register bank assignment as the system status.
Next, a case where the bank designation command is a bank setting modification command and becomes a single command in combination with a normal command immediately after that will be described. In this case, since the bank setting modification instruction only affects the instruction immediately after that, there is no need to write the temporary assignment of the register bank to the SSR 82. Therefore, the bank select register 66 is rewritten at the instruction decode stage, but the written contents are not transmitted to the instruction execution stage and the write back stage. In this way, temporary bank assignment effective only for the normal instruction immediately after the bank setting modification instruction is realized.
With the processor configuration as described above, the register bank configured as the register bank of the present invention can be used. That is, a processor capable of implementing a register switching operation by a register bank setting instruction and an operation of switching a register at the operand point of a subsequent instruction by a register bank setting prefix is provided as specific hardware. In addition, the external memory can be accessed even during the operation of the arithmetic unit, and the stagnation of processing due to the memory latency can be prevented.
Although not shown in the figure, the memory output device 74 and the memory input device 76 can use a well-known cache memory to reduce latency caused by the external memory.
[Multiprocessor system configuration example]
A multiprocessor configuration can be realized by using a plurality of single processors described with reference to FIGS. At this time, the individual processors to be cooperated are connected to the instruction storage means. The instruction storage means stores instructions for causing each multiprocessor to cooperate. Each processor fetches only an instruction required by each processor at a fetch stage according to a program counter of each processor. The instruction of each processor can be a register bank setting instruction similar to that used in the single processor of the present invention or a register bank modification instruction.
The external memory may be accessed from some processors. That is, it is possible to configure the external memory as a shared memory system, share a certain data area in the external memory with a plurality of processors, and share registers among the processors. In this configuration, in order to access an external memory having a large latency, for example, a register that shares a value with another processor (hereinafter referred to as a “shared register”) and a register that is used only by each processor are separated. Can be assigned to a register bank. For example, each processor accesses a register bank including the shared register as a destination operand or a source operand only when performing an operation on the shared register, and accesses other register banks in other operations. The shared memory is accessed only when the shared register is rewritten. When the processors constituting the multiprocessor operate as described above, only the register rewrite result to be shared by the processors is accessed via the shared memory having a large latency. During the access to the shared memory, the arithmetic unit of each processor can execute an instruction that does not handle the shared register. As described above, the multiprocessor system including a plurality of processors according to the present invention realizes a multiprocessor system in which operations in each processor are hardly affected by the latency due to external memory access while guaranteeing data coherency.

Industrial applicability

With the processor configuration of the present invention, a large number of registers can be used while keeping the instruction length short. In addition, the stagnation of processing due to the memory latency can be prevented.
In the multiprocessor system including a plurality of processors according to the present invention, it is possible to realize a multiprocessor system in which operations in each processor are hardly affected by the latency due to external memory access while guaranteeing data coherency.

Claims (13)

An instruction decoder that decodes an instruction including a register bank designation instruction and a normal instruction to generate a control signal;
An arithmetic unit that performs arithmetic processing based on the control signal from the instruction decoder;
Memory access means for inputting / outputting data to / from an external memory based on a signal from the computing unit;
A plurality of register banks each having a register accessible from the computing unit and the memory access means;
Bank switching means controlled by a register bank designation control signal generated by the instruction decoder based on the register bank designation instruction, determining which register bank the computing unit accesses, and the memory access means And bank switch means for determining which register bank to access,
The register bank designation instruction is an instruction to switch a register bank to be assigned to a register used by an operand in order to execute a normal instruction after the register bank designation instruction using the operand by controlling the bank switch means. A processor having a multi-bank register. The bank switch means is controlled by the register bank designation control signal to determine which of the register banks the arithmetic unit accesses, and the memory access means accesses any of the other register banks. And
2. The processor according to claim 1, wherein the access to the register by the arithmetic unit and the access to the register by the memory access means can be performed simultaneously. The register bank designation instruction is a register bank setting modification instruction,
The register bank setting modification instruction controls the bank switch means to execute the normal instruction immediately after the register bank setting modification instruction using an operand, so that the normal instruction immediately after the register bank setting modification instruction is executed. The processor according to claim 1 or 2, which is an instruction for switching a register bank to be assigned to a register for an operand. When the register bank setting modification instruction is immediately preceding, the instruction length is extended from the instruction length of the normal instruction, and the register bank setting modification instruction and the immediately following normal instruction have the extended instruction length. 4. A processor according to claim 3, wherein the processor is one instruction. The register bank designation instruction is a register bank setting instruction,
In a normal instruction after the register bank setting instruction, the register bank assignment based on the register bank designation instruction is applied to the register used by the operand without requiring an explicit register bank designation. The processor according to claim 1 or 2. A multiprocessor system comprising at least an instruction storage means, a first processor, a second processor, and an external memory,
The first processor and the second processor are:
An instruction decoder that decodes an instruction including a register bank designation instruction from the instruction storage means and a normal instruction to generate a control signal;
An arithmetic unit that performs arithmetic processing based on the control signal from the instruction decoder;
Memory access means for inputting / outputting data to / from the external memory based on a signal from the computing unit;
A plurality of register banks each having a register accessible from the computing unit and the memory access means;
Bank switching means controlled by a register bank designation control signal generated by the instruction decoder based on the register bank designation instruction, determining which register bank the computing unit accesses, and the memory access means And bank switch means for determining which register bank to access,
The register bank designation instruction is an instruction to switch a register bank to be assigned to a register used by an operand in order to execute a normal instruction after the register bank designation instruction using the operand by controlling the bank switch means. And
The multiprocessor system, wherein the external memory is connected so as to be accessible from both the memory access means of the first processor and the memory access means of the second processor. The bank switch means is controlled by the register bank designation control signal to determine which of the register banks the arithmetic unit accesses, and the memory access means accesses any of the other register banks. And
7. The multiprocessor system according to claim 6, wherein access to the register by the arithmetic unit and access to the register by the memory access means can be performed simultaneously. 8. The multiprocessor system according to claim 6 or 7, wherein at least one of a memory area accessed by the first processor and a memory area accessed by the second processor in the external memory. A multiprocessor system with shared parts. An instruction decoder that decodes an instruction including a register bank designation instruction and a normal instruction to generate a control signal, an arithmetic unit that performs arithmetic processing based on the control signal from the instruction decoder, and a signal of the arithmetic unit A memory access means for inputting / outputting data to / from an external memory, a plurality of register banks each including the arithmetic unit and a register accessible from the memory access means, and the arithmetic unit and the memory access means. A control method of a processor comprising bank switch means for determining which register bank to access,
The instruction decoder generating a register bank designation control signal based on the register bank designation instruction;
By controlling the bank switch means with the register bank designation control signal, the register bank assigned to the register used by the operand of the normal instruction after the register bank designation instruction is switched, and the register bank is accessed by the computing unit. A step of controlling whether to
Switching the register bank assigned to the register used by the operand by controlling the bank switch means by the register bank designation control signal, and controlling which register bank the memory access means accesses;
A method for controlling a processor having a multi-bank register, comprising: executing the normal instruction using an operand. The step of executing the normal instruction with an operand comprises:
10. The multi-bank register according to claim 9, comprising a step in which an access to a register in a certain register bank by the arithmetic unit and an access by a memory access means to a register in another register bank are simultaneously performed. A method for controlling a processor having: The register bank designation instruction is a register bank setting modification instruction,
The register bank setting modification instruction controls the bank switch means to execute the normal instruction immediately after the register bank setting modification instruction using an operand, so that the normal instruction immediately after the register bank setting modification instruction is executed. The method for controlling a processor according to claim 9 or 10, wherein the instruction is an instruction for switching a register bank assigned to a register of the operand. When the register bank setting modification instruction is immediately preceding, the instruction length is extended from the instruction length of the normal instruction, and the register bank setting modification instruction and the immediately following normal instruction have the extended instruction length. 12. The method of controlling a processor according to claim 11, wherein the instruction is a single instruction. The register bank designation instruction is a register bank setting instruction,
In a normal instruction after the register bank designation instruction, register bank allocation based on the register bank designation instruction is applied to a register used by the operand without requiring an explicit register bank designation. A method for controlling a processor according to claim 9 or 10.

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