JPS6432723A - Divider - Google Patents

Divider

Info

Publication number
JPS6432723A
JPS6432723A JP62189272A JP18927287A JPS6432723A JP S6432723 A JPS6432723 A JP S6432723A JP 62189272 A JP62189272 A JP 62189272A JP 18927287 A JP18927287 A JP 18927287A JP S6432723 A JPS6432723 A JP S6432723A
Authority
JP
Japan
Prior art keywords
matrix
multiplier
adder
modulus
executes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62189272A
Other languages
Japanese (ja)
Inventor
Chiyoko Matsumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62189272A priority Critical patent/JPS6432723A/en
Publication of JPS6432723A publication Critical patent/JPS6432723A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To simplify a circuit constitution by providing a matrix arithmetic means to execute the dividing of the elements of a vector-represented GF(2<m>) as an mXn matrix operation on a GF(2). CONSTITUTION:A modulus 2 adder 8 executes an exclusive logic (exclusive.OR) operation, and a multiplier 9 executes a logic production 9 (AND) operation. Respective elements of 4X4 matrix by A=(a3, a2, a1, a0) are obtained, further, a matrix multiplaying with B=(b3, b2, b1, b0) is executed, and C=(c3, c2, c1, c0) is obtained. Thus, a ROM, which is necessary for obtaining an inverse number, can be replaced with a circuit to use only the modulus 2 adder and the multiplier on the GF(2).
JP62189272A 1987-07-29 1987-07-29 Divider Pending JPS6432723A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62189272A JPS6432723A (en) 1987-07-29 1987-07-29 Divider

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62189272A JPS6432723A (en) 1987-07-29 1987-07-29 Divider

Publications (1)

Publication Number Publication Date
JPS6432723A true JPS6432723A (en) 1989-02-02

Family

ID=16238540

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62189272A Pending JPS6432723A (en) 1987-07-29 1987-07-29 Divider

Country Status (1)

Country Link
JP (1) JPS6432723A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007501965A (en) * 2003-05-16 2007-02-01 アナログ デバイシーズ インク Compound Galois field engine and Galois field divider and square root engine and method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007501965A (en) * 2003-05-16 2007-02-01 アナログ デバイシーズ インク Compound Galois field engine and Galois field divider and square root engine and method
JP2010102352A (en) * 2003-05-16 2010-05-06 Analog Devices Inc Compound galois field engine and galois field divider and square root engine and method

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