JPS6382015A - Toothless clock generating circuit - Google Patents

Abstract

PURPOSE:To reduce the jitters of a D-VCO master clock by generating switching control pulses by using a 2nd master clock which is 180 deg. out of phase at the same frequency, and substituting a 1st two master clocks with the 2nd one master clock. CONSTITUTION:When a '0'-phase and a pi-phase master clock generated by an LSI master clock except in a D-PLL circuit are inputted to a toothless clock generating circuit, the former is applied to an N-scale counter 6, a switch 91, and a D-type flip-flop 82 and the latter is applied to the D-FF 81 and switch 91. When the counted value of the N-scale counter is between '0' and '1', two '0'-phase clocks are substituted with one pi-phase master clock. Consequent ly, the frequency of the '0'-phase master clock is f(N-1)/N and T' of an equa tion (T'/T)X360=360 deg. (T': time of movement of leading edge, T: time of one cycle) becomes (1/2)T, so the jitters are at 180 deg. and the D-VCO master clock where the jitters are reduced is supplied to the D-VCO.

Description

[Detailed Description of the Invention] [Summary] Tooth extraction is performed in a clock generation circuit using the output of an N-ary counter, a first master clock, and a second master clock that has the same frequency as this clock and a phase difference of π. The generated switching control pulse controls the switching means to switch the two first
By replacing the master clock with one second master clock and outputting the second master clock, the frequency of the first master clock is lowered and jitter is reduced.

[Industrial application field]

The present invention relates to an improvement in a clock generation circuit, for example, a clock generation circuit included in a digital phase synchronization circuit portion of an LSI for a car telephone.

FIG. 4 shows a block diagram of the digital phase synchronization circuit.

In the figure, an LSI master clock with frequency f is input to a digital phase locked circuit (hereinafter abbreviated as D-PLL), and this master clock is used by a digital voltage controlled oscillator (hereinafter abbreviated as O-VCO) 4. Since the frequency is higher than that of the frequency, the clock generating circuit 1 periodically removes the pulses (hereinafter abbreviated as "toothless") to reduce the frequency to the normal frequency.

And, the D-VCO Master Kurofuku, who has lost his teeth, is D
- It is applied to the VCO 4, divided by i, and further divided by the 1 frequency divider 5, and then output as an output signal, and the phase is compared with the input signal by the 1 phase comparator 2, and the phase is delayed or advanced. The comparison result information is integrated by integrator 3, and D-V
Control CO4.

Here, the D-VCO normally divides the D-VCO master clock and outputs it, but the frequency is divided by (M + 1) only once when the integrator output exceeds a predetermined threshold. Alternatively, an attempt is made to make the phase difference between the input signal and the output signal 0 by sending out the frequency-divided output by (M-1).

At this time, tooth extraction is performed from clock generation circuit 1 to D with jitter.
- When the VCO master clock is input, a jittery output signal is sent from the D-PLL circuit, which may cause other circuits that use this output signal to malfunction.
- It is necessary that the jitter of the VCO master clock is small.

[Conventional technology]

FIG. 5 is a block diagram of a conventional example, and FIG. 6 is a time chart of FIG. 5. The operation shown in FIG. 5 will be explained below with reference to FIG. Note that the numbers on the left side of FIG. 6 indicate the waveforms of the portions with the same numbers in FIG.

First, when an LSI master clock with a frequency f as shown in Figure 6-■ is input, the N-ary counter 6 starts counting from 0, and when the count value reaches (N - 1), the
A pull carry is output to the OR circuit 7 as shown in (2).

Well, as shown in Figure 6-○, the LSI master clock in the part where the count value is 0 is masked, and the frequency becomes f・(N
-1)/N is obtained. Note that f is the frequency of the LSI master clock.

[Problem that the invention seeks to solve]

Here, since the next rising edge after the 6 rising edges in FIG. 6 is not 4 points but point B, the jitter at this time is as follows.

(T'/T) X360 = 360 degrees (1)T
' is the time the rising edge moves from A to B.

T is the time of one cycle.

In other words, since one clock is removed, the D-VCO master clock with 360 degrees of jitter is input to D-VCO4, so the D-PLL circuit, which should originally absorb jitter, sends out a clock with jitter added. become.

Therefore, there is a problem in that the jitter of the O-VCO master clock must be reduced.

[Means for solving problems]

The above problem can be solved by the clock generation circuit shown in FIG. 6 is an N-ary counter that counts the first master clock; 8 is the output of the N-ary counter;
A switching control pulse generating means generates a switching control pulse using the first master clock and a second master clock having the same frequency as the first master clock and a phase difference of 180 degrees.

Further, reference numeral 9 indicates the first signal by the output of the switching control pulse generating means.
This is a switching means for switching and outputting the master clock and the second master clock.

[Effect]

The present invention provides switching control pulse generation means using a first master clock, an output from an N-ary counter 6 that counts this clock, and a second master clock that has the same frequency as the first master clock but has a phase difference of 180 degrees. generates a switching control pulse, and drives the switching means with this pulse to
The two master clocks are replaced with one second master clock.

Therefore, since the second master clock is inserted in the center of the first master clock, the jitter is reduced by half, and since one first master clock is removed, the frequency of this clock is reduced. .

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a time chart of FIG. 2. The numbers on the left side indicate the waveforms of the portions with the same numbers in FIG. It should be noted that the same reference numerals refer to the same objects throughout the plan, and D-type flip-flops 81, 82, . The OR circuit 83 represents a component of the switching control pulse generating means 8, and the switch 91 represents a component of the switching means 9.

Hereinafter, the operation of FIG. 2 will be described with reference to FIG. 3, assuming that the first master clock is a 0-phase master clock and the second master clock is a π-phase master clock.

First, when the 0-phase and π-phase master clocks shown in FIG. The latter is a D-type flip-flop (abbreviated as D-FF) 82;
It is added to F81 and switch 91.

Therefore, the N-ary counter starts counting up from O, and when the count value reaches (N - 1), it sends ripple carry to the D-FF81 as shown in Figure 3-0, so the π-phase master An output that changes from 1 at the rising edge of the clock to 0 at the first rising edge is sent to the OR circuit 83 and the D-FF 82 (see FIG. 3--).

Next, as shown in FIG. 3-■, the output of the D-FF 82 changes to 1 at the rising edge of the O-phase master clock and returns to 0 at the falling edge, and is sent to the OR circuit 83. The output shown in FIG. 3-0 is applied to the switch 91, and only during this time, the π-phase master clock is output instead of the 0-phase master clock as shown in FIG. 3-2.

That is, when the count value of the N-ary counter is between 0 and 1, two O-phase master clocks are replaced with one π-phase master clock. As a result, the frequency of the 0-phase master clock becomes f(
N-1)/N, and T' of (1) 2 above becomes (1
/2) T, so the jitter is 180 degrees, and the D-VCO master clock with reduced jitter is supplied to the D-VCO.

〔Effect of the invention〕

As described in detail above, according to the present invention, there is an effect that the jitter of the D-vCO master crofter supplied to the D-VCO is reduced.

As a result, the output signal sent out from the D-PLL has less jitter, and malfunctions of other circuits that utilize this signal are reduced.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is a time chart of Fig. 2, Fig. 4 is a block diagram of a digital phase synchronization circuit, Fig. 5 is a block diagram of a conventional example, and FIG. 6 shows a time chart of FIG. 5. In the figure, 6 is an N-ary counter, 8 is a switching control pulse generating means, and 9 is a switching means. Sword ＼ Planning January cr) Awa! Bron 20 Haya 12 Bo plot moon eji (μ&example 0 b0n 2 (i) Kaya 2 mouths

Claims (1)

[Claims] An N-ary (N indicates an integer) counter (6) that counts a first master clock, an output of the N-ary counter, the first master clock, and the first master clock. a switching control pulse generating means (8) for generating a switching control pulse using a second master clock having the same frequency and a phase difference of 180 degrees; 1. A clock generation circuit comprising a switching means (9) for switching and outputting a second master clock.