JPS63269236A - Performance testing system for multiplexing computer system - Google Patents

Performance testing system for multiplexing computer system

Info

Publication number
JPS63269236A
JPS63269236A JP62103047A JP10304787A JPS63269236A JP S63269236 A JPS63269236 A JP S63269236A JP 62103047 A JP62103047 A JP 62103047A JP 10304787 A JP10304787 A JP 10304787A JP S63269236 A JPS63269236 A JP S63269236A
Authority
JP
Japan
Prior art keywords
computer
information
external information
performance test
dma area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62103047A
Other languages
Japanese (ja)
Inventor
Kunisumi Kasahara
笠原 邦純
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62103047A priority Critical patent/JPS63269236A/en
Publication of JPS63269236A publication Critical patent/JPS63269236A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To execute the performance test in the actual operating state by using one computer as a performance testing computer and using the other as a simulation signal generating computer to simulate the state change. CONSTITUTION:A simulation signal generating computer 3 obtains external information from equipment information preliminarily defined by a data base 1 and outputs it to a DMA area 7. A computer interface device 11 periodically reads in information of the DMA area 7 and transmits it to a computer interface device 10, and external information is written in a DMA area 6 and is transmitted to a performance testing computer 2. In this case, the computer interface device 10 compares external information with transmission information read from the DMA area 6 for the computer 2 and sends a signal to the computer 2 at the time of detecting the change, and the computer 2 recognizes the state change of a power system by an interruption signal to execute the actual work, thus executing the performance test.

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は電力系統監視制御などに用いられる多重化計算
機システムの性能試験方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a performance testing method for a multiplexed computer system used for power system monitoring and control.

(従来の技術) 従来、電力系統監視制御システム等における性能試験で
は、遠方監視制御装置等からの外部情報の作成及び、状
態変化の割込信号の模擬を計算機内臓型で行うのが一般
であった。つまり、実運用状態で性能試験を行おうとす
る計算機内にて、遠方監視制御装置等から受信する外部
情報を作成し外部情報の変化によって発生する割込信号
を模擬することにより実運用状態相当の環境をつくり、
各業務を遂行させ、計算機性能を求めていた。
(Prior art) Conventionally, in performance tests of power system monitoring and control systems, etc., it has been common to create external information from remote monitoring and control equipment, etc., and to simulate interrupt signals for state changes using a built-in computer. Ta. In other words, by creating external information received from a remote monitoring and control device, etc. in a computer that is performing a performance test under actual operating conditions, and simulating interrupt signals generated by changes in external information, Create an environment
They were required to carry out various tasks and required computer performance.

(発明が解決しようとする問題点) 上述した従来方式によれば、実運用状態相当の環境をつ
くるので遠方監視制御装置等から受信すべき外部情報を
作成したり、外部情報の変化によって発生する割込信号
を模擬する演算処理が付加されること自体実運用と異な
っている。また外部情報を計算機内にて模擬することよ
り実際の外部情報の変化によって発生する割込信号が外
部機器より伝わらないので実運用とは異なった運用状態
となり、正確な計算機性能試験が行えなかった。
(Problems to be Solved by the Invention) According to the conventional method described above, since an environment equivalent to the actual operating state is created, external information to be received from a remote monitoring and control device, etc. is created, and problems occur due to changes in external information. The addition of arithmetic processing to simulate interrupt signals is itself different from actual operation. Furthermore, by simulating external information within the computer, interrupt signals generated by changes in actual external information were not transmitted from the external equipment, resulting in an operating state that was different from actual operation, making it impossible to perform accurate computer performance tests. .

よって本発明は一方の模擬系の計算機にて外部情報を作
成し、他方の試験系の計算機へ伝送することにより割込
信号の発生と外部情報の状態変化を模擬し、実運用状態
と同等で正確な計算機性能を得るための試験装置を提供
することを目的としている。
Therefore, the present invention creates external information on one simulation system computer and transmits it to the other test system computer, thereby simulating the generation of an interrupt signal and the state change of the external information, which is equivalent to the actual operating state. The purpose is to provide testing equipment to obtain accurate computer performance.

〔発明の構成〕[Structure of the invention]

(問題点を解決するための手段) あらかじめ定義した設備情報を同じく有する多重化計算
機システムのそれぞれの系の間で遠方監視制御装置を経
由して情報伝送できる構成をとり模擬系から試験系へ外
部情報を伝送できるようにする。
(Means for solving the problem) A configuration is established in which information can be transmitted via a remote monitoring and control device between each system of a multiplexed computer system that has the same predefined equipment information, and external information is transmitted from the simulation system to the test system. Allow information to be transmitted.

(作 用) 模擬系にてあらかじめ定義した設備情報より、外部情報
を作成し変化させながら遠方監視制御装置へこの外部情
報を送出しさらに遠方監視制御装置から試験系へ作成し
た外部情報を送出する。これにより、あたかも遠方監視
制御装置から収集する外部情報を受信したのと同様に動
作する性能試験ができる。
(Function) External information is created from the equipment information predefined in the simulation system, and this external information is sent to the remote monitoring and control device while changing.Furthermore, the created external information is sent from the remote monitoring and control device to the test system. . This allows a performance test that operates as if it were receiving external information collected from a remote monitoring and control device.

(実施例) 以下図面を参照して実施例を説明する。第1図は本発明
による多重化計算機システムにおける性能試験方式を説
明する一実施例の構成図である。
(Example) An example will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment for explaining a performance test method in a multiplexed computer system according to the present invention.

第1図において1は遠方監視制御装置から入力される外
部情報の妥当性を判別するための情報等があらかじめ定
義された設備情報を格納するデータベース、2は実業務
運用状態での計算機性能を測定する性能試験計算機、3
は遠方監視制御装置から入力される外部情報を模擬する
模擬信号発生計算機である。4,5は計算機2及び計算
機3にそれぞれ接続されたローカルメモリー、6,7は
遠方監視制御装置からの書込み及び読込み可能なダイレ
クト・メモリー・アクセス領域(以下DMA領域と称す
)8,9は計算機2及び計算機3用のダイレクト・メモ
リー・アクセスバス(以下DMAバスと称す)である、
 20は遠方監視制御装置、10゜11は計算機とのイ
ンターフェイス装置、12は電力系統機器を制御するた
めの伝送制御装置、13.14は計算機2及び計算機3
用の伝送システムバス、15はその伝送システムバスの
切換装置、16は電力系統機器との間の伝送路である。
In Figure 1, 1 is a database that stores equipment information in which information for determining the validity of external information input from a remote monitoring and control device is defined in advance, and 2 is a database that measures computer performance under actual business operation conditions. performance test calculator, 3
is a simulated signal generation computer that simulates external information input from a remote monitoring and control device. 4 and 5 are local memories connected to the computers 2 and 3, respectively; 6 and 7 are direct memory access areas (hereinafter referred to as DMA areas) that can be written and read from remote monitoring and control equipment; 8 and 9 are the computers. A direct memory access bus (hereinafter referred to as DMA bus) for 2 and computer 3,
20 is a remote monitoring control device, 10°11 is an interface device with a computer, 12 is a transmission control device for controlling power system equipment, and 13.14 is a computer 2 and a computer 3.
15 is a switching device for the transmission system bus, and 16 is a transmission path between the transmission system bus and power system equipment.

この伝送システムバス切換装置15は計算機2の性能試
験を行う際伝送システムバス13側切替え、計算機イン
ターフェイス装置10と11の間で伝送可能な構成とす
る。つまり、通常は伝送路16から伝送制御装置12を
介して送られてきた外部情報は伝送システム13.14
を介して計算機インターフェイス装置10.11にてそ
れぞれの計算機2,3へ送られる(これを上りという)
The transmission system bus switching device 15 is configured to switch to the transmission system bus 13 side when performing a performance test of the computer 2 and to enable transmission between the computer interface devices 10 and 11. In other words, normally the external information sent from the transmission path 16 via the transmission control device 12 is transferred to the transmission system 13.14.
are sent to the respective computers 2 and 3 via computer interface devices 10 and 11 (this is called upstream).
.

しかしこの切替えにより性能試験計算機2側の伝送シス
テムバス13には伝送制御装置12から入力される外部
情報と同様に模擬された情報が模擬信号発生計算機3か
ら送出(これを下りという)できるようになる。なお、
計算機インターフェイス装置10は、外部情報をDMA
領域6に書込む場合、DMA領域6の情報と新しく伝送
されてきた外部情報との比較により、外部情報に状態変
化があるとき性能試験計算機2に対して割込信号により
通知する。
However, due to this switching, simulated information similar to the external information input from the transmission control device 12 can be sent from the simulated signal generation computer 3 to the transmission system bus 13 on the performance test computer 2 side (this is called downstream). Become. In addition,
The computer interface device 10 converts external information into DMA
When writing to the area 6, the information in the DMA area 6 is compared with the newly transmitted external information, and if there is a state change in the external information, the performance test computer 2 is notified by an interrupt signal.

次に作用について説明する。模擬信号発生計算機3は、
データベース1よりあらかじめ定義された設備情報を得
る。この設備情報の中には、伝送情報の並びに対し、各
データの種別情報・妥当性判別情報が含まれている。デ
ータの種別情報とは、伝送における制御情報、0N10
FFを示す2値情報あるいはアナログデータの様な数値
情報を示す情報であり、妥当性判別情報とは数値情報に
おける定常範囲を示す上限値・下限値情報である6以上
で示した設備情報をもとにして定常状態での伝送情報を
作成する。例えば、2値情報においては定常状態パター
ンの設定や数値情報においては上限値と下限値の中間値
といったぐあいである。さらに一定周期毎に数値情報を
変化させたり、異常状態に変化させたりして、状態変化
を模擬する。また2値情報については系統事故時の状態
変化等を模擬する。模擬信号発生計算機3は1以上の様
にして求めた外部情報をローカルメモリー5の中にもう
けられたDMA領域7に出力する。
Next, the effect will be explained. The simulated signal generation computer 3 is
Obtain predefined equipment information from database 1. This equipment information includes type information and validity determination information of each data for the transmission information array. Data type information refers to control information in transmission, 0N10
This is information that indicates binary information indicating FF or numerical information such as analog data, and validity determination information also includes equipment information indicated by 6 or higher, which is upper and lower limit value information that indicates a steady range in numerical information. transmission information in a steady state is created. For example, in the case of binary information, a steady state pattern is set, and in the case of numerical information, it is set as an intermediate value between an upper limit value and a lower limit value. Furthermore, the numerical information is changed at regular intervals, or the state is changed to an abnormal state, thereby simulating a state change. In addition, for binary information, changes in status at the time of a system fault are simulated. The simulated signal generation computer 3 outputs the external information obtained as described above to the DMA area 7 provided in the local memory 5.

次に計算機インターフェイス装置11は、1定周期毎に
DMAバス9を介してDMA領域7の情報を読込み、伝
送システムバス13へ送出し、計算機インターフェイス
装置10へ伝送する。計算機インターフェイス装置10
は、伝送システムバス13より読込んだ外部情報をDM
Aバス8を介して性能試験計算機用ローカルメモリー4
の中にもうけたDMA領域6に書込む。こうして模擬信
号発生計算機3にて作成された外部情報が性能試験計算
機2に伝送される。この際計算機インターフェイス装置
10は、伝送システムバス13より読込んだ外部情報と
前回性能試験計算機2用のDMA領域6より読込んだ伝
送情報とを比較し、外部情報に変化があった場合はDM
Aバス8を介して性能状計算機2に信号を伝送する。性
能試験計算機2は、こうして得られた割込信号にて電力
系統の状態変化を認識し、ローカルメモリー4内にもう
けられたDMA領域6の外部情報を読込み電力系統の状
態を識別し、電力系統の監視等の実業務を遂行し性能試
験が行われる。
Next, the computer interface device 11 reads the information in the DMA area 7 via the DMA bus 9 at regular intervals, sends it to the transmission system bus 13, and transmits it to the computer interface device 10. Computer interface device 10
DM the external information read from the transmission system bus 13.
Local memory 4 for performance test computer via A bus 8
Write to the DMA area 6 created in the . In this way, the external information created by the simulated signal generation computer 3 is transmitted to the performance test computer 2. At this time, the computer interface device 10 compares the external information read from the transmission system bus 13 with the transmission information read from the DMA area 6 for the previous performance test computer 2, and if there is a change in the external information, the DM
The signal is transmitted to the performance calculator 2 via the A bus 8. The performance test computer 2 recognizes the change in the state of the power system based on the interrupt signal obtained in this way, reads external information in the DMA area 6 created in the local memory 4, identifies the state of the power system, and changes the state of the power system. Performance tests will be conducted by performing actual tasks such as monitoring.

以上の様に、模擬信号発生計算機3にて電力系統の状態
を示す外部情報を刻々と変化させることにより、性能試
験計算機2では電力系統機器より遠方監視制御装置20
を介して伝送される外部情報と同様の状態にて計算機性
能試験ができる。また。
As described above, by constantly changing the external information indicating the state of the power system in the simulated signal generation computer 3, the performance test computer 2
Computer performance tests can be performed under the same conditions as external information transmitted via . Also.

模擬信号発生計算機3にて模擬する状態変化率を調整す
ることにより、性能試験計算機2に発生する割込信号の
数を変更することができ、容易に割込信号発生率に対す
る計算機性能試験が可能となる。
By adjusting the state change rate simulated by the simulated signal generation computer 3, the number of interrupt signals generated in the performance test computer 2 can be changed, making it possible to easily perform computer performance tests on the interrupt signal generation rate. becomes.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く、本発明によれば多重化計算機システ
ムにおける計算機性能試験において一方の計算機を性能
試験計算機、他方の計算機を模擬信号発生計算機とし、
状態変化を模擬することにより容易に正確な実運用状態
での性能試験が可能となる。
As explained above, according to the present invention, in a computer performance test in a multiplexed computer system, one computer is used as a performance test computer, the other computer is used as a simulated signal generation computer,
By simulating state changes, it becomes possible to easily perform accurate performance tests under actual operating conditions.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は1本発明による多重化計算機システムにおける
試験装置を示す一実施例の構成図である。 1・・・データベース 2・・・性能試験計算機 3・・・模擬信号発生計算機 4.5・・・ローカルメモリー 6.7・・・DMA領域 8.9・・・DMAバス 10.11・・・インターフェスイ装置12・・・伝送
制御装置 13.14・・・伝送システムバス 15・・・伝送システムバス切換装置 16・・・伝送路 20・・・遠方監視制御装置 代理人 弁理士 則 近 憲 佑 同    第子丸   健 第1図
FIG. 1 is a block diagram of an embodiment of a test device in a multiplexed computer system according to the present invention. 1... Database 2... Performance test computer 3... Simulated signal generation computer 4.5... Local memory 6.7... DMA area 8.9... DMA bus 10.11... Interface device 12...Transmission control device 13.14...Transmission system bus 15...Transmission system bus switching device 16...Transmission line 20...Remote monitoring control device agent Patent attorney Nori Chika Ken Yudo Daishimaru Ken Diagram 1

Claims (1)

【特許請求の範囲】 外部情報を取込み演算業務を遂行する多重化計算機シス
テムにおいて、 一方の計算機にて予め定められた設備情報などにより性
能試験を行う計算機が入力する前記外部情報を作成し、 他方の性能試験を行う計算機が作成された前記外部情報
を取込み実際の演算業務同様に遂行して性能試験を行う
ことを特徴とする多重化計算機システムの性能試験方式
[Claims] In a multiplexed computer system that takes in external information and performs arithmetic operations, one computer creates the external information to be input by a computer performing a performance test based on predetermined equipment information, and the other computer 1. A performance test method for a multiplexed computer system, characterized in that a computer that performs a performance test takes in the created external information and performs a performance test in the same way as an actual calculation task.
JP62103047A 1987-04-28 1987-04-28 Performance testing system for multiplexing computer system Pending JPS63269236A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62103047A JPS63269236A (en) 1987-04-28 1987-04-28 Performance testing system for multiplexing computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62103047A JPS63269236A (en) 1987-04-28 1987-04-28 Performance testing system for multiplexing computer system

Publications (1)

Publication Number Publication Date
JPS63269236A true JPS63269236A (en) 1988-11-07

Family

ID=14343756

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62103047A Pending JPS63269236A (en) 1987-04-28 1987-04-28 Performance testing system for multiplexing computer system

Country Status (1)

Country Link
JP (1) JPS63269236A (en)

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