JPS632488B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog-to-digital converter using a double integration method, and an object of the present invention is to provide a converter that can convert multi-channel analog input into digital signals at high speed. do.

FIG. 1 is a connection diagram of a conventional analog-to-digital converter using a double integration method for converting multi-channel analog input into digital signals, and FIG. 3 is an operating waveform diagram thereof. As is well known, analog-to-digital conversion using the double integration method is performed using an integrator IG consisting of an amplifier A, a capacitor C, and an input resistor _RI , a reference voltage source ± _ES , and a comparator COMP, as shown in Figure 1. In the case of multi-channel, a multiplexer MP is added to this. S _I , S _- , S ₊ , and S _R are analog switches, and these switches are shown in Figure 3 (b),
It is turned on and off at the time intervals shown in c and d. _t1 ,
t ₂ , ... indicate the elapsed time. _The analog input _EX1 of _the first channel ch ₁ selected by the multiplexer MP is integrator
It is integrated by IG. After time _t2 , integrator IG integrates the reference voltage _-ES , and when integrator IG returns to its original level at time _t3 , comparator COMP detects it. The output of the integrator IG is shown by A in FIG.
Digital _{conversion of the input E} be exposed. Then the integrator
IG integrates the reference voltage -E _S during the period from _t3 to t3 _' . The period from t ₂ to t ₃ ', that is, the period during which the reference voltage -E _S is applied to the integrator IG, is set to a constant value, and during this period the integrator IG is integrating the input E _X1 . It is selected to be equal to or larger than the period t ₁ -t ₂ . After the time t ₃ ' has elapsed, the integrator IG is reset and now the second
Input _EX2 of channel ch ₂ is selected. Input _E
The integrator IG integrates the reference voltage −E _S for a period from t ₄ to t ₅ and then for a certain period from t ₅ to t ₆ ′. Second
The digital conversion of the channel input _EX2 takes place during the periods t ₅ and t ₆ . Similarly, the integration of the input E _X and the reference voltage E _S are performed alternately, and the reference voltage E _S
A digital conversion of that channel is performed within the integration period of . In addition, in Figure 1, SR is an integrator.
This shows the IG reset switch.

As described above, in the conventional double-integration type analog-to-digital converter, no digital conversion operation is performed while the input to be converted _EX is being integrated. This input integration time to be converted is selected to be an integral multiple of the power supply cycle in order to provide integrality with respect to the wraparound from the power supply. Therefore, although double-integration type analog-to-digital converters are resistant to power supply noise, they have the disadvantage that the number of analog-to-digital conversions that can be processed per unit time (for example, 1 second) is small. As a result, it is not necessarily satisfactory as an analog-to-digital converter for devices such as data loggers that have a large number of channels to be converted.

The present invention solves the above-mentioned problems by using the period during which the input to be converted _EX is being integrated for digital conversion processing.

FIG. 2 is a block diagram of one embodiment of the analog-to-digital converter of the present invention.
IG ₂ and analog switches S _S1 , S _I2 , S _S2 , and S _C are added. Each switch is turned on and off at time intervals C to F and J to N in FIG. 4, and the outputs of the integrators IG ₁ and IG ₂ are shown in A and B in FIG. That is, the switch SI ₁ is turned on (the other switches are OFF, and S _C is connected to "0") between time t ₁ and _{t 2} , and the input E _X1 of the first channel ch ₁ is connected to the integrator.
Integrate with IG ₁ . After the time t ₁ to _{t 2} has elapsed, the switch
SI ₁ is turned off, S _S1 and S _- are turned on, and S _C is connected to "1", and the reference voltage - E _S is set for a fixed time period t ₂ to t ₃ ' that is longer or equal to t ₁ to _{t 2} , It is given to the integrator IG ₁ and integrated. The output of the integrator _IG1 returns to its original level at time _t3 , which is detected by the comparator COMP. Digital conversion of the input _EX1 of the first channel ch ₁ is performed by counting clock pulses between t ₂ and _{t 3} as shown in FIG. 4. On the other hand, during the time t ₂ to t ₂ ′, the integrator IG ₂ is reset, and then the switch SI 2 is turned on for the period t ₂ ′ to t ₃ ′ (equal to t ₁ to t ₂ ), and the integrator IG ₂ is reset _. integrate the input E _X2 of the second channel ch ₂ . Therefore, the period during which this input E _X2 is integrated is performed within the period t ₂ to _{t 3} ' during which the reference voltage - E _S of the first channel ch ₁ is integrated. After the time t ₂ ′ to t ₃ ′ has elapsed, the next time
From t ₃ ' to t ₅ , the switch SI ₂ is turned off, S _S2 and S _- are turned on, and S _C is connected to "0", and the reference voltage -E _S is integrated by the integrator IG ₂ . This period from t ₃ ′ to t ₅ is the same as the above-mentioned t ₂
is equal to ~t ₃ ′. Integrator IG ₂ returns to original level in time
Returns at t ₅ ', which is detected by the comparator COM. Digital conversion _{of the input E} Next, reset the integrator IG ₁ for the time t ₃ ' to t ₄ and then for the time t ₁ to _{t 2} , t 4 to t 2 , which is equal to t ₂ ' to _{t 3 '} .
Switch S _I1 is turned on for t ₅ and integrator IG ₁
Integrate the input E _X3 of channel ch ₃ . Therefore, the integration of this input E _X3 is performed within the period t ₃ ' to _{t 5} during which the reference voltage -E _S of the second channel ch ₂ is integrated. After time t ₄ to t ₅ has elapsed, switch SI ₁ is turned off, S _S1 and S _- are turned on, and S _C is set to "1" for a period of t ₅ to _{t 6} '.
Connect to the integrator IG ₁ to integrate the reference voltage - E _S. This period t ₅ to _{t 6} ′ is the same as the above-mentioned t ₂ to _{t 3} ′, t ₃ ′ to _{t 5}
is equal to The output of the integrator IG ₁ returns to the original level in time
Returns at t ₆ , which is detected by the comparator COM. Digital conversion of the third channel ch ₃ is performed by counting the period from t ₅ to _{t 6} using clock pulses, as shown in FIG. 4. Similarly, during the period _from t ₅ to _{t 6} ' when the integrator IG ₁ integrates the reference voltage - E _S of the third channel ch ₃ , the integrator IG ₂ integrates the reference voltage _-E Integrate.
The same process is repeated thereafter.

In this way, in the present invention, two integrators are used in a double-integration type analog-to-digital converter, and during the period when one integrator is integrating the reference voltage for the input to be converted of one channel, the other integrator Since the integrator is configured to integrate the input to be converted of the next channel and this is performed alternately, the idle time for digital conversion is shortened. Therefore, even if the integration time of the input to be converted is an integral multiple of the power supply period and the period of the clock pulse is the same as that of the conventional converter, digital processing can be performed approximately twice as much as the conversion operation of the conventional converter. Therefore, the analog-to-digital converter of the present invention is suitable for use in equipment that handles multi-channel input, such as a data logger. Furthermore, although the converter of the present invention has more integrators and analog switches than the converter shown in FIG.
Since components that require precision such as R _I , R _S , and reference power supply ±E _S are shared, it can be realized without a significant increase in cost.

In addition, in the case of the analog-to-digital converter according to the present invention, the capacitors C ₁ and C ₂ of the integrators IG ₁ and IG ₂
The capacitance difference is not related to the count number of digital conversion, and the count difference due to the offset of integrators IG ₁ and IG ₂ can be compensated for by performing calibrated zero before digital conversion. , there is no difference in the digital conversion value due to passing through the integrators IG ₁ and IG ₂ .

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional analog-to-digital converter, Fig. 2 is a block diagram of an analog-to-digital converter of the present invention, Fig. 3 is an operating waveform diagram of Fig. 1, and Fig. 4 is a diagram of Fig. 2. FIG. MP...Multiplexer, IG ₁ , IG ₂ ...Integrator, ±
E _S ...Reference voltage source, COMP...Comparator.

Claims (1)

[Claims] 1. An integrator that integrates an input to be converted for a certain period of time and then integrates a reference voltage having a polarity opposite to that of the input to be converted for a certain period of time that is equal to or longer than this input integration time, A double integration type analog signal converter converts the input to be converted into a digital signal by detecting with a comparator until the output returns to the original level and counting the period digitally.
In the digital converter, a second integrator whose input resistance is shared by the integrator via a switch, and a changeover switch for making the comparator commonly used for detecting the output level of both integrators, An analog-to-digital converter in which a reference voltage for an input of one channel is integrated by one integrator, while a second integrator integrates the input of the next channel.