JPS63200081A - Timing signal generator - Google Patents

Abstract

PURPOSE:To obtain a high speed highly accurate timing signal, by distributing the test cycle signal formed by dividing the frequency of a fundamental clock to each phase generating part by a high speed operable frequency divider. CONSTITUTION:In a rate generating part RG, a frequency divider 16 for a rate subjects a fundamental clock to G-frequency division while a synchronous counter 17 for a rate counts the fundamental clock subjected to G-frequency division to generate a count finish pulse 117. In a phase generating part PG, a frequency divider 18 for a phase subjects the fundamental clock to M-frequency division while a synchronous counter 19 for a phase counts the fundamental clock subjected to M-frequency division to obtain a phase signal having resolving power M-times the cycle of the fundamental clock. Therefore, it is unnecessary to operate the counters 17, 19 at a high speed and the frequency of the fundamental clock can be enhanced up to the operation frequency of each of the frequency dividers. Further, a variable delay circuit 22 using a shift register 21 changes the step number of the resistor permitting the passage of the phase signal to make a delay time variable with the same resolving power as the cycle of the fundamental clock and, since the variable width in the circuit 22 is one cycle of the fundamental clock, said variable width becomes small by highly enhanced frequency.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a timing signal generator used in test equipment for ICs and LSIs, general measuring instruments, etc., and particularly for ICs and LSIs.
The present invention relates to a timing signal generator suitable for test equipment that performs high-speed and highly accurate timing tests such as SI.

[Conventional technology]

Regarding timing signal generators used in conventional IC and LSI test equipment, for example, Digest
of Papers Semiconductor Test Symposium (1977), pages 152 to 157 (Dig
est of papers Sem1conduct
ortest symposit++w (1977)
pp152-157).

FIG. 3 is a block diagram illustrating this conventional timing signal generator. This timing signal generator includes a basic clock generator CG that generates a basic clock 114 in response to a basic clock setting signal 211, and a test period setting signal 21.
7, a rate generator RG that generates a test period signal 116, a phase setting signal 219, and a phase fine adjustment signal 2.
The phase generating section PC outputs a phase signal 122 corresponding to the phase signal 122.

The basic clock generator CG includes a reference oscillator 10, a V frequency divider 11 that divides the output reference oscillation signal 110 by F by a value V given by a basic clock setting signal 211, and controls the oscillation frequency using a control voltage 113. voltage controlled oscillator 1
4, an F frequency divider 15 that divides the basic tarokk 114 of its output by F, and its F frequency division output 115 and V frequency division output 111.
, and a low-pass filter 13 that smoothes the output error signal 112 and outputs a control voltage 113.

The rate generator RG has a late synchronization counter 1 that counts the basic clock 114 and generates a count output 101, and compares the count output 101 with a test cycle setting signal 217 and outputs a late match output 103 when the two match. It consists of a late comparator 3 and a reset gate 2.

The phase generator PC has a count output 101 and a phase setting signal 2.
19 and if they match, phase match output 1
04, and a phase fine adjustment signal 2.
22 and a pulse gate 5.

FIG. 4 is an operational waveform diagram of the timing signal generator of FIG. 3. Next, the operation shown in FIG. 3 will be explained with reference to FIG. First, in the basic clock generator CG, the phase comparator 12 compares the phases of the V frequency division output 111 and the F frequency division output 115, and sends the output error signal 112 to the control voltage 113 via the low pass filter 13. The voltage is applied to the voltage controlled oscillator 14 as follows. As a result, the oscillation period Tv of the V frequency division output 111 and the F frequency division output 1
P L L (
Phase Locked Loop) control is performed. Therefore, if the period of the basic clock 114 is TC and the period of the reference oscillation signal 110 is T, then TV=V・T,
・・・・・・・・・ (11TF=FT-T,
・・・・−(2+TV=T,
−・−・−(3) (From formulas 11 to (3), Tc = (V/F) ・Ts −□−
(4i, and the period Tc of the basic clock 114 can be varied by the value V given by the basic clock setting signal 211.

In the rate generating section RG, a late synchronization counter l counts the basic clock 114 and outputs a count output 101.

Then, when the test cycle setting signal 217 and the count output 101 match, a late match output 103 is generated, and the late synchronization counter 1 is reset via the reset gate 2, and the counting of the upper hand is repeated again. Therefore, test period signal 1
16 cycle is TEA□, and the setting value of the test cycle setting signal 217 is N, then T*att=N* -Tc =N* (V/F) ・Ts...-(5)
becomes.

In the phase generating section PC, when the phase setting signal 219 and the count output 101 match, a phase matching output 104 is generated, and a phase pulse 105 having the same pulse width as the basic clock 114 is obtained via the pulse gate 5. Furthermore, a high-resolution phase signal 122 is obtained by a variable delay circuit 22 having a variable width up to one cycle of the basic clock 114 in accordance with the phase fine adjustment signal 222 . Therefore, if the delay time of the phase signal 122 is T□0, the set value of the phase setting signal 219 is P, and the delay time of the variable delay circuit 22 is T4, then Tphas* = P-Tc + T4...
−... (6).

In such a timing signal generator, the variable delay circuit 2
If the variable width of 2 is large, the accuracy will deteriorate as the resolution increases. Therefore, in order to obtain a high-resolution and highly accurate phase signal 122, it is essential to increase the frequency of the basic taro clock 114. Similarly, in order to obtain a high-speed test cycle signal 116, it is necessary to increase the frequency of the basic clock 114. However, since the basic clock 114 must be counted by a synchronous counter, it is disadvantageous for increasing the speed, precision, and resolution of timing signals.

[Problem that the invention seeks to solve]

Since the above-mentioned conventional technique requires counting the basic clock using a synchronous counter, it is disadvantageous in increasing the reference oscillation frequency to a higher frequency. In addition, since the variable range of the variable delay circuit needs to extend to the basic clock period, if the reference oscillation frequency cannot be made higher, the variable range must be expanded, leading to a decrease in the accuracy of the delay time in the variable delay circuit, Time accuracy deteriorates.

Furthermore, when the count output of the synchronous counter is distributed to a plurality of phase generators, there is a problem that adjustment is required to minimize the time difference between each signal.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a timing signal generator that can generate high-speed and highly accurate timing signals.

[Means for solving problems]

The above purpose is to increase the frequency of the basic clock by inserting a frequency divider that can control the frequency division number before the synchronous counter in the rate generation unit RG, and controlling the frequency division number with the count completion output of the synchronous counter. With this configuration, the basic tarok is frequency-divided to generate a test period signal, and the test period signal is distributed to each phase generation section PG.In the phase generation section PC, a frequency divider is inserted before the synchronous counter, and a This is achieved by a timing signal generator configured with a variable delay circuit using a shift register and a variable delay circuit for fine adjustment.

[For production]

In the above timing signal generator, the late frequency divider divides the basic clock by G, the late synchronous counter counts the G-divided basic clock and generates a count end pulse, and the phase frequency divider divides the basic clock by G. After dividing the basic clock by M, the phase synchronous counter counts the M-divided basic tally and obtains a phase signal with a resolution of M times the basic clock period. Therefore, the late synchronous counter and the phase synchronous counter It is not necessary to operate at high speed, and the basic clock can be made to have a high frequency up to the operating frequency of each frequency divider.

In addition, the variable delay circuit using a shift register for phase can vary the delay time with the same resolution as the basic clock cycle by switching the number of register stages through which the phase signal passes, and the variable width in the variable delay circuit for fine adjustment is basically Since it is one cycle of the clock, the variable width becomes smaller as the frequency of the basic tarok becomes higher, so the ratio of the minimum resolution to the variable width in the variable delay circuit also becomes smaller, so that a high-resolution, high-precision phase signal can be changed.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram showing one embodiment of a timing signal generator according to the present invention. Note that the same reference numerals or symbols indicate the same or corresponding parts throughout the drawings. In FIG. 1, this timing signal generator includes a basic clock generator CG that generates a basic clock 114 in response to a basic clock setting signal 211, and a basic clock generator CG that generates a basic clock 114 in response to a basic clock setting signal 211, and a basic clock generator CG that generates a basic clock 114 in response to a basic clock setting signal 211. Periodic signal 116
A phase generating section PG outputs a phase signal 122 corresponding to a phase setting signal 219, a shift register delay circuit setting signal 220, and a phase fine adjustment signal 222.

The basic clock generation unit CG uses a reference oscillator 110 and the output reference oscillation signal 110 as a basic clock setting signal 211.
A V frequency divider 11 that divides the frequency by F by a value given by , a voltage controlled oscillator 14 whose oscillation frequency is controlled by a control voltage 113, and an F frequency divider 11 that divides the basic clock 114 of its output by F.
Frequency divider 15 and its F frequency division output 115 and V frequency division output 11
1, and a low-pass filter 13 that smoothes the output error signal 112 and outputs a control voltage 113.

The rate generation unit RG divides the frequency division number G from G0 to Gl (G(1
A late frequency divider 16 that can change up to <G+ <2Go 1) and a late frequency divider 16 that counts the output G frequency division clock 126 and generates a late counting end pulse 117.
It consists of a late synchronization counter 117 that outputs to

The phase generator PC includes a phase frequency divider 18 that divides the basic clock 114 by M, and the output of the phase divider 18 that divides the basic clock 114 by M.
A phase synchronization counter 19 that counts 18 and outputs a phase counting end pulse 119, and a basic clock 11.
The variable delay circuit SRD includes a pulse selector 20 and a shift register 21, and a variable delay circuit 22 that varies the delay time in response to a phase fine adjustment signal 222. .

FIG. 2 is an operational waveform diagram of the timing signal generator of FIG. 1. Next, the operation shown in FIG. 1 will be explained with reference to FIG. First, in the basic clock generator CG, the phase comparator 12 compares the phases of the V frequency division output 111 and the F frequency division output 115, and sends the output error signal 112 to the control voltage 113 via the low pass filter 13. The voltage is applied to the voltage controlled oscillator 14 as follows. With this PLL configuration, the oscillation period Tv and F of the V frequency division output 111 are
PL so that the oscillation periods T of the divided output 115 are equal.
L control is performed. Therefore, if the period of the basic clock 114 is T6 and the period of the reference oscillation signal 110 is T, then '
rv = V, T, , −・−・(
1) TF=FT-T, ・------
(2) TV=TF ・−・−[3
) (From formulas 11 to (3), Tc ” (V/F) ・Ts
--.-(41, and the period T of the basic clock 114 is determined by the value ■ given by the basic clock setting signal 211.

can be varied.

Next, in the rate generation unit RG, the rate synchronization counter 1
7 is the basic clock 114. The frequency-divided G-divided clock 126 is counted by the number of times of the value C given by the test cycle setting signal 217, and a late counting end pulse 117 is output. Then, the rate frequency divider 16 sets the frequency division number to the value G given by the frequency division number setting signal 216.

, and outputs a test period signal 116 obtained by dividing the basic clock 114 by G. At the same time, the late synchronization counter 17 repeats the above counting again.

Therefore, the test period of the test period signal 116 is TRAT!
, if the basic clock period is TC, then T*Ayt= (C-Go + Cz) ・Tc-
(7), and the test period TRAT* which is an integral multiple of the basic clock period Tc can be obtained by the set values G o and G + of the frequency division number G given by the frequency division number setting signal 216.

FIG. 2 shows the value c,=3. G+ =5. This is an example when C-2(7). At this time, since the rate synchronization counter 17 operates at a speed less than 1/00 of the frequency of the basic clock 114, it is possible to increase the frequency of the basic clock 114 to the limit determined by the frequency divider 16.

Next, in the phase generation unit PC, the phase synchronization counter 19 and the phase frequency divider 18 receive the test periodic signal 116.
The phase synchronization counter 19 counts the M-divided clock 118 obtained by dividing the basic clock 114 by M by the phase frequency divider 18, and outputs the phase setting signal 2.
After counting the number of times of value P given by 19, a phase counting end pulse 119 is generated. Therefore, the phase count end pulse 119 output from the phase synchronization counter 19 can be set in units of time M times the period Tc of the basic clock by the phase setting signal 219. The shift register variable delay circuit SRD changes the delay time with one period Tc of the basic clock 114 as the resolution by switching the number of register stages through which the phase counting end pulse 119 passes in the shift register 21. The end pulse 119 is supplied to the shift register 21 via the pulse selector 20, but at this time, the input to the shift register 21 is switched by the set value S of the shift register delay circuit setting signal 220, and the above delay time is varied. An action is taken. The phase pulse 121 output from the shift register 21 can be set in units of one period Tc of the basic clock 114, and is further increased by a variable delay circuit 22 having a variable width up to one period of the basic clock 114 according to the phase fine adjustment signal 222. A resolution phase signal 122 is obtained. Therefore, the test period signal 116
From time Tph,. When obtaining the phase signal 122 delayed by 100 seconds, if the period of the basic tarlock 114 is Tc, the period of the M-divided clock 118 is T, and the delay time in the variable delay circuit 22 is T4, then Tphmm* = P-Tsc + 5- Tc + T
a --(8). FIG. 2 shows the value M=4. P-2,
This is an example when 3=1.

As described above, according to this embodiment, the late synchronization counter 17 and the phase synchronization counter 19 are 1/00 or less and 1/M of the basic clock 114, respectively.
Since the frequency of the basic clock 114 can be increased up to the operating frequency of the late frequency divider 16, phase frequency divider 18, and shift register 21, a high-speed timing signal can be used.

Furthermore, since the phase pulse 121 is set in units of one period of the basic clock 114, the variable width of the variable delay circuit 22 is limited to one period of the basic clock 114, but this variation can be made smaller by increasing the frequency of the basic clock 114. , and the minimum resolution in the variable delay circuit 22 can be kept small, so a highly accurate and high resolution phase signal 122 can be obtained.

Furthermore, when multiple phase generators PC are provided, only two signals, the test period signal 116 and the basic clock 114, are supplied to the phase generator PG, so the adjustment of the signal propagation time during signal distribution can be done in the same way as before. It has the effect of being able to reduce the amount compared to others.

Note that the above embodiment is an example of a timing signal generator such as a test device that performs timing tests on ICs, LSIs, etc.
-It can also be widely used in timing signal generators such as i-meters.

〔Effect of the invention〕

According to the present invention, the synchronous counter that constitutes the timing signal generator counts the output obtained by dividing the frequency of the basic clock, so the frequency of the basic clock can be increased to the operating frequency of the frequency divider and shift register, resulting in high-speed timing. The signal can be changed. Furthermore, by increasing the frequency of the basic clock, the variable width of the variable delay circuit for fine adjustment can be made smaller, so the ratio of the minimum resolution to the variable width becomes smaller, resulting in the effect of changing the phase signal with high precision.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing one embodiment of a timing signal generator according to the present invention, FIG. 2 is an operation waveform diagram of FIG. 1, FIG. 3 is a configuration diagram illustrating a conventional timing signal generator, and FIG. The figure is an operational waveform diagram of FIG. 3. 10...Reference oscillator, 11...F frequency divider, 12...
・Phase comparator, 13...Low pass filter, 14...Voltage controlled oscillator, 15...F frequency divider, 16...Rate frequency divider, 17...Late synchronous counter , 18...
Phase frequency divider, 19... Phase synchronous counter, 20... Pulse selector, 21... Shift register, 22... Variable delay circuit, CG... Basic clock generator, RG...・Late generation part, PG...phase generation part. Agent Patent Attorney Tadashi Akimoto Figure 2

Claims (1)

[Claims] 1. Generate a basic clock based on the reference oscillation signal,
In a timing signal generator that is configured to count the basic clock and send out a desired periodic signal, as well as send out a desired phase signal that is periodized to this, the basic clock is divided by a frequency divider that can operate at high speed. means for generating a synchronization signal and distributing it to means for generating a phase signal, and means for receiving this phase signal and counting the basic clock using a circuit combining a frequency divider, a counter, and a shift register and generating a phase signal. A timing signal generator characterized by: