JPS6319934A - Multiplex transmission equipment - Google Patents

Abstract

PURPOSE:To easily set addresses with a multiplex transmitting device by transmitting an address through a primary station in response to a request signal received from a secondary station and then setting addresses to each secondary station and an end state. CONSTITUTION:An input/output terminal 1-0 of a primary station 1 is connected to a double-core transmission line. The secondary stations 2-5 and an end station 6 are connected to the transmission line at each optional point by a multi-drop system. The station 1 supplies the power to the stations 2-5 and 6 via a transmission line 7 and at the same time transmits the address and data signals with superposition on a power supply. While the stations 2-5 receive supply of the power and send the request signals to the station 1 with different timings to perform transmission of data with the station 1 via the line 7.

Description

[Detailed Description of the Invention] [Field of the Invention] The present invention connects a primary station (master station) and a plurality of secondary stations (slave stations) to two stations.
The present invention relates to a multiplex transmission device that connects core wires in a multi-drop manner and performs time-division multiplex transmission using a power supply superimposition method.

[Summary of the invention]

In the multiplex transmission device according to the present invention, a large number of secondary stations and end stations are connected to the primary station via transmission lines in a multi-drop manner, and power is supplied from the primary station, and the primary station receives request signals. Address signals are sequentially sent to each secondary station and end station according to the address. The secondary station and the end station each have their own time constant circuits, and each sends a request signal to the primary station at different timings, and stores the address signal obtained thereafter as its own address, and thereafter uses that address as its own address. Similarly, when the end station receives an address, it outputs an end signal and performs data transmission. With this configuration, addresses can be automatically set for each secondary station and end station, making it possible to easily install secondary stations.

[Prior art and its problems]

(Prior art) In general, in a multiplex transmission device that configures a data transmission system by connecting a primary station and a plurality of secondary stations using a two-core dedicated line, a secondary station can be connected to any point on a common bus. A multi-drop method is often used to connect stations, and in this case it is necessary to set a unique address to each secondary station. Such address settings are normally made using a DIP switch or the like provided at each secondary station.

(Problems to be Solved by the Invention) However, when it is necessary to make the secondary station extremely compact, there is a problem in that miniaturization is restricted by the DIP switch. Furthermore, when setting up a large number of secondary stations at once, setting addresses is relatively easy, but when increasing or decreasing the number of secondary stations after configuring the multiplex transmission equipment system, the addresses may not be consecutive. Furthermore, there is a possibility that a plurality of secondary stations may be set to the same address by mistake, resulting in a transmission error. Also, a multiplex transmission device in which an end station is connected to the last secondary station is known, but it is necessary to set the address of the end station itself using a DIP switch, etc., making it difficult to downsize and the configuration complicated. There was a problem.

[Purpose of the invention]

The present invention has been made in view of the problems of the conventional multiplex transmission equipment, and eliminates the need to set an address for each secondary station using a switch, etc. at the time of installation. is a technical issue.

[Structure and effects of the invention]

(Configuration) The present invention is a multiplex transmission device in which a primary station, a plurality of secondary stations, and end stations are connected in a multi-drop manner via transmission lines, and as shown in FIGS. consists of a power supply circuit that supplies power to each secondary station and end station via a transmission line, a request signal receiving circuit that receives a request signal from the secondary station, and a request signal receiving circuit that receives a request signal from each secondary station. an address signal transmitting means for sequentially transmitting unique address signals to the station and the end station; an end signal receiving circuit for receiving the end signal and starting data transmission/reception; and a data transmission means for transmitting data, and each secondary station has its own time constant circuit, and starts at different timings of each time constant circuit based on the power supply voltage applied from the transmission line. a reset circuit that generates a signal to cancel the reset; a request signal transmission circuit that sends out a request signal after the reset is canceled; an address signal holding unit that receives and holds the address signal after sending the request signal; and data transmission means for transmitting data with the primary station after receiving the address, and the end station has a time constant circuit that is slower than each secondary station, and the end station has a time constant circuit that is slower than each secondary station, and the end station has a time constant circuit that is slower than each secondary station, and the end station has a time constant circuit that is slower than each secondary station, and the end station has a time constant circuit that is slower than each secondary station. A reset circuit that generates a start signal at the timing of a time constant circuit to release the reset, an address signal holding means that receives and holds the address setting after transmitting the request signal, and an end signal for the primary station after receiving the address signal for the end station. The device is characterized by comprising an end signal transmitting circuit that sends out a signal.

(Function) According to the present invention having such characteristics, each secondary station and end station are connected to a time constant circuit having a unique time constant, and when the power is turned on, the reset is released with a different time constant. A request signal is given from each secondary station. Therefore, the primary station sends out an address in response to this and sets an address to each secondary station and end station. When an end signal is given from the end station, the address setting is completed, and data transmission is thereafter performed with each secondary station based on the set address.

(Effects) Therefore, according to the present invention, there is no need to set addresses for each secondary station and end station using a DIP switch or the like. Therefore, the secondary station and the end station can be downsized, and the workability when installing the secondary station can be improved. In addition, when adding a secondary station to a transmission line, the address can be automatically set by simply connecting a time constant circuit that has a different time constant from that of other secondary stations, making expansion extremely easy. Become.

[Explanation of Examples]

FIG. 1 is a schematic block diagram showing an embodiment of a multiplex transmission apparatus according to the present invention. In this figure, the input/output terminal 1-o of the primary station 1 is connected to a two-core transmission line, and a plurality of secondary stations 2 to 5 and an end station 6 are connected to this transmission line in a multi-drop manner at any point. It is connected.

The primary station 1 supplies power to each of the secondary stations 2 to 5 and the end station 6 via a transmission line 7, and also sends address signals.

The data signal is superimposed on the power supply and sent out, and each secondary station sends a request signal to the primary station at different timings when the power is supplied, and the data is sent via the transmission line 7 between it and the primary station 1. It is used for transmission.

(Configuration of the primary station) As shown in FIG. 2, the primary station 1 includes the primary station 1 and each of the secondary stations 2 to 5. It has a power supply circuit 11 that supplies power to the industrial station 6, and a block filter 12 through which the voltage output of the power supply circuit 11 passes a DC component and an input/output terminal 1-.
o to the transmission line 7. Further, the power output of the power supply circuit 11 is also given to the reset circuit 13. The reset circuit 13 has a charging/discharging circuit including a resistor R1, a diode D1 for speeding up discharging, and a capacitor C1, and a Schmitt trigger circuit 13a connected to the midpoint of the charging/discharging circuit. and is given to the address setting flag 15. Also, input/output terminal 1-
0 via the line interface 16 to the request signal receiving circuit 17 . The end signal receiving circuit 18 is connected,
Also, the address signal transmitting circuit 19 and the data signal transmitting/receiving circuit 2
0 is connected. The request signal receiving circuit 17 receives request signals from each secondary station and end station,
It gives a signal to the address signal transmitting circuit 19 to start transmission. The address signal transmission circuit 19 transmits the address corresponding to the count value of the counter 14 to the line interface 16.
The counter 14 is incremented after the transmission. The counter 14 and the address signal transmitting circuit 19 constitute address signal transmitting means for transmitting a unique address signal to each secondary station and end station. The address signal transmitting circuit 19 provides an operation start signal to the data signal transmitting/receiving circuit 20 every time transmission is completed. When the end signal is received, the end signal receiving circuit 18 resets the counter 14 and the address setting flag 15 and outputs the body symbol indicating that one scan has been completed to the outside. If the address setting flag 15 is not set, the data signal transmitting and receiving circuit 20 transmits and receives data signals to and from the secondary station corresponding to the address via the line interface 16, and sends a completion signal when the transmission and reception are completed. This is given to the address signal transmitting circuit 19. The data signal transmitting/receiving circuit 20 constitutes data transmission means for transmitting data with each secondary station.

(Configuration of Secondary Station) FIG. 3 is a block diagram showing the configuration of the secondary station 2. In the secondary station 2, a line interface 21 and a block filter 22 are connected to the transmission line 7.

The block filter 22 provides only the DC component sent onto the transmission line 7 to the power supply circuit 23.

The power supply circuit 23 stabilizes the voltage and supplies the voltage to each part of the secondary station, and also provides a voltage output to the reset circuit 24.

Like the reset circuit of the primary station 1 described above, the reset circuit 24 has a time constant circuit consisting of a resistor R2, a capacitor C2, and a diode D2, and a Schmitt trigger circuit 24a. In the time constant circuit, for example, the resistor R2 is configured to be detachable by plug-in, and the capacitance of the capacitor C2 is changed to the capacitor C2.
1, the resistance value R2 is selected to be sufficiently larger than R'l. The reset circuit 24 provides a start signal from the Schmitt trigger circuit 24a at a predetermined time constant after the power is turned on. Now line interface 2
1 is connected to a data signal transmitting/receiving circuit 25 and an address signal receiving circuit 26. Address signal receiving circuit 26
is for transmitting the address signal applied via the line interface 21 to the address buffer 27 and comparator 28. The address signal receiving circuit 26 and the address buffer 27 constitute address signal holding means that receives and holds an address signal. The aforementioned reset circuit 2
The start signal No. 4 is given to the request signal transmitting circuit 29. The request signal transmitting circuit 29 provides a request signal to the primary station via the transmission line 7, and also provides an operation permission signal to the address signal receiving circuit 26 and address buffer 27. Comparator 28 is address signal receiving circuit 26
The address received by the address buffer 27 is compared with the address held in the address buffer 27, and if the addresses match, a signal is given to the data signal transmitting/receiving circuit 25 to enable transmission/reception. The data signal transmitting/receiving circuit 25 performs data transmission between the secondary station 2 and the primary station 1, transmits output data given from the outside, and outputs received data to the outside. The data signal transmitting/receiving circuit 25 constitutes data transmitting means for transmitting data with the primary station after receiving the address.

The secondary stations 3 to 5 have substantially the same configuration as the secondary station 2, and have different time constants of time constant circuits connected to the reset circuit. For example, the secondary stations 2 to 5 each have a resistor R2 connected to the reset circuit 24 in a plug-in manner.
~R5, but each resistance value increases sequentially at a predetermined interval (i.e., R1<R2<R3<R4
<R5).

(Configuration of End Station) FIG. 4 is a block diagram showing the configuration of the end station 6. As shown in FIG. The end station 6 also has almost the same configuration as the secondary stations 2-5. That is, a line interface 31 and a block filter 32 are connected to the transmission line 7, and a power supply circuit 33 and a reset circuit 34 are connected to the block filter 32. The reset circuit 34 has a time constant circuit similar to other secondary stations,
It is assumed that the plug-in resistor R6 has a larger resistance value than the resistor R5 of the secondary station 5. Further, an address signal receiving circuit 36 is connected to the line interface 31. The address signal receiving circuit 36 similarly receives the address buffer 3.
7 and comparator 38 with the received address signal. The address signal receiving circuit 36 and the address buffer 37 constitute address signal holding means that receives and holds an address signal. The reset circuit 34 also provides a start signal to the request signal transmission circuit 39. The request signal transmitting circuit 39 transmits a request signal to the primary station via the transmission line 7, and also provides an operation permission signal to the address signal receiving circuit 36 and address buffer 37. Comparator 3
8 provides a transmission start signal to the end signal transmission circuit 35 when the received address signal and the address of the address buffer 37 match. The end signal transmitting circuit 35 sends an end signal to the primary station via the transmission line 7.

(Operation of this embodiment) Next, the operation of this embodiment will be described with reference to flowcharts and time charts. Fig. 5 is a flowchart showing the operation of the primary station 1, and Figs.
5 is a flowchart showing operations of the end station 6 and the end station 6;
FIG. 8 is a time chart showing the address setting operation after power is turned on.

First, when the power is turned on at time t0, the primary station 1 proceeds to step 41 and waits for a start signal to be transmitted from the reset circuit 13. When the reset is canceled by the start signal, the process proceeds to step 42, where the count value of the counter 14 is cleared. Then, in steps 43 and 44, reception of a request signal or an end signal is awaited. . 2 each
Since the next stations 2 to 5 and the end station 6 are connected to resistors (R2 to R6) having different resistance values, the reset release times are different from each other. When the X source is turned on, the primary station 1
A voltage is supplied to the power supply circuit 23 via the block filter 12, the transmission line 7, and the block filter 22 of each secondary station. Therefore, the start signal is sent to the request signal transmitting circuit 29 from the reset circuit 24 at different timings.
can be conveyed to. That is, when the start signal of the secondary station 2 rises at a certain time after the power is turned on, as shown in FIG.
A request signal R1 is sent out as shown in a) (steps 61 and 62).

When the primary station 1 receives the request signal R1, it performs step 4.
Proceeding to step 5, the address signal transmission circuit 19 sends out the address signal A(0) via the line interface 16,
After that, the counter 14 is incremented (step 4
6) Return to step 43. The secondary station 2 receives the thus applied address signal A(0) from the address signal receiving circuit 26 and holds it in the address buffer 27 (step 63).
), and then waits for the reception of an address signal.

Then, at time t2, as shown in Fig. 8(al), (d), (1), when the start signal of the secondary station 3 rises, the secondary station 3
A request signal R2 is sent out. The primary station 1 sends out an address signal A(1) in accordance with the count value of the counter 14. The secondary station 2 receives address signal A (11) in step 64, but since the received address does not match the stored address A (01),
Return to and repeat the same process. On the other hand, the secondary station 3 receives the address signal A]1) after transmitting the request signal R2, so the process proceeds from step 62 to step 63 and stores the address A (11) given to the address buffer 27.In this way, each secondary station Address A for 2-5 (01-A
(Set 31. Also, Fig. 8 (d+, (fl.

(As shown in gl, when a start signal is applied from the reset circuit 34 of the end station 6 with the slowest rise time at time t, the end station 6 proceeds from step 71 to step 72 and sends out the request signal R5.

In this case as well, primary station 1 has address A for end station 6.
(4) is sent. End station 6 uses this address A (4)
is held in the address buffer 37, and the ta in FIG.
＞The end signal E is sent as shown in step 73.
．． 74). When the primary station 1 receives the end signal E, it proceeds from step 44 to step 47 and sets the address setting flag 1.
5 is cleared to end the address setting process.

In this way, each secondary station 2 to 5 and end station 6 are addressed.

Once the station is set up, data is transmitted between each secondary station. That is, at the start of data transmission, the primary station 1 first clears the counter 14 in step 48 and outputs the address signal A.
(0) and increments the counter (steps 49 and 50). Initially, as shown in FIG. 9, address A (Q) is sent, so the address of secondary station 2 is designated. This address signal is given to all the secondary stations 2 to 5 and the end station 6 via the line interface 21 of each secondary station.

When each secondary station 2-5 and end station 6 receives the address signal in steps 64.65 and 75.76, it checks whether the received address matches the held address. This address signal A(0)
matches only the address signal held in the address buffer 27 of the secondary station 2.

Therefore, the secondary station 2 proceeds to routine 66 to transmit and receive data signals, and the other secondary stations and end stations proceed to step 64.
Then, the process returns to step 75 and waits for the next address signal. That is, as shown in FIG. 9, the data signal transmitting/receiving circuit 25 of the secondary station 2
When the data signal D21 is sent to the primary station 1,
The primary station 1 is waiting for a data signal or an end signal in steps 51 and 52, and upon receiving the data signal, the process proceeds from step 51 to step 53 and sends out a data signal to the secondary station 2. Then, the process returns to step 49, the counter 14 is incremented, and the same process is repeated.

In this way, as shown in FIG. 9, address signals can be sequentially sent to each of the secondary stations 2 to 5, and then data can be transmitted with each secondary station.

Then, when the address signal A(4) to the end station 6 is sent, the end station 6 receives the address signal (step 75). Since the received address matches the address A(4) of the address buffer 37, the end station 6 sends the address signal A(4) to the end station 6. The end signal E is then transmitted (step 77). When the primary station 1 receives this end signal E, it proceeds from step 52 to step 47, resets the counter 14, and repeats the same process thereafter.

In this way, after completing one cycle of data transmission to all secondary stations, data transmission and reception can be repeated again to continue data transmission.

In this embodiment, a multiplex transmission apparatus using four secondary stations has been described, but it goes without saying that a similar system can be constructed using an even larger number of secondary stations.

In addition, in this embodiment, resistors with different resistance values are set in each secondary station and the end station to make the time constants of the time constant circuits different. However, capacitors with different capacitances are connected to each secondary station. Alternatively, a time constant circuit combining a resistor and a capacitor may be installed at each secondary station and each end station.

Furthermore, in this embodiment, a multiplex transmission device that alternately transmits data between each secondary station and a primary station has been described. It goes without saying that the present invention can also be applied to.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing an embodiment of the multiplex transmission device according to the present invention, FIG. 2 is a block diagram showing the configuration of the primary station of the multiplex transmission device according to the present embodiment, and FIG. 3 is a block diagram showing the configuration of the secondary station. FIG. 4 is a block diagram showing the configuration of an embodiment of the end station. FIG. 5 is the primary station, FIG. 6 is the secondary station, and FIG. 7 is the end station. Flowcharts showing the respective operations, Figure 8 is a time chart of each station during initial operation when setting addresses for each secondary station and end station, Figure 9 is data transmission of each station during normal data transmission operation. It is a time chart showing the state. 1...--Primary station 2-5...-Secondary station
6-----End station 7--Transmission line
11.23.33...--Power supply circuit 12,22.3
2--Block filter 13, 24.34
・−・−Reset circuit 14−−−1−・Counter
15.--Address setting flag 16.21.3
1---Line interface 17---Request (word receiving circuit 18--End signal receiving circuit 19---Address signal transmitting circuit 20.25.----- Data signal transmission/reception circuit
26.36---Address signal receiving circuit 27.37
...--Address buffer 28.38--
...Comparator 29, 39--Request signal transmission circuit 35--End signal transmission circuit Patent applicant Tateishi Electric Co., Ltd. Figure 1, Figure 2, Dress Day 7 Figure 3 Figure 4 Figure 5! I Figure 6 Figure 7

Claims (2)

[Claims] (1) A multiplex transmission device in which a primary station and a plurality of secondary stations and end stations are connected in a multi-drop manner via transmission lines, and the primary station is connected to each secondary station and end station. a power supply circuit that supplies power via a transmission line; a request signal receiving circuit that receives a request signal from a secondary station; and a request signal receiving circuit that sequentially sends a unique address signal to each of the secondary stations and end stations each time a request signal is received. an end signal receiving circuit that receives an end signal and starts data transmission/reception; and a data transmission means that transmits data with the secondary station after transmitting the address signal to each of the secondary stations. Each of the secondary stations has its own time constant circuit, and releases the reset by generating a start signal at different timings of the respective time constant circuits based on the power supply voltage applied from the transmission line. a reset circuit; a request signal transmitting circuit that transmits a request signal after the reset is released; an address signal holding unit that receives and holds an address signal after transmitting the request signal; data transmission means for transmitting data; the end station has a time constant circuit that is slower than each of the secondary stations, and the end station has a timing constant circuit that is slower than each of the secondary stations, and the timing of the time constant circuit is determined based on the power supply voltage applied from the transmission line. a reset circuit that generates a start signal to release the reset; address signal holding means that receives and holds an address signal after transmitting the request signal; and sends an end signal to the primary station after receiving the address signal to the end station. A multiplex transmission device comprising: an end signal transmission circuit. (2) The multiplex transmission according to claim 1, wherein the time constant circuits provided in each of the secondary stations and the end stations are constructed by installing resistors having different resistance values in advance. Device.