JPS63197112A - Data converting circuit - Google Patents

Abstract

PURPOSE:To obtain a stable output data by switching a conversion table converting an input data into an output data depending on the change in the input data so as to give a hysteresis characteristic to the input/output characteristic of the data conversion circuit. CONSTITUTION:The conversion table converting an input data SD2 into an output data SD5 is switched based on results of detection SC2, SC3 of a comparator 12. That is, the conversion table converting the input data SD2 into an output data SD5 is switched in response to the change in the input data SD2. Thus, a hysteresis characteristic is provided to the input characteristic of a data converting circuit 9. Thus, even when the input data SD2 is changed at a minute range frequently, the stable output data SD5 is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a data conversion circuit, and is suitable for application to, for example, a sampling rate converter circuit.

B. Summary of the Invention The present invention provides stable input/output characteristics of the data conversion circuit by switching the conversion table for converting input data to output data in response to changes in the input data. It is designed to obtain output data.

C. Conventional technology Conventionally, in a sampling rate converter circuit,
The transfer characteristics of the digital filter circuit are changed depending on the data sampling frequency.

That is, as shown in FIG. 6, 1 indicates the sampling rate converter circuit as a whole, and the sampling pulse signal Sl(
Frequency 30~50 (kHz)) is detected by frequency detection circuit 2.
receive it.

The frequency detection circuit 2 detects the frequency of the sampling pulse signal Sl at the timing of the clock signal GK, and outputs the detection result to the data conversion circuit 3 as detection data SD2 consisting of, for example, 15-bit parameter data.

As shown in FIG. 7, the data conversion circuit 3 receives the detection data SD2 as input data at the timing of the clock signal CK, and the value of the detection data SD2 is set to a predetermined value D1,
When changing beyond D2 and D3, the value DDI,
For example, by outputting 3-bit parameter data SD3 in which DD2, DD3, and DD4 change as output data, the detection data SD2 can be converted into the parameter data S.
Convert to D3.

The digital filter circuit 4 receives parameter data SD3.
By switching the operation of the flip-flop circuit constituting the digital filter circuit 4 in accordance with the change in the frequency of the sampling pulse signal Sl, the filter characteristics are switched in a stepwise manner.

Therefore, via the digital filter circuit 4, it is possible to obtain sampling data SDO that has been filtered according to the frequency of the sampling pulse signal S1.

D Problems to be Solved by the Invention However, in this type of sampling rate converter circuit, the value of the detection data SD2 fluctuates within a small range due to detection errors of the frequency detection circuit 2, fluctuations in the frequency of the sampling pulse signal 31, etc. There are cases where

Such fluctuations in the detected data SD2 are caused by the data conversion circuit 3.
When the value D1, D2, or D3 varies, the value of the parameter data SD3 varies with the variation of the detection data SD2, and there is a problem that stable parameter data SD3 cannot be obtained.

As a result, in the sampling rate converter circuit 1, the filter characteristics of the digital filter circuit 4 change frequently, making it impossible for the digital filter circuit 4 to operate stably and to obtain stable sampling data SDO.

The present invention has been made in consideration of the above points, and aims to propose a data conversion circuit that can obtain stable output data even if the input data value fluctuates frequently within a small range. be.

E Means for Solving the Problem In order to solve this problem, in the present invention, in the data conversion circuit 9 configured to convert the input data SD2 into the output data SD5 at a predetermined clock cycle, the output data SD5 and , input data SD2 obtained at a timing delayed or advanced by a predetermined clock cycle with respect to output data SD5, or output data SD5 obtained at a timing delayed or advanced by a predetermined clock cycle with respect to output data SD5. A comparison circuit 12 is provided to detect changes in input data SD2 by comparison, and a conversion table for converting input data SD2 to output data SD5 is switched based on detection results SC2 and SC3 of comparison circuit 12.

By switching the conversion table for converting the input data SD2 to the output data SD5 in response to changes in the F-action input data SD2, the input/output characteristics of the data conversion circuit 9 can be provided with hysteresis characteristics.

In this way, stable output data SD5 can be obtained even if the value of input data SD2 changes frequently within a small range.

G example An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, in which parts corresponding to those in FIG. 6 are given the same reference numerals, 9 indicates a data conversion circuit as a whole, and receives detected data SD2 into a conversion table circuit 10. In FIG.

The conversion table circuit 10 is composed of a read-only memory circuit equipped with first and second conversion tables for converting the detection data SD2 into 3-bit parameter data SD4 using the value of the detection data SD2 as an address value. The first and second conversion tables are switched based on a switching signal SCI.

As shown in FIGS. 2 and 3, the first and second conversion tables are configured such that the value of the parameter data SD4 changes stepwise as the detection data SD2 increases. The change in the second conversion table is made to change when the detected data SD2 becomes a value larger by one bit than the change in the second conversion table.

Therefore, the 15-bit detection data SD2 is converted via the conversion table circuit 10 based on the first or second conversion table.
3-bit parameter data S that changes according to changes in
D4 can be obtained at a timing synchronized with the clock signal CK.

The flip-flop circuit 11 receives the parameter data S
In response to D4, the parameter data SD5 delayed by one clock period is outputted to the comparison circuit 12 and the digital filter circuit 4, and the parameter data 5DD5 further delayed by one clock period is outputted to the comparison circuit 12 via the flip-flop circuit 13. Output to.

Therefore, the comparison circuit 12 can determine whether the detected data SD2 is increasing or decreasing by comparing the parameter data SD5 and the parameter data 5DD5 one clock period earlier than this at the timing of the clock signal GK.

In other words, if the value of parameter data SD5 is larger than the value of parameter data 5DD5 one clock period before,
The value of the detection data SD2 increases over the value Di, D2 or D3 with respect to the first conversion table, or
The value D1+1, D2+1 or D3 for the conversion table of
This means that the value of the parameter data SD5 has increased by more than +1, and conversely, if the value of the parameter data SD5 is smaller than the value of the parameter data 5DD5 l clock cycle ago, the value of the detection data SD2 is the value DiD2 for the first conversion table. or decreases beyond D3, or for the second translation table the value [
)l+1. This means a decrease of more than D2+1 or D3+1.

On the other hand, if the value of the parameter data SD5 is equal to the value of the parameter data 5DD5 one clock period before, the value of the detection data SD2 is changed from the value D1 to the value D2 or from the value D2 to the first conversion table. Value D3 or value DI+1 to value D2+1 for the second conversion table
Or it means changing between the values D2+1 and D3+1.

The comparison circuit 12 outputs a detection signal SC when the value of the parameter data SD5 is larger than the value of the parameter data 5DD5.
2 and SC3, the logic level of the detection signal SC2 is raised to logic rHJ, and conversely, when the parameter data SD5 is smaller than the value of the parameter data 5DD5, the detection signal S
The logic level of detection signal SC3 of C2 and SC3 is raised to logic rHJ.

On the other hand, when the value of parameter data SD5 and the value of parameter data 5DD5 are equal, the logic levels of detection signals SC2 and SC3 are both maintained at logic "L".

The flip-flop circuit 14 receives detection signals SC2 and SC
3 and the clock signal CK, and when the logic level of the detection signal SC2 rises to the logic rHJ, the table switching signal SC
I, the conversion table circuit 10 is switched from the first conversion table to the second conversion table, and conversely, when the logic level of the detection signal SC3 rises to logic rHJ, the conversion table circuit IO is switched from the first conversion table to the second conversion table. Switch to .

Therefore, as shown in FIG. 4, when the value of the detection data SD2 gradually increases and then fluctuates between the value D2 and a value D2+1 that is 1 bit larger than this, the parameter data S
As the value of D4 changes from value DDI to value DD2, the logic level of detection signal SC3 rises to logic rHJ, and after the first conversion table is selected, when the value of detection data SD2 becomes value D2, the parameter Data SD4
The value of is switched to the value DD3 as shown by arrow a.

As a result, as already indicated by the arrow, the detected data SD2 becomes the value D2.
Even if the parameter data SD4 changes between the value D2+1 and the value D2+1, the parameter data SD4 held at the value DD3 can be obtained.

On the other hand, the variation range of the detection data SD2 ranges from the value D2 and the value D2+1 to the value D that is 1 bit smaller than this value.
2-1 and the value D2, arrow C in FIG.
When the value of the parameter data SD4 decreases from the value DD3 to the value DD2 as shown in , the logic level of the detection signal SC2 rises to the logic rHJ, and the second conversion table is selected. As a result, even if the value of the detection data SD2 fluctuates between the value D2-1 and the value D2 as shown by the arrow d, it is possible to obtain the parameter data SD4 maintained at the value DD2.

Subsequently, when the variation range of the detection data SD2 moves between the value D2 and the value D2+1, the value of the parameter data SD4 increases from the value DD2 to the value DD3 as shown by the arrow e, so the first conversion table is again changed. is selected.

Therefore, when the detected data SD2 fluctuates around the value D2, each value D1,
It is possible to obtain parameter data SD4 that changes with a hysteresis characteristic of one bit above and below D2 and D3, and the input/output characteristics of the entire data conversion circuit 9 can have a hysteresis characteristic.

Therefore, the detection error of the detection circuit and the sampling pulse signal S
Even if the value of the detection data SD2 frequently fluctuates within a small range due to fluctuations in the frequency of the filter circuit 1, stable parameter data SD4 can be obtained, and as a result, the digital filter circuit 4 can be controlled to switch frequently. Stable sampling data SDO can be obtained without any problems.

According to the above configuration, by switching the conversion table of the conversion table circuit and providing hysteresis characteristics to the input/output characteristics of the data conversion circuit, even if the value of the detected data fluctuates frequently within a small range, it can be stabilized. Parameter data S
D4 can be obtained, and stable sampling data SDO can be obtained without frequently switching and controlling the digital filter circuit 4.

In this way, even if the detected data fluctuates due to detection errors of the frequency detection circuit 2, fluctuations in the frequency of the sampling pulse signal S1, etc., stable sampling data SDO can be obtained.

In the above embodiment, a case was described in which 15-bit detection data was converted to 3-bit parameter data, but the number of bits of input/output data before and after conversion is not limited to this, for example, the number of bits before and after conversion is It can also be applied when they are equal.

Furthermore, in the above embodiment, the data after conversion is compared and the conversion table is switched based on the comparison result. However, if the number of bits before and after conversion is the same, The input/output data may be compared and the conversion table may be switched based on the comparison result.

Furthermore, in the above-described embodiment, a case was described in which the first and second conversion tables were used in which the change in parameter data was shifted by one bit with respect to the detected data. However, the present invention is not limited to this, and it is also possible to prepare a conversion table that varies by 2 bits, for example, and to switch between these tables.

In addition, the number of conversion tables to be prepared is not limited to just one set; for example, a 1Mi conversion table that changes by 1 bit and a set of conversion tables that changes by 2 bits may be prepared. , the conversion table to be switched may be selected depending on the fluctuation of the detected data.

Furthermore, in the above-described embodiment, a case was described in which the present invention was applied to a sampling rate converter circuit, but the present invention is not limited to this. It can be widely applied to data conversion circuits that convert into .

H Effects of the Invention As described above, according to the present invention, by switching the conversion table used for data conversion, hysteresis characteristics can be obtained in the input/output characteristics, and thus the value of input data required for data conversion can be changed. However, stable output data can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a sampling rate converter circuit according to the present invention, FIGS. 2 and 3 are characteristic curve diagrams showing the human output characteristics of the first and second conversion tables, and FIGS. 4 and 5 is a characteristic curve diagram for explaining its operation,
FIG. 6' is a block diagram showing a conventional sampling rate converter circuit, and FIG. 7 is a characteristic curve diagram showing the input/output characteristics of the data conversion circuit. 2... Frequency detection circuit, 3.9... Data conversion circuit, 4... Digital filter circuit, 10... Conversion table circuit, 11.13. 1
4...Flip-flop circuit, 12...
・Comparison circuit.

Claims (1)

[Claims] A data conversion circuit configured to convert input data into output data at a predetermined clock cycle, wherein the output data is delayed or preceded by the predetermined clock cycle with respect to the output data. comprising a comparison circuit that detects a change in the input data by comparing input data obtained at a timing or output data obtained at a timing delayed or advanced by a predetermined clock cycle with respect to the output data; A data conversion circuit characterized in that a conversion table for converting the input data to the output data is switched based on the detection result of the comparison circuit.