JPS631559Y2 - - Google Patents
Info
- Publication number
- JPS631559Y2 JPS631559Y2 JP15343180U JP15343180U JPS631559Y2 JP S631559 Y2 JPS631559 Y2 JP S631559Y2 JP 15343180 U JP15343180 U JP 15343180U JP 15343180 U JP15343180 U JP 15343180U JP S631559 Y2 JPS631559 Y2 JP S631559Y2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- thyristor
- dividing resistors
- series
- voltage dividing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000015556 catabolic process Effects 0.000 claims description 3
- 239000006096 absorbing agent Substances 0.000 description 5
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000010008 shearing Methods 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009545 invasion Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Description
【考案の詳細な説明】
本考案は電源電圧より小さい定格電圧のサイリ
スタを複数個直列接続した制御回路に関するもの
で、漏電しや断器などに好適なものである。[Detailed Description of the Invention] The present invention relates to a control circuit in which a plurality of thyristors having a rated voltage lower than the power supply voltage are connected in series, and is suitable for leakage, disconnection, etc.
この種の制御回路においては、主のサイリスタ
のオンにより従のサイリスタがトリガーされて、
負荷に通電されるのであるが、従のサイリスタの
トリガー回路が複雑であつた。 In this type of control circuit, turning on the master thyristor triggers the slave thyristor,
Although the load is energized, the trigger circuit of the secondary thyristor was complicated.
本考案の目的は、従のサイリスタのトリガー回
路を簡単にすることができる。複数個の直列サイ
リスタから成る制御回路を提供することである。 The purpose of the present invention is to simplify the trigger circuit of the secondary thyristor. It is an object of the present invention to provide a control circuit consisting of a plurality of series thyristors.
以下図面によつて本考案の一実施例を説明す
る。この実施例は漏電しや断器に使用された例で
ある。主回路Ｌには漏電電流を検出する零相変流
器ZCTが設けられ、零相変流器ZCTより電源端
子t1，t2の側には、しや断部Ｓが設けられる。し
や断部ＳはトリツプコイルTCに電流が流れると、
しや断動作する。トリツプコイルTCは制御回路
Ｋの負荷となるものである。制御回路Ｋの電源電
圧は、零相変流器ZCTより負荷端子t3，t4の側の
主回路Ｌからとられる。零相変流器ZCTの２次
コイルＷは可変抵抗Raを経て増幅器Ａに接続さ
れ、増幅器Ａの出力電圧は主のサイリスタTh1の
ゲート・カソード間に与えられる。主のサイリス
タTh1は従のサイリスタTh2及びトリツプコイル
TCと共に電源ラインl1，l2の間に直列に接続され
る。サイリスタTh1，Th2の定格電圧は等しく、
且つ電源ラインl1，l2の電源電圧より小さい。電
源ラインl1，l2間には、電圧バランス用の分圧抵
抗R1，R2、サージ吸収器Z1，Z2、トリガー用の
分圧抵抗R3，R4が接続される。分圧抵抗R1，R2
の分圧比と分圧抵抗R3，R4の分圧比とは等しい。
分圧抵抗R1，R2間の接続点ａと分圧抵抗R3，R4
間の接続点ｂとの間には、二端子サイリスタTh3
と従のサイリスタTh2のゲート・カソード間とが
直列に接続される。二端子サイリスタTh3には、
主サイリスタTh1がオンした時に二端子間に印加
される電圧より小さい降伏電圧を有するものが選
ばれる。従のサイリスタTh2のゲート・カソード
間に並列にゲート抵抗R5が接続される。増幅器
Ａには、電源ラインl1，l2の電源電圧が抵抗R6を
経てダイオードＤにより半波整流されて、電源電
圧として与えられる。R7は電流制限用の抵抗、
R8は主のサイリスタTh1のゲート抵抗である。 An embodiment of the present invention will be described below with reference to the drawings. This embodiment is an example used for leakage and disconnection. The main circuit L is provided with a zero-phase current transformer ZCT for detecting leakage current, and a sheath section S is provided on the side of the power supply terminals t 1 and t 2 from the zero-phase current transformer ZCT. When the current flows through the trip coil TC, the gap S becomes
It works. The trip coil TC serves as a load for the control circuit K. The power supply voltage of the control circuit K is taken from the main circuit L on the side of the load terminals t 3 and t 4 from the zero-phase current transformer ZCT. The secondary coil W of the zero-phase current transformer ZCT is connected to an amplifier A via a variable resistor R a , and the output voltage of the amplifier A is applied between the gate and cathode of the main thyristor Th 1 . The master thyristor Th 1 is connected to the slave thyristor Th 2 and the trip coil
It is connected in series with the TC between the power lines l 1 and l 2 . The rated voltages of thyristors Th 1 and Th 2 are equal,
Moreover, it is smaller than the power supply voltage of power supply lines l 1 and l 2 . Connected between the power lines l 1 and l 2 are voltage dividing resistors R 1 and R 2 for voltage balance, surge absorbers Z 1 and Z 2 , and voltage dividing resistors R 3 and R 4 for triggering. Voltage dividing resistor R 1 , R 2
The voltage dividing ratio of is equal to the voltage dividing ratio of voltage dividing resistors R 3 and R 4 .
Connection point a between voltage dividing resistors R 1 and R 2 and voltage dividing resistors R 3 and R 4
A two-terminal thyristor Th 3 is connected between the connection point b and
and the gate and cathode of the slave thyristor Th2 are connected in series. The two-terminal thyristor Th 3 has
One is selected that has a breakdown voltage smaller than the voltage applied between the two terminals when the main thyristor Th 1 is turned on. A gate resistor R5 is connected in parallel between the gate and cathode of the secondary thyristor Th2 . The power supply voltage of the power supply lines l 1 and l 2 is half-wave rectified by a diode D through a resistor R 6 and is applied to the amplifier A as a power supply voltage. R7 is a current limiting resistor,
R 8 is the gate resistance of the main thyristor Th 1 .
漏電電流が主回路Ｌに流れていない場合には、
主のサイリスタTh1はオフであり、従のサイリス
タTh2もオフである。分圧抵抗R1，R2によつて
電源電圧は1/2に分圧され、この均等な分圧電圧
がそれぞれサイリスタTh1，Th2に印加されるの
で、サイリスタTh1，Th2の漏れ電流にバラツキ
があつても、サイリスタTh1，Th2は電源電圧の
１／２ずつを均等に分担する。トリガー用の分圧抵
抗R3，R4も電源電圧を1/2に均等に分圧するの
で、接続点ａと接続点ｂとの間の電位差は零であ
る。したがつて二端子サイリスタTh3はオンしな
い。 If the leakage current is not flowing in the main circuit L,
The master thyristor Th 1 is off and the slave thyristor Th 2 is also off. The power supply voltage is divided into 1/2 by the voltage dividing resistors R 1 and R 2 , and this equal divided voltage is applied to the thyristors Th 1 and Th 2 , respectively, so that the leakage of the thyristors Th 1 and Th 2 is reduced. Even if there are variations in current, thyristors Th 1 and Th 2 each equally share 1/2 of the power supply voltage. Since the trigger voltage dividing resistors R 3 and R 4 also equally divide the power supply voltage by half, the potential difference between the connection point a and the connection point b is zero. Therefore, the two-terminal thyristor Th3 does not turn on.
漏電電流が主回路Ｌに流れると、零相変流器
ZCTがこれを検出し、検出出力は増幅器Ａによ
り増幅されて、トリガー信号として主のサイリス
タTh1のゲート・カソード間に与えられる。これ
によつて主のサイリスタTh1はオンし、接続点ａ
は電源ラインl2と同一電位に落ちる。これによつ
て接続点ａと接続点ｂとの間の電位差は電源電圧
の1/2となり、電源ラインl1がプラス極性で、電
源ラインl2がマイナス極性になつた時に、二端子
サイリスタTh3はオンし、従のサイリスタTh2の
ゲートがトリガーされる。従のサイリスタTh2が
オンすることによつてトリツプコイルTCに電流
が流れ、しや断部Ｓはしや断動作し、しや断状態
を保持する。 When leakage current flows into the main circuit L, the zero-phase current transformer
ZCT detects this, and the detection output is amplified by amplifier A and applied as a trigger signal between the gate and cathode of main thyristor Th1 . This turns on the main thyristor Th 1 , and the connection point a
falls to the same potential as the power line L2 . As a result, the potential difference between connection point a and connection point b becomes 1/2 of the power supply voltage, and when power supply line l1 has positive polarity and power supply line l2 has negative polarity, two-terminal thyristor Th 3 is turned on and the gate of slave thyristor Th 2 is triggered. When the secondary thyristor Th 2 is turned on, a current flows through the trip coil TC, and the shear section S performs a shearing operation and maintains the shearing state.
抵抗R1及びサージ吸収器Z1，Z2は雷サージな
どの異常電圧を吸収する。更に、サージ吸収器Z2
は、主のサイリスタTh1がオンしてから従のサイ
リスタTh2がオンするまでの瞬間的な時間に、電
源電圧の全電圧が従のサイリスタTh2に加わるこ
とによる破壊を防止するものである。 The resistor R 1 and the surge absorbers Z 1 and Z 2 absorb abnormal voltages such as lightning surges. Furthermore, surge absorber Z 2
This prevents damage caused by the full voltage of the power supply being applied to the slave thyristor Th 2 during the instantaneous time between the main thyristor Th 1 turning on and the slave thyristor Th 2 turning on. .
本考案におけるサイリスタは一方向のサイリス
タのみならず、双方向サイリスタをも用いること
ができる。また従のサイリスタは１個には限ら
ず、電源電圧の大きさに応じていくつも直列に接
続することができる。この場合には、分圧抵抗
R1、分圧抵抗R3及びサージ吸収器Z1を、増えた
従のサイリスタの数だけ増やせばよい。外部から
の異常電圧の侵入が他の手段によつて防止されて
いる場合にはサージ吸収器Z1はなくてもよい。二
端子サイリスタTh3の代りに、ゼナーダイオード
などの二端子スイツチング素子を用いることもで
きる。 The thyristor in the present invention can be not only a unidirectional thyristor but also a bidirectional thyristor. Further, the number of secondary thyristors is not limited to one, and a number of secondary thyristors can be connected in series depending on the magnitude of the power supply voltage. In this case, the voltage dividing resistor
R 1 , voltage dividing resistor R 3 and surge absorber Z 1 may be increased by the increased number of slave thyristors. If the invasion of abnormal voltage from the outside is prevented by other means, the surge absorber Z1 may not be provided. Instead of the two-terminal thyristor Th3 , a two-terminal switching element such as a Zener diode can also be used.
本考案においては、電圧バランス用の分圧抵抗
の分圧比に等しい分圧比を有し、サイリスタの数
に等しい数のトリガー用の分圧抵抗間の直列回路
を電源ライン間に接続し、電圧バランス用の分圧
抵抗間の接続点とトリガー用の分圧抵抗間の接続
点との間に、主のサイリスタがオンした時に二端
子間に印加される電圧より小さい降伏電圧を有す
る二端子スイツチング素子と、従のサイリスタの
ゲート・カソード間とを直列に接続したから、主
のサイリスタが外部からのトリガー信号によつて
オンすると、二端子スイツチング素子の二端子間
にトリガー用の分圧抵抗によつて分圧された分圧
電圧が印加され、二端子スイツチング素子がオン
し、従のサイリスタがオンする。したがつて、従
のサイリスタのトリガー回路を、トリガー用の分
圧抵抗及び二端子スイツチング素子から成る簡単
なものにすることができる。 In the present invention, a series circuit between the trigger voltage dividing resistors, which has a voltage dividing ratio equal to that of the voltage dividing resistor for voltage balancing and a number equal to the number of thyristors, is connected between the power lines, and the voltage is balanced. A two-terminal switching element with a breakdown voltage smaller than the voltage applied between the two terminals when the main thyristor is turned on, between the connection point between the voltage-dividing resistors for triggering and the connecting point between the voltage-dividing resistors for triggering. Since the main thyristor and the gate and cathode of the secondary thyristor are connected in series, when the main thyristor is turned on by an external trigger signal, a trigger voltage dividing resistor is connected between the two terminals of the two-terminal switching element. Then, the divided voltage is applied, the two-terminal switching element is turned on, and the secondary thyristor is turned on. Therefore, the trigger circuit of the secondary thyristor can be made simple, consisting of a trigger voltage dividing resistor and a two-terminal switching element.
図面は本考案の一実施例を示す回路図である。
Ｋ……制御回路、l1，l2……電源ライン、Th1
……主のサイリスタ、Th2…従のサイリスタ、
TC……トリツプコイル、R1，R2……電圧バラン
ス用の分圧抵抗、R3，R4……トリガー用の分圧
抵抗、Th3……二端子サイリスタ。
The drawing is a circuit diagram showing an embodiment of the present invention. K...control circuit, l1 , l2 ...power line, Th1
...Main thyristor, Th 2 ...Slave thyristor,
TC...trip coil, R1 , R2 ...divider resistor for voltage balance, R3 , R4 ...divider resistor for trigger, Th3 ...two-terminal thyristor.
Claims (1)
源ライン間に、外部からのトリガー信号によつて
オンする主のサイリスタと従のサイリスタと負荷
とを直列に接続し、各サイリスタにそれぞれ並列
接続された電圧バランス用の分圧抵抗の直列回路
を電源ライン間に接続した制御回路において、電
圧バランス用の分圧抵抗の分圧比に等しい分圧比
を有し、サイリスタの数に等しい数のトリガー用
の分圧抵抗の直列回路を電源ライン間に接続し、
電圧バランス用の分圧抵抗間の接続点とトリガー
用の分圧抵抗間の接続点との間に、主のサイリス
タがオンした時に二端子に印加される電圧より小
さい降伏電圧を有する二端子スイツチング素子
と、従のサイリスタのゲート・カソード間とを直
列に接続したことを特徴とする制御回路。 A voltage balancer in which a main thyristor that is turned on by an external trigger signal, a secondary thyristor, and a load are connected in series between power lines with a power supply voltage higher than the rated voltage of the thyristor, and each thyristor is connected in parallel. In a control circuit in which a series circuit of voltage dividing resistors for voltage balancing is connected between the power lines, the voltage dividing resistors for triggering have a voltage dividing ratio equal to that of the voltage dividing resistors for voltage balancing, and the number of triggering voltage dividing resistors is equal to the number of thyristors. Connect the series circuit between the power lines,
Two-terminal switching with a breakdown voltage between the connection point between the voltage-balancing voltage-dividing resistors and the connection point between the triggering voltage-dividing resistors that is less than the voltage applied to the two terminals when the main thyristor is turned on. A control circuit characterized in that an element and a gate/cathode of a slave thyristor are connected in series.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15343180U JPS631559Y2 (en) | 1980-10-29 | 1980-10-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15343180U JPS631559Y2 (en) | 1980-10-29 | 1980-10-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5778234U JPS5778234U (en) | 1982-05-14 |
| JPS631559Y2 true JPS631559Y2 (en) | 1988-01-14 |
Family
ID=29512686
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15343180U Expired JPS631559Y2 (en) | 1980-10-29 | 1980-10-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS631559Y2 (en) |
-
1980
- 1980-10-29 JP JP15343180U patent/JPS631559Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5778234U (en) | 1982-05-14 |
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