JPS62260565A - Drive circuit for actuator - Google Patents

Abstract

PURPOSE:To inhibit the heat generation of FETs due to switching loss by driving each of first and second MOSFET pairs connected in series with a power supply by first and second switching elements and displaying high-speed switching characteristics. CONSTITUTION:FET pairs 29a, 29b connecting a drain D for a P channel type FET 3a and a drain D for an N channel type FET 19a are connected in parallel between both poles of a main power supply 1, and a motor 8a for an actuator is connected between the nodes of each drain D. Drive circuits 17a, 17b for the FETs 3a, 3b are constituted of transistors(hereinafter called Tr) 4-7, diodes 9-12, etc., and drive circuits 18a, 18b for FETs 19a, 19b are also organized of Trs 27-28, 30, etc. When the FET 3a is turned ON at that time, the Tr 4 is turned OFF and the Tr 5 is turned ON. A reverse bias is applied to the Tr 6 only by a forward voltage section between a base and an emitter for the Tr 7 at that time, and the Tr 6 previously turned ON at the time of the OFF of the FET 3a can be turned OFF at high speed.

Description

Detailed Description of the Invention [Field of Application of the Invention] The present invention relates to a circuit for driving an actuator such as a motor using a MOS F'ET, and particularly to an actuator drive circuit suitable for suppressing heat generation due to switching loss of the MO8FET. It is something.

[Background of the invention]

The driving force of the actuator can be controlled by adjusting the current supplied from the power supply to the actuator, such as a motor, by turning on and off the switching element. At this time, if the switching operation speed of the switching element is slow, the element generates heat due to switching loss, and especially when driving a high-output actuator, the switching element may be destroyed by the heat generated.

-4. MOS FET, which is a type of switching element, has excellent characteristics such as low operating power and high-speed operation because it is a voltage controlled element, and is suitable as a switching element for driving an actuator. However, large-capacity MOS FETs have an input capacitance of several hundred pF or more between the dirt and source on the input side.
To drive the SFET, it is necessary to provide a circuit that charges and discharges the input capacitance in a short time.

Here, the operation of the MOS FET will be explained with reference to FIG. In this figure, 81 is an actuator to which electric power is to be supplied, here a DC motor (hereinafter simply referred to as a motor), and 1 is a DC power supply (hereinafter simply referred to as a motor) for supplying electric power to the motor 8a.
(hereinafter referred to as the main power supply), 3a is a P-channel type MO8FE
T (hereinafter simply referred to as FET). In such a circuit, F E is used to supply power to the motor 8a.
When a negative voltage is applied to the gate G of T3m and the source S, the source S and the fillet 4F0 of FET3m become conductive,
That is, it is in the on state and current A flows as shown by arrow A.

As mentioned above, FET3m has a large capacity of several hundred nine
Since it has an input capacitance of more than F, in order to operate it at high speed, it is necessary to charge and discharge the above input capacitance in a short time, that is, how to raise the r-to-source voltage VaS quickly. , it is important to decide whether to stand down or not.

Figure 18 is a diagram showing a drive circuit for a conventional actuator (here, the motor 8m) using such an FET 3m as a switching element, in which the FET 3a in the figure is turned on to supply power to the motor 8a from the main power supply l. The button to do this sends the drive signal V, (hereinafter abbreviated as v1) to the transistor 4.
is turned on (hereinafter simply referred to as high), transistor 4 is turned on, and current B flows through the path of arrow B. The input capacitance of FET3m is charged by this current B, and the y-to-source voltage Vas (hereinafter abbreviated as "G8") rises, causing FET3m to turn on, and the drain current ID (hereinafter abbreviated as ID) to motor 8& as indicated by arrow C. ) flows to obtain the driving force of the motor 8a.

In order to turn off FET3m and cut off the current supplied to motor 8m, set ■ to the voltage at which transistor 4 turns off (hereinafter simply referred to as low), turn it off, and change the input capacitance of FET3a to the voltage shown by the arrow. The stored charge is discharged, the FET 3a is turned off, and the power to the motor 8& is cut off. At this time, the energy stored in the inductance of the motor 8a causes a current E to flow through the diode 23 as indicated by the arrow E.
flows.

The drain-source voltage VOS of "j+■G8+ FET3m" in Fig. 18 (hereinafter abbreviated as ■os)
,■. and the energy consumed by FF and T3 during switching, that is, vDs. The time chart of FIG. 19 shows the energization.

The energy consumed per unit time in the above F E T 3m, that is, the switching loss PLoss (hereinafter abbreviated as Ploms) can be determined by the following equation (1) by integrating the product of vGs and ID. Here, t is time and 1r is VDI of FET3m! Rise time, tf is F
os fall time of E T 3m, f is the switching frequency of FET 3m.

From this equation (1), if f is constant, the integral interval [0, tr]
.

It can be seen that the larger [:O, tf] is, the larger Ptoss becomes. This Ptoss causes FET3a to generate heat and is released into the atmosphere, but if this is too large, the FET
Not only will it overheat and destroy the 3m, but it is also unfavorable from the point of view of energy efficiency. For this reason, it is necessary to suppress the heat generation of FETaa as much as possible, and considering that the voltage of the main power supply 1 is generally several tens [73 or more], the resistor 13
．． 14 cannot be made smaller. Therefore, V as shown in FIG. 8 is the input capacitance of FET3m and resistance 13.1
It changes slowly with a time constant determined by 4, and therefore t
rt”f cannot be kept small.

As described above, in the conventional circuit, the dirt-source voltage V of MOS FET 3a. 8 cannot be started up and stopped at high speed. Therefore, there was a problem in that the high-speed switching characteristics of the MOS FET 3a could not be fully utilized and the FET 3 would generate heat.

[Purpose of the invention]

The present invention has been made to solve the above-mentioned problems, and it is possible to drive a MOS F'ET used as a switching element for driving an actuator at high speed, and to fully exhibit its high-speed switching characteristics. MOS FET due to switching losses
An object of the present invention is to provide an actuator drive circuit that can suppress heat generation.

[Summary of the invention]

The circuit of the present invention includes a first power source and a first power source connected in series between both poles of the first power source. Second MOS FET
at least two MOS FET pairs consisting of the first . In a circuit that drives an actuator whose input terminal is connected to the connection point of the second MOS FET, the second
A first charging/discharging means is provided to charge/discharge the input capacitance of the MOS IT, and the first power supply and the second MOS F
The first circuit operates on and off using the ET connection point as a reference potential.
and a first MOS FET connected in series between the output terminal of the first switch element and the connection point of the first power supply and the first MOS FET. a second current limiting element; a second switch element that operates on and off when the potential at the connection point of the second current limiting element changes with respect to the normal potential; A second charging/discharging means is provided for charging and discharging the input capacitance of the MOS FET, and when the second switching element is turned on, a part of the current to the input terminal is applied to the output terminal of the second switching element. By providing means for applying a reverse voltage to the input terminal of the switch element when the switch element is turned off, the turn-off operation of the second switch element is made faster, and the first MO
The above object is achieved by making it possible to charge and discharge the input capacitance of the SFET at high speed.

[Embodiments of the invention]

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of an actuator drive circuit according to the present invention. In FIG. 1, the same reference numerals as in FIG. 18 indicate the same or corresponding parts. In Figure 1, the drain D of P-channel FET 3m and the N-channel FET 19
The drain D of m is connected to the FET pair 29 a and 29
b is connected in parallel between both poles of main power supply 1, and FET pair 29
A motor 8a as an actuator is connected between the drain D connection points of a and 29b.

First, P channel type FET 3m, 3b
The drive circuits 17m and 17b will be explained below, but since both drive circuits 17m and 17b have similar configurations, the drive circuit 17m will be explained here based on FIG. In FIG. 2, 4 is an NPN transistor (first switching element) for driving FET 3m, the collector of which is connected to the first and second current limiting elements, here resistors 13 and 14.
are connected in series to the positive terminal of main power supply (first power supply) 1 and FET.
It is connected to the connection point with the source S of 3m, and its emitter is connected to the negative electrode of the main power supply 1.

The connection point of the resistors 13 and 14 is connected to the collector of the NPN transistor (second switch element) 5 through the diode 9 in the forward direction, and is connected to the collector of the transistor 5 through the diode 10 in the forward direction. connected to. The transistor 5 has a collector connected to the positive terminal of the main power supply 1 via a resistor 15, and an emitter connected to a DC power supply (hereinafter referred to as a second power supply) for driving the FET 3a whose positive terminal is connected to the positive terminal of the main power supply 1. ) is connected to the negative pole of 2.

Note that the voltage of the second power supply 2 is lower than the voltage of the main power supply 1,
For example, it is set to the first name.

11 is a diode connected in antiparallel to the diode IO, and 12 is a diode (voltage limiting element) connected between the pace emitter of the transistor 5 in the opposite direction. Reference numerals 6 and 7 are NPN type and PNP type transistors, their paces are commonly connected and directly connected to the collector of the transistor 5, and their emitters are commonly connected and directly connected to the G of the FET 3a. Further, the collector of the transistor 6 is directly connected to the positive electrode of the main power source 1, and the collector of the transistor 7 is connected to the negative electrode of the second power source 2 via a resistor 16.

Next, the operation of the drive circuit 17m for the FET 3m will be explained. In order to turn on the FET 3m, first the transistor 4 is turned off, and a pace current Il (hereinafter abbreviated as "I") is caused to flow through the transistor 5 as shown by the arrow DI, and the transistor 5 is turned on. At this time, as described in Part 1, the diodes 9 and 10 cause 2 to flow, and part of it flows into the collector of the transistor 5 through the diode 9, resulting in oversaturation of the transistor 5 (storage time t,
This prevents long periods of time. When transistor 5 is turned on, current D2 flows along the path indicated by arrow D2, turning on transistor 7, and as a result, current D3 flows along the path indicated by arrow D3, charging the input capacitance of FET 3a and turning on FET 3m.

To turn off the FET 3a, the transistor 4 is turned on and a current E1 is caused to flow by the main power supply 1 along the path indicated by the arrow E1. At this time, a slight voltage is generated in the diode 12 due to a forward voltage drop, and this becomes the reverse bias voltage of the transistor 5. For this reason, the charge accumulated in the transistor 5 is rapidly drawn out, and as shown in Fig. 3, the turn-off time "off" described later can be significantly shortened. When the transistor 5 is turned off, the charge accumulated in the input capacitance of the FET 3m is starts discharging along the path of arrow E2, transistor 6 is turned on by this current E2, and the remaining charge is discharged at a high speed along the path of arrow E3.Therefore, FET 3m is also turned off at high speed. 1. When the current E2 due to discharge flows, a reverse bias voltage is applied to the transistor 7 by the forward voltage drop between the pace emitter of the transistor 6, so the transistor 7, which was on when the FET 3m was on, is turned off at high speed.

Also, to turn on FF 73m again, transistor 4
is turned off and transistor 5 is turned on. As a result, the stain current D2 flows, and the FET 3a is turned on again in the same manner as described above, but at this time, the current D2 reverse biases the transistor 6 by the forward voltage between the pace emitter of the transistor 7. The transistor 6, which was on when the FET 3m was turned off, is turned off at high speed.

In addition, since the second power supply 2 is usually 20 V or less,
Even if the resistors 15 and 16 are each set to a small value, the problem of heat generation does not occur. Therefore, the current E2. The size of D3 can be set appropriately, and from this point of view, transistor 6.
7 can be turned on faster.

As described above, the transistors 6 and 7 are not required to be turned on and off at high speed, and the high speed drive (on,
off). That is, the transistor 6.7 and FET3a can all be turned on and off at high speed.

The reason why oversaturation of the transistor 5 can be prevented by the diodes 9 and 10 will now be explained in detail. FIG. 4 is a circuit diagram illustrating the operation of the transistor 5. In FIG. 4, when ■ becomes high, IN flows. At this time, if the collector current Ic (hereinafter abbreviated as ■c) is constant, then the pace-emitter voltage V□ (hereinafter abbreviated as V) and the collector-emitter voltage Vcz
(hereinafter abbreviated as "cz") is as shown in Fig. 5. In other words, vBffi is almost constant regardless of I3, Vct decreases with the increase of , and at point P, Vct
becomes smaller than Vllffi.

Figure 6 shows vl and V when the resistor 22 is selected appropriately so that the operating point when the transistor 5 is turned on is point P.
5 is a time chart showing the relationship between ct and ct.

In FIG. 6, the turn-on time t is the time from when vt goes high until transistor 5 turns on and vcE goes low. n (hereinafter abbreviated as t.n), the time from when vl becomes low until the transistor 5 is turned off and vc starts to rise is defined as the accumulation time 1. (hereinafter abbreviated as t), the time from when vI goes low until the transistor 5 turns off and vcg goes high is the turn-off time t. ff (hereinafter abbreviated as t.ff).

FIG. 7 is a time chart showing the relationship between vl and van when resistor 22 is decreased and ■1 is increased in FIG. t to be supplied. Although n becomes shorter, extra charge is stored in the base. Therefore, when the transistor 5 is turned off, the time t3 required for the charge to be discharged becomes longer, and the operating time of the transistor 5 becomes longer as a whole.

FIG. 8 shows that the resistor 22 in FIG.
This is a time chart showing the relationship between V and "c+e" when I is made small. That is, when I is made small, t.

becomes shorter, but ton increases, and vcm when turned on becomes higher, resulting in an increase in power loss by the transistor 5 and the problem of heat generation.

The operation of the transistor 5 shown in FIG. 6 is operating at point P in FIG. 5, so it has a slightly faster operating speed as a whole compared to FIGS. 7 and 8, but the operating speed of the FET 3a itself is The comparison is still not enough.

Further, as shown in FIG. 9, the construction of the transistor 5 is performed. When vo and V increase, the intersection of vo and V also moves to the right from point P to point P' to point P', and good operation cannot be maintained if III is kept constant.

Below is the construction of transistor 5. A circuit that maintains relatively good operation even when the value fluctuates will be described. Figure io is an example of such a circuit. In the circuit shown in FIG. 10, a diode 1 is connected from the resistor 22 to the base of the transistor 5.
0, and a diode 9 was provided from the resistor 22 toward the collector of the transistor 5. Also, the resistor 22 is the transistor 5
It is selected to be small in advance so that enough ■3 can flow to the area. FIG. 11 is a time chart showing the relationship between V and vcE in the circuit of FIG. 10.
The circuit shown in diagram O will be explained. First, when vI becomes high and the current begins to flow to transistor 5, transistor 5 is off, so vcm is the same voltage as power supply 2. On the other hand, point Q in FIG. 10 has only a small potential equal to the forward voltage drop between diode 10 and the base-emitter of transistor 5 with respect to the negative side of power supply 2, so diode 9 has a reverse voltage. It will take a while.

Therefore, all the current flowing through the resistor 22 passes through the diode 10. Therefore, since a sufficiently large current flows, t of the transistor 5 as shown in FIG. n becomes shorter.

Furthermore, once the transistor 5 is turned on, the resistor 22 is selected to be small so that the voltage is sufficiently large, so that the transistor 5 tends to operate on the right side of the point P in FIG.

However, when vCffi becomes smaller than VIIg, the potential of the collector of transistor 5 becomes lower than the potential of point Q, so a forward voltage is applied to diode 9, and part of the current flowing through resistor 22 flows through diode 9 to the collector of transistor 5. Reduce inflow IB. This decrease in I is V. This continues until V14 and V14 become equal, so that transistor 5 remains on at point P in FIG.

This is transistor 5! , is automatically adjusted to an appropriate size, and t is automatically adjusted to an appropriate size as shown in FIG. f is also relatively short. In other words, in the circuit shown in FIG. The transistor 5 is kept in a relatively good state (both ton and t.ff are short) even if the characteristics of each element change or the characteristics of each element vary.
It can be operated with.

Therefore, in FIG. 1, one or both resistors 13 and 140, which are equivalent to resistor 22 in FIG.
If , is selected appropriately, a sufficient 1. and that t. n is short. Furthermore, in FIG. 1, the diode 9. The transistor 5 is prevented from oversaturation by lO, and when it is off, a reverse bias voltage is applied by the main power supply 1, so that
Off is also short. Furthermore, at this time, the transistor 5 is protected because the diode 12 limits the reverse bias voltage of the transistor 5, and even if the voltage of the main power supply 1 fluctuates, a constant reverse bias voltage can be applied.

Next, drive circuit 1 for N-channel FETs 19m and 19b.
Since both drive circuits 18m and 18b have similar configurations, the drive circuit 18m will be explained here based on FIG. 12. 1st
In Figure 2, 30 is an NPN transistor for driving FET 19a, and its emitter is connected to the negative terminal of main power supply 1.
27 and 28 are of NPN type. and PNP type transistors, their bases are commonly connected and directly connected to the collector of the transistor 30, and their emitters are commonly connected and directly connected to the GK of FET19m. In addition, the collector of the transistor n is connected to the power supply 2 through a resistor 26.
The collector of the transistor n is connected to the negative terminals of the main power supply 1 and the power supply 20.

Next, the drive circuit 18 of such FET 19 m
The operation of m will be explained. To turn on FET 19a, first turn off transistor 30 and turn the arrow F
A current F1 is caused to flow through the path No. 1, and the transistor 27 is turned on. As a result, current F2 flows along the path of arrow F2, causing F
E T 19 m input capacity is charged, and this F E T
19 Turn on a.

To turn off F F, T 19 a, transistor 3
0 is turned on to discharge the charge stored in the input capacitance of FET19m along the path of arrow H1. The transistor 28 is turned on by the current H1 caused by this discharge, and the remaining charge is discharged at a high speed along the path indicated by the arrow H2, resulting in F E T 19 m
is turned off. Note that when the current H1 due to the discharge flows in the path indicated by the arrow H1, a reverse bias voltage is applied to the transistor 27 by the amount of the forward voltage drop between the pace emitter of the transistor 28, so that the transistor 27 is turned on when FET19a is turned on. Turn off the transistor nails that were being used at high speed.

After that, in order to turn on F F T 19 a again, the transistor 30 is turned off and the current F1 flows, but at this time, the current Fl applies a reverse bias to the transistor 27 by the forward voltage between the pace φ emitter of the transistor 27. , F ET 19 The transistors that were on when m was turned off are turned off at high speed.

Note that, like the power source 2, the power source 20 is also normally 20 V or less, so even if the resistor 25 is set to a small value, no problem of heat generation will occur. Thereby, the magnitude of the current F1 can be set appropriately, and from this point of view as well, the transistors 27 and 28 can be turned on and off quickly. Therefore, transistor 27.2
The transistor 8 turns on and off at high speed like the transistor 6.7, and does not interfere with high-speed driving of F E T 19 m.

FIG. 13 is a time chart in the circuit of the present invention shown in FIG. In this Fig. 13, FET3m,
19m, 3b, 19b drive signal "11 e v
l 2 + vi 3 e "14 is applied as shown in the figure, an armature voltage vM is applied to the motor 8&. This causes the motor 8a to rotate, but in the illustrated example, the time when the positive voltage is applied is different from the time when the positive voltage is applied. The motor 8a rotates in the forward direction because it is longer than the time it takes.
9m, 3b, 19b drive signal vI 1 v ”l
By giving 2 r ”13 r vl 4 appropriately, F E T 3m, 19m, 3b, 1
The output of the motor 8 can be freely controlled by changing the armature voltage Vi while suppressing the switching loss Ptoss caused by the motor 9b.

As explained above, in the circuit of the present invention, there are 3m FETs.

3b, 19a, IQ r-to-source voltage■. s
can be started up and stopped down at high speed, therefore MOS FET (FET 3m, 3b, 19a,
Taking full advantage of the high-speed switching characteristics of t9b),
Heat generation due to switching loss Ptoss can be suppressed.

In addition, in the embodiment shown in FIG. 1, D is used as the actuator.
Although the case has been described in which the C motor 8a is used and driven, a three-phase AC motor may also be used as the actuator. In this case, for example, as shown in FIG. 14, a P-channel MO8FET 3c and an N-channel MO8F
A MOS FET pair 29e connected to each drain of the ET 19c is connected to a MOS FET pair 29a.

29 b and a MOS FET pair 29 a
The input terminal of the three-phase AC motor 8b is connected to the connection point of each drain of r29b+29c. and FET3
a, 3b, and 3c are driven by drive circuits 17m, 17b, and a drive circuit 17e similar to these;
E T 19a, 19b, 19e are connected to drive circuits 18a, 18b and a drive circuit 18e similar to these.
The AC motor 8a is driven by the AC motor 8a.

In addition, in the circuit of the present invention, in order to further increase the reverse bias voltage of the transistor 5, a plurality of diodes 12, here two diodes 12m and 12b, are connected in series between the pace emitter of the transistor 5 as shown in FIG. Furthermore, for the same purpose, the diode 12 may be provided by connecting a Zener diode 12c and a diode 12a in series, as shown in FIG.

〔Effect of the invention〕

As described above, according to the present invention, the input capacitance of a MOSFET that drives an actuator such as a DC motor or an AC motor can be charged and discharged in a short time, so the MOSFET can be driven at high speed, and switching loss can be reduced. It is possible to suppress the heat generation of the MO8FET due to the above. For this reason, even if the switching frequency is increased to higher than the audible frequency, for example 20kHz or higher, heat generation due to switching loss of the MOS FET will not be a problem, and therefore it is possible to suppress noise generated from the actuator due to current pulsation. There are side effects.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the circuit of the present invention, and FIG.
A circuit diagram for explaining the drive circuit of the P-channel MO8FET shown in the figure, FIG. 3 is a time chart showing the operation of the transistor 5 in FIG. 2, and FIGS. Circuit diagram for explanation, 5th
9 and 9 are characteristic diagrams of the transistor 5, FIGS. 6 to 8, and 11 are time charts, and FIG.
The figure is a circuit diagram for explaining the drive circuit of the N-channel type MO8FET in FIG. 1, FIG. 13 is a time chart thereof, and FIGS. 14 to 16 are circuit diagrams showing other embodiments of the present invention. Fig. 17 is a circuit diagram for explaining the operation of the MOS FET, Fig. 18 is a diagram showing a conventional circuit, and Fig. 19 is a time chart for explaining the operation of the conventional circuit. 1 power supply), 2...second power supply, 3
m, 3b, 3e -MOS FET (first MO
S FET), 4.5...transistor (1st, 2nd
switch element), 6, 7.27.28.30-...
Transistor, 8a-DC motor (actuator)
, 8b...AC motor (actuator), 9-12
...Diode, 13.14...Resistor (1st, 2nd
current limiting element), 19m, 19b. 19 c -MOS F] IET (second MOSFE
T), 29a, 29b. 29 c-MOS FET pair.

Claims (1)

[Claims] 1. A first power source, a first MOS FET whose source is connected to one electrode of the first power source, and a source connected to the other electrode of the first power source, the first MOS
A second MOS whose drain is connected to the drain of the FET
and a plurality of MOS FET pairs each configured with a FET, the first and second MOS FETs of each MOSFET pair
In a circuit for driving an actuator whose input terminal is connected to a FET connection point, a first charging/discharging means for charging and discharging the input capacitance of the second MOS FET, the first power supply and the second MOS a first switch element that operates on and off using a connection point with the FET as a reference potential;
first and second current limiting elements connected in series between the output terminal of the first switching element and the connection point of the first power supply and the first MOS FET;
a second switch element that operates on and off when the potential at the connection point of the current limiting element changes with respect to the reference potential; and the on and off operations of this second switch element,
a second charging/discharging means that conducts between the second power supply and the input capacitor of the first MOSFET to charge the input capacitor, or conducts between the two poles of the input capacitor to discharge the charged charge; , a shunt means for supplying a part of the current flowing toward the input terminal of the second switch element to its output terminal when the second switch element is turned on; and a reverse voltage is applied to the input terminal when the second switch element is turned off. An actuator drive circuit characterized by comprising a reverse voltage applying means. 2. The reverse voltage applying means connects one or more voltage limiting elements connected between the input terminal of the second switch element and the ground terminal, and the input terminal of the second switch element and the first 2. The actuator drive circuit according to claim 1, further comprising an element that conducts between a connection point of the second current limiting element and a connection point of the second current limiting element at least when the first switching element is turned on.