JPS6223224A - Dc restoration circuit for digital repeater - Google Patents

Abstract

PURPOSE:To attain DC restoration with high accuracy and less interference between codes in response to an input signal form by obtaining a maximum value and a minimum value of an input signal amplitude, comparing its intermediate value with a reference signal to obtain the difference of the both and applying negative feedback control to the input signal. CONSTITUTION:A circuit composing of a diode D, a capacitor C1 and a resistor R1 detects a maximum amplitude of an input signal VI1 and a circuit composing of a diode D2, a capacitor C2 and a resistor R2 detects a minimum amplitude of the input signal VI1. After the impedance is converted from a high to a low from each detection value by buffer circuits Bu1, Bu2, the result is given to division resistors R3, R4. The division resistors R3, R4 add the maximum amplitude and the minimum amplitude, outputs an intermediate signal of both the amplified values from the connecting point and the value is given to a differential amplifier Am. The differential amplifier Am obtains a difference between the intermediate signal and a reference voltage VR, the difference is amplified by a prescribed amplification factor set by resistors R3-R5 and its comparison signal is outputted. A transistor Q superimposes a bias signal onto the input signal VI1 via a resistor R7.

Description

[Detailed Description of the Invention] (Field of Industrial Application) The present invention relates to a DC regeneration circuit for a digital repeater used in a digital wired transmission system using coaxial cables, optical cables, etc., or in a digital wireless transmission system. be.

(Prior Art) A digital repeater is used in digital communication systems and is a device that reproduces a signal that is distorted in the amplitude direction and time direction by a digital transmission circuit, or has noise added to it, back to the original signal. . This device is comprised of circuits such as a waveform shaping circuit, a waveform regeneration circuit, a timing regeneration circuit, and a modulation/demodulation circuit. Here, as one of the waveform shaping circuits, there is a DC regeneration circuit (also called a clamp circuit) for fixing the voltage of a part of the input waveform to a constant voltage6. Conventionally, such a DC regeneration circuit , for example 7? ,2
There was something like the picture. The configuration will be explained below.

FIG. 2 is a circuit diagram showing an example of the configuration of a conventional DC regeneration circuit.

In FIG. 2, 1 is an input terminal f to which an input signal v■ is input.
, and 2 are output terminals that output an output signal vO.

A capacitor 3 is connected between the input and output terminals 1 and 2, and a parallel circuit of a diode 4 and a resistor 5, and a power supply 6 that provides a bias voltage VB are connected in series between the capacitor 3 and the ground. There is.

Next, the operation will be explained with reference to the signal waveform diagram in FIG.

It is assumed that the circuit shown in Figure 2 has ideal conditions: the output impedance of the drive circuit that supplies the input signal Vl is zero ohm, the forward resistance of diode 4 is zero ohm, and its reverse resistance is infinite. .

First, an input signal "qvr" in the form of a rectangular pulse train having an amplitude V
When is applied to input terminal 1, at the rising edge of input signal vI, a total of 3 becomes short-circuited and a negative pulse appears, but since diode j becomes conductive, the output signal vO is bias voltage The voltage becomes a voltage (VB-VD) lower than VB by VD by the forward voltage drop F of the diode 4. In the sharp portion of the input signal VI, the capacitor 3 is short-circuited and a positive pulse appears, but the diode 4 is turned off, so the output signal VO has the input signal amplitude V.

In the flat part of the input signal Vl, the output signal VO tends to decrease exponentially with the time constant RC determined by the capacitor 3 C and the resistor 5 R, but the time constant RC is set larger than the pulse repetition period. Therefore, the output signal vO remains approximately constant.

At the next falling edge of the input signal vI, the output signal vO becomes the voltage (VB-VD) again, thus the baseline of the input signal pulse is clamped to the voltage level (VB-VD).

(Problem to be solved by the invention) However, although accurate lamp operation can be expected under ideal conditions in the circuit with the above configuration, in actual circuits, it is difficult to make the output impedance of the drive circuit close to zero ohm. Moreover, since the forward resistance of the diode 4 is zero ohm and the reverse resistance is not infinite, the ratio between the two resistances is not so large. Therefore, the input signal V
If l is a signal containing pulses with a long duration, the clamping operation will not be performed sufficiently, and this will cause code amount interference in the DC reproduction signal passed through the DC reproduction circuit, causing signal loss at the identification point in the digital repeater. Noise ratio (S/N)
Due to the deterioration, there was a problem in that the code error rate characteristic, which is 13% of the quality evaluation scale of a digital transmission system, worsened.

The present invention provides a DC regeneration circuit which solves the problem of the prior art, which is that the clamping operation is not performed sufficiently.

(Means for solving the problem) In order to solve the problem No. 11, the present invention provides a peak value detection circuit for detecting the maximum value and minimum value of the input signal amplitude in a DC regeneration circuit for a digital repeater. an intermediate value generation circuit that generates an intermediate value signal from the maximum value and the minimum value; a comparison circuit that compares the intermediate value signal with a reference signal and outputs a comparison signal corresponding to the comparison signal; and a bias generation circuit that negatively feeds back the input bias signal and superimposes it on the input signal.

(Function) According to the present invention, since the DC regeneration circuit for a digital repeater is configured as described above, the peak value detection circuit detects the maximum value and minimum value of the amplitude of the input signal, and based on the detected values, An intermediate value generation circuit produces an intermediate value signal. The comparison circuit compares the intermediate value signal with the reference signal and outputs a corresponding comparison signal, which is applied to the bias generation circuit. The bias generation circuit generates a bias signal according to the comparison signal, feeds it back negatively, and superimposes it on the human input signal. As a result, even if the input signal includes a pulse with a long duration, accurate ramp operation can be performed. Therefore, the above problem can be eliminated.

(Embodiment) FIG. 1 is a block diagram of a reproducing circuit showing an embodiment of the present invention.

In FIG. 1, 11 is an input terminal to which an input signal Vl is manually input, and 12 is an output terminal for outputting an output signal vO. An output terminal 12, a maximum value detection circuit 14, and a minimum value detection circuit I5 are connected to the input terminal 11 via a coupling capacitor 13 for removing DC components. Maximum value detection circuit 1
4 is a circuit that detects the maximum value of the amplitude of the input signal VII after DC component removal, and a minimum value detection circuit 15 is a circuit that detects the minimum value of the input signal amplitude. 15 constitutes a peak value detection circuit.

An intermediate value generation circuit 16 and a comparison circuit 17 are connected to the output sides of the maximum value detection circuit 14 and the minimum value detection circuit 15. The intermediate value generation circuit 16 is a circuit that adds the maximum value and minimum value of the input signal amplitude and generates a signal of the intermediate value. The comparison circuit 17 is a circuit that compares the reference voltage VR and the intermediate value signal, determines the difference between the two signals, and outputs the comparison signal.

A low-pass filter circuit 18 and a bias generation circuit 19 constituting a negative feedback circuit are connected to the output side of the comparison circuit 17. The low-pass filter circuit 18 is a circuit that removes high frequency components of the comparison signal. The bias generation circuit 19 is a circuit that generates a bias signal corresponding to the comparison signal from which the high frequency component has been removed and adds it to the input signal Vll.

Next, the operation will be explained.

First, when an input signal VI in the form of a rectangular pulse train is input to the input terminal 11, the DC component is removed by the coupling capacitor 13, and then the input signal VI is supplied to the maximum value detection circuit 14 and the minimum value detection circuit 15. The maximum value detection circuit 14 detects the maximum amplitude value of the input signal VII after removing the DC component, and the minimum value detection circuit 15 detects the minimum amplitude value of the input signal VII, and generates an intermediate value from these rain detection values. to circuit 1B. The intermediate value generation circuit 18 adds the maximum amplitude value and the minimum amplitude value, determines the intermediate value between the maximum value and the minimum value without depending on the amplitude of the input signal vI, and provides the intermediate value signal to the comparison circuit. The comparison circuit 17 compares the applied reference voltage VR and the intermediate value signal, determines the difference, and outputs a comparison signal. This comparison signal is sent to the bias generation circuit 13 after its high frequency components are removed by the low-pass filter circuit 18 . The bias generation circuit 19 generates a bias signal according to the comparison signal after the high frequency component has been removed, superimposes this on the input signal VI after the DC component has been removed by the coupling capacitor 13, and generates the output signal V.
It is sent out from the output terminal 12 as O.

Here, the low-pass filter circuit 1 and the bias generation circuit 19 constitute a negative feedback circuit, and convert the intermediate value signal to the reference voltage VR.
Since the balance operates so as to be equal to , accurate balance operation is performed, and it is possible to generate a highly accurate direct bite signal.

In this embodiment, depending on the transmission speed of the input signal VI and the duration of the pulse included in the input signal vI, the constant of one day of the low-pass filter circuit is selected to an appropriate value or changed, so that the sign can be changed. It is possible to provide a DC regeneration circuit for a digital repeater that is close to ideal and free from quantity interference.

For example, if the transmission speed of the input signal VI is high and the pulse duration is short, the low-pass filter circuit 18 is shut off [4 Intersymbol interference can be reduced by increasing the wave number and speeding up the loop response. . In addition, the transmission speed of the input signal VT is slow,
When the pulse duration is long, code amount interference can be reduced by lowering the cutoff frequency and slowing down the loop response.

Further, the circuit of this embodiment is suitable for high-speed transmission.

That is, in order to perform high-speed operation in a conventional circuit, the drive circuit that supplies the input signal VI must have a low output impedance value at high frequencies, and the capacitance of the diode 4 and resistor 5 must be made small to achieve high-speed operation. It is necessary to take measures such as making the circuit configuration operable. However, in this embodiment, these countermeasures are not required, and high-speed operation can be easily performed simply by speeding up the loop response.

Note that in FIG. 1, depending on the form of the input signal VI, the initial objective can be achieved even if the coupling capacitor 13 and the low-pass filter circuit 18 are omitted. Therefore, the coupling capacitor 13 and the low-pass filter circuit 18 are not essential circuit elements.

FIG. 4 is a diagram showing a specific example of the circuit configuration of FIG. 1.

In this circuit, the maximum value detection circuit 14 includes a forward diode D1, a capacitor [01 branch-coupled to it, a resistor R1,
and a buffer circuit Bul for impedance conversion such as an operational amplifier. Similarly, the minimum value detection circuit 15 is composed of a reverse diode D2, a capacitor C2 and a resistor R2 branch-coupled thereto, and a bar-fur circuit Bu2. The intermediate value generation circuit 16 is composed of dividing resistors R3 and R4 having equal resistance values and connected in series between the output sides of the buffer circuits Bul and Eu2. The comparison circuit 17 includes a differential amplifier Am, a reference voltage source E connected to its (+) side input terminal, and a resistor R5 connected between its (-) side input terminal and its output terminal. It is configured. The low-pass filter circuit 18 includes a T-shaped resistor R6 and a capacitor C4. The resistor R8 and capacitor C4 are either fixed or variable. Further, the bias generation circuit 19 is composed of an emitter follower type amplifier including a transistor Q, a bias resistor R7, and the like.

Next, the operation of the DC regeneration circuit configured as described above will be explained with reference to the input/output signal waveform diagram of FIG.

First, when the input signal VI is applied to the input terminal 11, the DC component is removed by the capacitor 13, and the input signal VII after the DC component is removed is passed through the diodes DI and D2 as shown in FIG.
be praised. One diode D, capacitor CI, and resistor R1 detect the maximum amplitude value of the input signal VII, and the other diode D2, capacitor C2, and resistor R2 detect the minimum amplitude value of the input signal VII. Each detected value is impedance-converted from high impedance to low impedance by each buffer circuit Bul and Eu2, and then applied to dividing resistors R3 and R4. Dividing resistors R3 and R4 add the maximum amplitude value and the minimum amplitude value, and output an intermediate value signal of both amplified values from the connection point thereof, which is applied to the differential amplifier As. The differential amplifier As+ determines the difference between the intermediate value signal and the reference voltage VR, and applies the difference to the resistors R3, R4, and R5.
The comparison signal is amplified at a predetermined amplification degree set by . The comparison signal is applied to the base of the transistor Q after high frequency components are removed by the resistor R6 and the capacitor C4. Transistor Q converts the input signal to the base from high impedance to low impedance to generate a bias signal.

The bias signal is gained through the resistor R7 to the input signal Vll.

This DC regeneration circuit operates so that the level of the intermediate value signal is always constant by increasing the loop gain of the negative feedback loop. Therefore, the intermediate value signal shown by the broken line of the output signal waveform in FIG. 5 becomes constant, and as a result, the output signal VO after DC regeneration has a waveform close to the ideal.

(Effects of the Invention) As described in detail above, according to the present invention, the maximum and minimum values of the input signal amplitude are determined, the intermediate value is compared with the reference signal, the difference between the two is determined, and the difference is calculated. Since the configuration is such that negative feedback control is applied to the input signal so that the input signal becomes zero, it can be expected that high-precision DC reproduction with little intersymbol interference depending on the input signal format can be performed.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a DC regeneration circuit showing an embodiment of the present invention, Fig. 2 is a circuit diagram of a conventional DC regeneration circuit, Fig. 3 is an input/output signal waveform diagram of Fig. 2, and Fig. 4 is a block diagram of a DC regeneration circuit according to an embodiment of the present invention. FIG. 1 is a specific circuit diagram, and FIG. 5 is an input/output signal waveform diagram of FIG. 4. 11...Input terminal, 12...Output terminal, 13...Coupling capacitance, 14...Maximum value detection circuit, 15...Minimum Value detection circuit, 16...
...Intermediate value generation circuit, 17...Comparison circuit,
18...Low-pass filter circuit, 19...Bias generation circuit.

Claims (1)

[Scope of Claims] A peak value detection circuit that detects the maximum value and minimum value of the amplitude of an input signal; an intermediate value generation circuit that generates a signal having an intermediate value from the maximum value and the minimum value; and the intermediate value. a comparison circuit that compares the signal with a reference signal and outputs a corresponding comparison signal; and a bias generation circuit that generates a bias signal according to the comparison signal, negatively feeds back the bias signal, and superimposes it on the input signal. A DC regeneration circuit for a digital repeater, comprising: