JPS6152997B2 - - Google Patents

Info

Publication number
JPS6152997B2
JPS6152997B2 JP11552580A JP11552580A JPS6152997B2 JP S6152997 B2 JPS6152997 B2 JP S6152997B2 JP 11552580 A JP11552580 A JP 11552580A JP 11552580 A JP11552580 A JP 11552580A JP S6152997 B2 JPS6152997 B2 JP S6152997B2
Authority
JP
Japan
Prior art keywords
light emitting
transistor
semiconductor light
capacitor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP11552580A
Other languages
Japanese (ja)
Other versions
JPS5739593A (en
Inventor
Isatake Sawano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP11552580A priority Critical patent/JPS5739593A/en
Publication of JPS5739593A publication Critical patent/JPS5739593A/en
Publication of JPS6152997B2 publication Critical patent/JPS6152997B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/04Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042Electrical excitation ; Circuits therefor

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Semiconductor Lasers (AREA)
  • Led Devices (AREA)
  • Optical Communication System (AREA)

Description

【発明の詳細な説明】 本発明は半導体よりなる発光素子の駆動回路に
関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a driving circuit for a light emitting element made of a semiconductor.

近年、光通信が発達するにつれて、その伝送容
量の大容量化がますます重要視されてきている。
In recent years, with the development of optical communications, increasing the transmission capacity has become increasingly important.

従つて、光通信に使用する半導体素子であるレ
ーザダイオード及びLED(Light Enitting
Diode)を高速に動作させる必要がある。
Therefore, laser diodes and LEDs (Light Enitting
diode) must operate at high speed.

従来、上記半導体発光素子を高速動作させるた
めに、第1図に示すように、トランジスタQ1
エミツタ端子E1に立上時間短縮用の抵抗R1とコ
ンデンサC1の並列回路よりなる加速回路を接続
し、該加速回路の他端子D1に半導体発光素子LD1
を接続して来た。本回路の動作を第2図の各部の
波形を参照して説明する。
Conventionally, in order to operate the semiconductor light emitting device at high speed, as shown in FIG. 1 , an acceleration circuit consisting of a parallel circuit of a resistor R 1 and a capacitor C 1 for shortening the rise time is connected to the emitter terminal E 1 of a transistor Q 1 . and connect the semiconductor light emitting device LD 1 to the other terminal D 1 of the acceleration circuit.
I connected it. The operation of this circuit will be explained with reference to waveforms at various parts in FIG.

トランジスタQ1のベース端子B1へ正パルスPI
が印加されると、トランジスタQ1がオンし電流
I1が流れ始める。コンデンサC1により短時間、過
渡電流21が流れる。一般に、半導体発光素子は
印加電流の増大に伴なつて、その立上時間が速く
なる特性がある。従つて、この過渡電流21は、
光パルス波形OPの前縁24を高速化させる。パ
ルス電流I1は加速回路の抵抗R1とコンデンサC1
時定数で減少しR1で制限される定常電流値22
に落着き、コンデンサC1及び半導体発光素子LD1
の接合コンデンサに電荷が蓄積される。入力パル
スPINがオフしても、これらのコンデンサに蓄積
された電荷は直ちに放電できず、半導体発光素子
LD1に電流23を流しつづけ、やがて、オフにな
る。光パルスOPの後縁25は、これらのコンデ
ンサの放電時間に依存し、比較的低速度となり、
次のパルスの前縁26に悪影響を及ぼす。従つ
て、伝送速度を増加させると、各パルス間で互い
に干渉し、伝送品質の劣化をきたすことになる。
Positive pulse P I to base terminal B 1 of transistor Q 1
When N is applied, transistor Q1 turns on and the current
I 1 begins to flow. A transient current 21 flows for a short time due to the capacitor C1 . Generally, a semiconductor light emitting device has a characteristic that its rise time becomes faster as the applied current increases. Therefore, this transient current 21 is
The leading edge 24 of the optical pulse waveform OP is sped up. The pulse current I 1 decreases with the time constant of the accelerator circuit resistor R 1 and capacitor C 1 , and the steady current value 22 is limited by R 1 .
I settled on a capacitor C 1 and a semiconductor light emitting device LD 1
Charge is stored in the junction capacitor of Even if the input pulse P IN is turned off, the charges accumulated in these capacitors cannot be discharged immediately, and the semiconductor light emitting device
Current 23 continues to flow through LD 1 , and eventually turns off. The trailing edge 25 of the light pulse OP will be relatively slow, depending on the discharge time of these capacitors,
The leading edge 26 of the next pulse is adversely affected. Therefore, if the transmission speed is increased, the pulses will interfere with each other, resulting in deterioration of transmission quality.

本発明の目的は、蓄積された電荷を高速度で除
去する回路を付加することにより、上記欠点を解
決し、高速度で且つ伝送品質のよい光パルスを発
生できる半導体発光素子駆動回路を提供すること
にある。
An object of the present invention is to solve the above-mentioned drawbacks by adding a circuit that removes accumulated charges at high speed, and to provide a semiconductor light emitting device driving circuit that can generate optical pulses at high speed and with good transmission quality. There is a particular thing.

本発明によれば、NPNトランジスタのエミツ
タ端子とPNPトランジスタのエミツタ端子を接続
し、該接続点にコンデンサと抵抗よりなる並列回
路の一端を接続し、該並列回路の他端を半導体発
光素子に接続したことを特徴とする半導体発光素
子駆動回路が得られる。
According to the present invention, the emitter terminal of an NPN transistor and the emitter terminal of a PNP transistor are connected, one end of a parallel circuit consisting of a capacitor and a resistor is connected to the connection point, and the other end of the parallel circuit is connected to a semiconductor light emitting element. A semiconductor light emitting device driving circuit is obtained.

次に本発明について図面を参照して詳細に説明
する。
Next, the present invention will be explained in detail with reference to the drawings.

第3図は、本発明の第1の実施例を示す回路図
であり、第4図は、その各部波形である。NPN
トランジスタQ2のエミツタ端子とPNPトランジ
スタQ3のエミツタ端子を接続し、該接続点E2
コンデンサC1と抵抗R1の並列回路からなる加速
回路の一端を接続し、該加速回路の他端D2は半
導体発光素子LD1のアノード電極に接続され、一
方、カソード電極は接地されている。
FIG. 3 is a circuit diagram showing the first embodiment of the present invention, and FIG. 4 shows waveforms of various parts thereof. NPN
Connect the emitter terminal of the transistor Q 2 and the emitter terminal of the PNP transistor Q 3 , connect one end of an acceleration circuit consisting of a parallel circuit of a capacitor C 1 and a resistor R 1 to the connection point E 2 , and connect the other end of the acceleration circuit. D2 is connected to the anode electrode of the semiconductor light emitting device LD1 , while the cathode electrode is grounded.

トランジスタQ2、Q3のベース端子B2は共通接
続され、駆動パルスPINの入力端子となる。
The base terminals B 2 of the transistors Q 2 and Q 3 are commonly connected and serve as input terminals for the drive pulse P IN .

各トランジスタQ2とQ3のコレクタは適当な正
電源V1と負電源―V2でバイアスされている。
The collectors of each transistor Q 2 and Q 3 are biased with a suitable positive supply V 1 and negative supply −V 2 .

正の電位の駆動パルスPINがベース端子B2
印加されると、NPNトランジスタQ2のベース・
エミツタ間は順バイアスされ、オンになる。
When a positive potential drive pulse P IN is applied to the base terminal B 2 , the base terminal of the NPN transistor Q 2
The emitter is forward biased and turned on.

一方、PNPトランジスタQ3のベース・エミツ
タ間は逆バイアスされオフとなる。その結果、正
電源V1より電流IONが流れ、コンデンサC1を通
して、過渡電流41が半導体発光素子LD1に流
れ、高速な前縁43をもつ光パルスOPが発生す
る。
On the other hand, the base and emitter of PNP transistor Q3 is reverse biased and turned off. As a result, a current I ON flows from the positive power source V 1 , a transient current 41 flows to the semiconductor light emitting device LD 1 through the capacitor C 1 , and an optical pulse OP with a high-speed leading edge 43 is generated.

次に、電流IONは、従来の駆動回路の項で説明
したように、加速回路の抵抗R1とコンデンサC1
の時定数で定常値40に達し、且つコンデンサ
C1と半導体発光素子の接合コンデンサには電荷
が蓄積される。従つて、E2の電位は正電位が保
たれる。
Next, the current I ON is determined by the resistance R 1 of the accelerator circuit and the capacitor C 1 as explained in the conventional drive circuit section.
It reaches a steady value of 40 with a time constant of , and the capacitor
Charge is accumulated in the junction capacitor between C1 and the semiconductor light emitting device. Therefore, the potential of E 2 is maintained at a positive potential.

次に、入力パルスPINがオフし、ベース端子
B2が接地電位となるとNPNトランジスタQ2はオ
フとなる。一方、PNPトランジスタQ3はそのエ
ミツタ端子E2が正電位のため、順方向バイアス
となる。従つて、電流IOFFがコンデンサC1およ
び半導体発光素子LD1の接合コンデンサに蓄積さ
れている電荷を除去する方向に過渡的に流れる。
エミツタ端子E2の電位は急速に降下し、PNPト
ランジスタQ3を順バイアス出来なくなるまで、
過渡電流42を流しつづける。したがつて、蓄積
電荷を高速度で除去できるため、光パルスOPの
後縁44を高速化可能となる。
Next, the input pulse P IN is turned off and the base terminal
When B 2 becomes ground potential, NPN transistor Q 2 is turned off. On the other hand, since the emitter terminal E2 of the PNP transistor Q3 has a positive potential, it becomes forward biased. Therefore, the current I OFF flows transiently in the direction of removing the charges accumulated in the capacitor C 1 and the junction capacitor of the semiconductor light emitting device LD 1 .
The potential at the emitter terminal E2 drops rapidly until it is no longer possible to forward bias the PNP transistor Q3 .
The transient current 42 continues to flow. Therefore, since the accumulated charge can be removed at high speed, it is possible to speed up the trailing edge 44 of the optical pulse OP.

第5図は、本発明の第2の実施例を示す回路図
である。
FIG. 5 is a circuit diagram showing a second embodiment of the present invention.

更に、高速化を計るため、NPNトランジスタ
Q2とPNPトランジスタQ3を能動領域で動作させ
るためのバイアス回路を該トランジスタのベース
側に付加したもので、その他の部分は第1の実施
例と全く同じである。ダイオードD1とD2によ
り、NPNトランジスタQ2とPNPトランジスタQ3
は順方向にバイアスされ、入力パルスがオフの状
態でも能動領域にバイアスされ、高速動作が計ら
れている。
Furthermore, in order to increase the speed, NPN transistor
A bias circuit for operating Q 2 and the PNP transistor Q 3 in the active region is added to the base side of the transistors, and the other parts are exactly the same as the first embodiment. Diodes D 1 and D 2 allow NPN transistor Q 2 and PNP transistor Q 3
is forward biased and biased in the active region even when the input pulse is off, ensuring high-speed operation.

以上、説明したように、本発明によつてNPN
トランジスタとPNPトランジスタのエミツタを共
通接続し、該接続点に抵抗とコンデンサの並列回
路よりなる加速回路を接続し、一方のトランジス
タは半導体発光素子に発光電流を供給し、高速な
前縁をもつ光パルスを発生させしめ、他のトラン
ジスタは加速回路のコンデンサおよび半導体発光
素子の接合コンデンサに蓄積された電荷を高速に
除去し、光パルスの後縁を高速化可能とし、高速
な半導体光素子駆動回路を提供することができ
る。
As explained above, the present invention provides NPN
The emitters of the transistor and the PNP transistor are commonly connected, and an acceleration circuit consisting of a parallel circuit of a resistor and a capacitor is connected to the connection point, and one transistor supplies a light emitting current to a semiconductor light emitting device, and a light source with a high-speed leading edge is connected to the emitter of the transistor and the PNP transistor. The other transistor quickly removes the charge accumulated in the accelerator circuit capacitor and the junction capacitor of the semiconductor light emitting device, making it possible to speed up the trailing edge of the optical pulse, thereby creating a high-speed semiconductor optical device drive circuit. can be provided.

尚、上記の説明での入力パルスの極性、各トラ
ンジスタの極性、及び半導体発光素子の極性を反
転して構成した場合等、本発明の要旨を逸脱しな
い範囲で種々の変形や適用が可能であることは言
う迄もない。
Note that various modifications and applications are possible without departing from the gist of the present invention, such as when the polarity of the input pulse, the polarity of each transistor, and the polarity of the semiconductor light emitting element in the above explanation are reversed. Needless to say.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、従来の半導体光素子駆動回路図、第
2図は従来の半導体光素子駆動回路の各部波形
図、第3図は本発明の第1の実施例を示す回路
図、第4図は本発明の駆動回路の各部波形図、第
5図は本発明の第2の実施例を示す回路図であ
る。 PIN:入力パルス、I:電流パルス、OP:光
パルス、R:抵抗、C:コンデンサ、Q:トラン
ジスタ、LD1:半導体光発光素子。
FIG. 1 is a conventional semiconductor optical device drive circuit diagram, FIG. 2 is a waveform diagram of each part of the conventional semiconductor optical device drive circuit, FIG. 3 is a circuit diagram showing the first embodiment of the present invention, and FIG. 4 5 is a waveform diagram of each part of the drive circuit of the present invention, and FIG. 5 is a circuit diagram showing a second embodiment of the present invention. P IN : input pulse, I: current pulse, OP: optical pulse, R: resistor, C: capacitor, Q: transistor, LD 1 : semiconductor light emitting device.

Claims (1)

【特許請求の範囲】[Claims] 1 NPNトランジスタのエミツタ端子とPNPト
ランジスタのエミツタ端子を接続し、該接続点に
コンデンサと抵抗よりなる並列回路の一端を接続
し、該並列回路の他端を半導体発光素子に接続し
たことを特徴とする半導体発光素子駆動回路。
1 The emitter terminal of the NPN transistor and the emitter terminal of the PNP transistor are connected, one end of a parallel circuit consisting of a capacitor and a resistor is connected to the connection point, and the other end of the parallel circuit is connected to a semiconductor light emitting element. Semiconductor light emitting device drive circuit.
JP11552580A 1980-08-22 1980-08-22 Driving circuit of semiconductor light emitting element Granted JPS5739593A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11552580A JPS5739593A (en) 1980-08-22 1980-08-22 Driving circuit of semiconductor light emitting element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11552580A JPS5739593A (en) 1980-08-22 1980-08-22 Driving circuit of semiconductor light emitting element

Publications (2)

Publication Number Publication Date
JPS5739593A JPS5739593A (en) 1982-03-04
JPS6152997B2 true JPS6152997B2 (en) 1986-11-15

Family

ID=14664678

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11552580A Granted JPS5739593A (en) 1980-08-22 1980-08-22 Driving circuit of semiconductor light emitting element

Country Status (1)

Country Link
JP (1) JPS5739593A (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58137340A (en) * 1982-02-09 1983-08-15 Matsushita Electric Ind Co Ltd Light emitting diode driving circuit
JPS5928396A (en) * 1982-08-10 1984-02-15 Nec Corp Semiconductor laser drive device
FR2537782A1 (en) * 1982-12-14 1984-06-15 Thomson Csf LIGHT-EMITTING DIODE DEVICE PROVIDED TO REMOVE THE EFFECTS OF CONSTANT THERMAL TIME
JPS61230438A (en) * 1985-04-03 1986-10-14 Mitsubishi Electric Corp Optical transmitter
JPS62122286A (en) * 1985-11-22 1987-06-03 Stanley Electric Co Ltd Led driving circuit
JP4277610B2 (en) * 2003-07-23 2009-06-10 豊田合成株式会社 Light emitting device
JP5509662B2 (en) * 2009-04-13 2014-06-04 ソニー株式会社 Laser drive device
JP6410522B2 (en) * 2014-08-22 2018-10-24 株式会社トプコン Light emitting device
WO2016175301A1 (en) * 2015-04-30 2016-11-03 株式会社トプコン Light-emitting device and distance measurement device
JP6972575B2 (en) * 2016-08-19 2021-11-24 富士通株式会社 Frequency characteristic adjustment circuit, optical transmission module using this, and optical transceiver
JP6852302B2 (en) * 2016-08-19 2021-03-31 富士通株式会社 Frequency characteristic adjustment circuit, optical transmitter using this, and optical transceiver
JP6904291B2 (en) * 2018-03-20 2021-07-14 日本電信電話株式会社 DML driver

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4813062B1 (en) * 1968-09-03 1973-04-25

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4813062U (en) * 1971-06-24 1973-02-14

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4813062B1 (en) * 1968-09-03 1973-04-25

Also Published As

Publication number Publication date
JPS5739593A (en) 1982-03-04

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