JPS6149695B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing apparatus, and particularly to an information processing apparatus employing a proactive control method.

In an information processing system, an input/output operation by an input/output device and an instruction execution operation by an information processing device are processed in parallel, and when the input/output operation is completed, the input/output device notifies the information processing device as an external interrupt. is taken. The information processing device receives an external interrupt signal at the break between instructions, reads information in the main memory that is predetermined according to the device that sent the interrupt request signal and the type of interrupt, and processes the information. Interrupt processing is performed according to the information. In this case, in an information processing device that performs advanced advance control processing or pipeline processing, the execution unit detects interrupt reception at the timing of a break in instruction execution, and the advance control unit reads the instruction.
Interrupt processing is performed after canceling all instructions in processing stages such as address calculation and operand fetch. That is, when an execution unit detects an interrupt, the processing operation of a subsequent instruction that has been partially prepared for execution is canceled, resulting in waste.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an information processing apparatus that includes a preceding control unit and is capable of performing interrupt processing without canceling an instruction that is currently being processed.

According to the present invention, there is provided a device which inputs external interrupt request signals from a plurality of devices and processes information by a preemptive control method in conjunction with a main storage device, wherein the plurality of input external interrupt requests a code corresponding to an external interrupt request signal with the highest priority selected from the signals; a pseudo-instruction including an address indicating the location of information on the main memory device required for interrupt processing;
and an external interrupt processing unit that generates a generation indication signal indicating that this pseudo-instruction is being generated, and when the next instruction is taken into the instruction register to decode the instruction, the generation indication signal is in a set state. an instruction prefetching means for receiving the pseudo-instruction when the pseudo-instruction is in the set state and receiving the next instruction when the generation indication signal is not in the set state; and the main memory indicated by the address information in the pseudo-instruction when the pseudo-instruction is decoded. an advance control unit comprising operand prefetching means for reading information from the device; and an execution unit that performs interrupt processing by inputting the pseudo-instruction given from the advance control unit and the information read from the main storage device. An information processing device equipped with the above-mentioned information processing apparatus can be obtained.

Next, a detailed description will be given with reference to the drawings.

FIG. 1 is a diagram showing the program status word (hereinafter referred to as PSW) used in interrupt processing of an information processing device. It is a diagram showing the program status word (hereinafter referred to as PSW) used in interrupt processing of an information processing device. It includes information such as accompanying condition code information and an instruction counter value indicating the location in main memory of the next instruction to be executed. The hardware that implements this in an information processing device is called a PSW register.

Figure 2 shows the arrangement of each area in main memory in one well-known method of interrupt processing, as shown in Figure 1.
FIG. 3 is a diagram showing the relationship with the PSW register. In this Figure 2. The contents of the PSW register of the interrupted program are saved to an area in main memory (hereinafter referred to as the old PSW area) that is predetermined by the type of interrupt and the interrupt requesting device (operation). , the PSW of the program that processes the interrupt is read from an area in the main memory that has been determined in advance (hereinafter referred to as the new PSW area).
Set the PSW register (behavior of) and set the new PSW
Resumes instruction execution according to the instructions.

FIG. 3 shows a time chart of the conventional interrupt processing example described above. When an interrupt request is generated and accepted at time _T5 , the instructions B, C, D, All E is canceled and the new PSW for the interrupt processing program is set to time.
It can be seen that it is sent to the execution unit at _T9 . In this way, several previously prepared orders were canceled, resulting in losses.

FIG. 4 shows an example of a format diagram of instructions used in the information processing apparatus of the present invention. The device instructions in this case are register-register type instructions (hereinafter referred to as RR type instructions) whose lower 16 bits are zero, and register-memory type instructions (hereinafter referred to as RR type instructions).
There are two types of instructions (referred to as RM type instructions), and the distinction between the two is made by the instruction code, both of which consist of 32 bits. (1) and (2) in the figure are RR type and RM type
Each represents a type command. (3) in the figure represents an RM type pseudo-instruction, which can be said to be a feature of the present invention, and is also made up of 32 bits.

FIG. 5 is a diagram showing the configuration of an embodiment of the present invention using instructions in the format shown in FIG. The explanation will be given below using both Figures 4 and 5, but first, Figure 5 will be explained.
The names of the parts that roughly divide the configuration in the figure are as follows: 1 is the external interrupt processing unit, 2 is the instruction preemption means, 3 is the operand preemption means, and 4 is the combination of 2 and 3.
5 represents a preemption control unit, 5 represents an execution unit, and 6 represents a cache (not shown) which is considered to be part of the main memory. In addition, there are a plurality of devices (not shown) that generate external interrupt request signals.

First, apart from the circuit configuration, we will functionally explain how the arithmetic register 11 of the execution unit 5 shown in FIG. 5 is processed by the arithmetic circuit 12 in relation to the instructions shown in FIG. 4. The execution unit 5 has a 16-word arithmetic register, each word consisting of 32 bits, and in the RR type instruction shown in Figure 4 (1), the contents of the arithmetic register specified by the instruction _R1 and the operation specified by _R2 are Performs an operation using the contents of the register as an operand, and stores the result in the operation register specified by _R1 . On the other hand, in the RM type instruction shown in FIG. 4(2), the value obtained by adding the contents of the arithmetic register specified by _R2 and the _D2 part of the instruction is treated as the address of the operand in the main memory. At this time, if R ₂ is zero, the D ₂ part itself is treated as an operand address in main memory. In other words, most RM-type instructions operate on the contents of the arithmetic register specified by _R1 and the operand in main memory specified by the address created in _R2 and _D2 , and then calculate the result. is stored in the calculation register specified by _R1 . The instruction to store the contents of the arithmetic register in the main memory (not shown) is still
In the RM type, the contents of the arithmetic register specified by R ₁ are
The value obtained by adding the _D2 part to the contents of the calculation register specified by _R2 is stored in the main memory at the address.

Next, the details of the configuration and operation of the apparatus will be explained with reference to FIG. The external interrupt processing unit 1 receives as input a plurality of external interrupt request signals and an interrupt mask sent from the execution unit 4 via the signal line a. External interrupt request signals are only considered valid when the corresponding interrupt mask bit is set. Among the external interrupt request signals considered to be valid, the one with the highest priority is selected, and an address in the main memory storing a new PSW corresponding to the selected interrupt request signal is generated. Then, create an interrupt code that corresponds to the type of interrupt, such as a communication interrupt between central processing units, an input/output end interrupt, an interrupt for an abnormality in another device, or a type of timekeeping device interrupt, and then write it as an instruction code. generates a code representing an external interrupt.

That is, when there is a valid external interrupt, external interrupt processing unit 1 creates an interrupt code corresponding to the type of interrupt, inserts it into the _R1 part of the instruction, and writes it to the unit number of the external device that caused the interrupt. An RM type pseudo-instruction is generated in which the corresponding D ₂ is created, R ₂ is set to zero, and the instruction code part is set to all "1". This is the command shown in FIG. 4(3). This generated pseudo-instruction is connected to the instruction selection circuit 11 via the signal line b. At the same time, an indication that a pseudo-instruction has been generated is sent to the instruction selection circuit 11 via the signal line c.

The cache 6 is a buffer storage device that reads out part of the information in the main memory in units of blocks, holds frequently used information, and performs read and write operations at high speed. Similarly to accessing the main memory, the memory access register 12 is connected by a signal line d so that the contents of the register 12 serve as an address.

The command buffer 13 is connected to the signal line e from the cache 6.
Holds instructions read out in parallel through 8 words. The output of the instruction buffer 13 is selected one instruction at a time and supplied to the instruction selection circuit 11 via the signal line f.

The instruction selection circuit 11 uses the output line f of the instruction buffer 13 and the output line b of the external interrupt processing unit 1 as inputs for instruction information, and when the signal line c represents a generation display signal indicating generation of a pseudo-instruction, The content of signal line b is selected for output line g, and when the generated display signal is not appearing, signal line f is selected. The selected instructions are stored one by one in the instruction register 14.
and is further sent to the instruction decoder 15 via the signal line h.
is supplied to

The instruction decoder 15 decodes the instructions held in the instruction register 14. That is, it decodes whether the instruction is RR type or RM type, and if it is RM type, it instructs the next address register 16 to perform address calculation via signal line i. Also
If the instruction is of the RM type, it is determined whether it is a normal instruction or a pseudo instruction generated by the external interrupt processing unit 1. If it is a pseudo-instruction, that is, Fig. 4
As shown in (3), if the instruction code part is all 1, in addition to normal RM type instruction operation, the instruction register 14 can be emptied and new instructions can be received in the instruction register 14 until a restart command is issued. It goes into a ``waiting state'' to prevent it from happening.

Address register 16 receives an instruction supplied via signal line i from instruction decoder 15 when a new instruction becomes available.
At this time, if address calculation is instructed by the instruction decoder 15, access is made via the signal line j in order to select the arithmetic register corresponding to the _R2 portion of the received instruction from among the arithmetic registers 9. The arithmetic register read out by the arithmetic register 2 is input to the address calculation circuit 17 via the signal line k.

On the other hand, the information in the _D2 portion of the address register 16 is supplied to the address calculation circuit 17 via the signal line l. Address calculation circuit 17 is address register 1
If the _R2 part of the instruction in step 6 is not zero, input signal line l and signal line k are added and output to signal line m, and _R2
When the part is zero, the contents of the signal line l are output as they are to the signal line m.

Returning to the address register 16, when the instruction code section, _R1 section, and _R2 section of this register are in a state where the instruction execution waiting register 18 receives a new instruction, the instruction execution waiting register 18 is transferred to the address register 16 via the signal line m. sent to. At the same time, if the instruction held in the address register 16 is of RM type,
The contents of signal line m are sent to memory access register 12. And if instruction execution wait register 18
If the instruction sent to the memory access register 12 is an RM type instruction other than a store instruction, the cache 6 is
Issue a read request to. If the instruction sent to the instruction execution wait register 18 is an RM-type storage instruction or a pseudo-instruction for external interrupt processing, the memory access register 12 will not be updated even after these instructions are sent to the execution unit 5. Since the contents of are used, the instruction execution wait register 18 and memory access register 12 receive the next instruction from the address register 16 and address calculation circuit 17 until the execution of these instructions is completed or the contents of the memory access register 12 are used. to postpone.

By the way, the memory access register 12 has a function of incrementing the word address information by one address using the adder 19 and returning it to itself. A pseudo-instruction for external interrupt processing is transferred from the instruction execution wait register 18 to the execution instruction register 21 via the signal line o, and the cache 6 is read out by the memory access register 12, and then transferred to the operand register via the signal line p. 22, the contents of the memory access register 12 increase by one address. In other words, in the case of a pseudo-instruction for external interrupt processing, the address on the main memory created by the address calculation circuit 17 is
As shown in the figure, it shows the new PSW area for the program that handles the interrupt, and the address that is one address higher than that address is the area for the currently running program that will be interrupted by the interrupt.
An area of the old PSW to save the contents of the PSW register is defined.

The instruction set in the instruction execution wait register 18 is
In the case of RR type and RM type storage instructions, when the execution instruction register 21 becomes able to accept the next instruction, that is, when the execution unit 5 becomes able to accept the next instruction, the execution instruction is sent via the signal line o. An instruction is received in the register 21 and execution of the instruction is started. If the instruction set in the instruction execution wait register 18 is an RM type instruction other than a store instruction, the execution instruction register 21 becomes ready to accept the next instruction, and the output line p of the cache 6 has an operand in the main memory. When read, the execution instruction register 21
and is transferred to the operand register 22, and execution of that instruction begins.

Of the two cases above, the former case where the instruction set in the instruction execution waiting register 18 is of the RR type will be explained.
The R ₁ portion of is sent to the arithmetic register 9 via the signal line q, one word of data out of the 16 words is accessed, its contents are read out to the signal line r, and sent to the first selection circuit 23 . The _R2 part of the execution instruction register 21 is sent to the calculation register 9 via the signal line s, one word of data from among the 16 words is accessed, and the contents are sent to the signal line t.
is read out and sent to the second selection circuit 24.

The first and second selection circuits 23 and 24 decode the instruction code part of the execution instruction register 21, and the former first selection circuit 23 selects the signal line r, and the latter second selection circuit 24 selects the signal line r. Line t is selected and output to signal lines u and v, respectively. The arithmetic circuit 10 has various arithmetic functions, performs arithmetic operations on two inputs as operands according to the contents of the instruction code portion of the normal execution instruction register 21, and outputs the results to the signal line w. The obtained calculation result is stored in the calculation register 9 designated by the R1 _section . Although not shown, the output of the arithmetic circuit 12 sets a state in the condition code section of the PSW register 25 depending on whether the result is zero, positive, negative, etc. The instruction counter portion of the PSW register 25 is incremented by 1 by the adder 26 every time an instruction is executed.

Next, to explain the latter case where the instruction set in the instruction execution wait register 20 is RM, when it is a store instruction or pseudo-instruction, as described later,
Although this is different from the case of the RR type, the other cases are the same as the case of the RR type described above except that the second selection circuit 24 selects the output of the operand register 22, that is, the signal line x, and its output line. .

If the instruction is a store instruction, one word of the arithmetic register 9 selected by the _R1 section is output to the signal line r, and is supplied to the arithmetic circuit 10 via the first selection circuit 23. The arithmetic circuit 10 supplies the same information as the signal line u to the output signal line w regardless of the state of the signal line v from the second selection circuit 24. This information is connected to the cache 6 and becomes write data to the cache and main memory. At this time, the address of the store instruction is held in the memory address register 12, and the execution unit 5 issues a write instruction to the cache 6 and the main storage device at the same timing, and ends the execution of the instruction.

If the instruction is a pseudo-instruction for external interrupt processing, R1 of the execution instruction register ₂₁ indicating the type of interrupt.
The information of the section is sent to PSW register 2 via signal line q.
It is transferred to the interrupt code section of No.5. Then, PSW
The contents of the register 25 are supplied to the first selector 23 through the signal line y. This information is written to the old PSW area corresponding to the interrupt on the main memory in the same manner as a store instruction.

After that, the new PSW information read to the operand register 22 is transferred to the signal line x, and the second selection circuit 2
4. Via the signal line v, the arithmetic circuit 10, and the signal line w,
Set in PSW register 25. The interrupt mask bit of this PSW register is supplied to the external interrupt processing unit 1 via signal line a. Also, the information in the newly set instruction counter section of the PSW register 25 is transferred to the memory access register 12 via the signal line z, the first eight words of the interrupt processing program are read, and the instruction buffer is transferred via the signal line e. 1
Transfer to 3.

When the above processing is completed, execution unit 1
The "wait state" of the instruction register 14 is released, the advance control operation is restarted, and its own operation is completed.

As can be seen from the functions of each circuit in the above description, the instruction selection circuit, instruction buffer 13, instruction register 14, and instruction decoder together form instruction prefetching means, and the memory access register 1
2, address register 16, address calculation circuit 1
7. The instruction execution waiting register and the adder 19 form combined operand prefetching means, and both prefetching means can be collectively called prefetching control means.

FIG. 6 is a time chart showing an example of interrupt processing in the embodiment of FIG. As shown in this figure, in this example, the interrupt request is
Even if it occurs at T ₅ , instructions B, C, and D are still being preempted.
is executed as is without being canceled,
The new PSW is sent to the execution unit at time _T9 when instructions B, C, and D are executed in one clock.

As explained above, the present invention is configured such that an external interrupt processing unit generates a pseudo-instruction and supplies it to an instruction register for prefetching. By executing the instructions without being canceled, efficient interrupt processing can be provided.

[Brief explanation of the drawing]

Figure 1 shows the structure of a program status word (PSW) used in interrupt processing of an information processing device, and Figure 2 shows the arrangement of each area in main memory in the interrupt processing method. Figure 3 shows the relationship with the PSW register, Figure 3 shows a time chart of conventional interrupt processing, and Figure 4 shows an example of the format of instructions used in the information processing device of the present invention. 5 is a diagram showing the configuration of an embodiment of the present invention using instructions of the type shown in FIG. 4, and FIG. 6 is a time chart showing an example of interrupt processing in the embodiment of FIG. 5. It is. Explanation of symbols: 1 is an external interrupt processing unit, 2 is an instruction prefetching means, 3 is an operand prefetching means, 4 is a preemptive control unit, 5 is an execution unit, 6 is a cache, 9 is an arithmetic register, 10 is an arithmetic circuit, 11
12 is an instruction selection circuit, 12 is a memory access register, 13 is an instruction buffer, 14 is an instruction register,
15 is an instruction decoder, 16 is an address register,
17 is an address calculation circuit, 18 is an instruction execution wait register, 21 is an execution instruction register, 22 is an operand register, 23 is a first selection circuit, and 24 is a second
The selection circuit 25 represents a PSW register.

Claims (1)

[Claims] 1 A device that inputs external interrupt request signals from a plurality of devices and processes information in conjunction with a main storage device using a preemptive control method, the device receiving priority signals selected from the plurality of input external interrupt request signals. A code corresponding to the highest-ranked external interrupt request signal, a pseudo-instruction including an address indicating the location of information on the main storage device required for interrupt processing, and this pseudo-instruction being generated. an external interrupt processing unit that generates a generation indication signal indicating the generation indication signal; instruction preemption means for receiving said next instruction when the signal is not in the set state, and when said pseudo-instruction is decoded;
a preceding control unit comprising operand prefetching means for reading out information from the main memory indicated by address information in this pseudo-instruction; An information processing device comprising an execution unit that receives information as input and performs interrupt processing.