JPS6134186B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an instruction control system that allows a later instruction to be executed before an earlier instruction in a data processing device, such as a vector processing device. Second operand A with multiple elements
(a ₀ , a ₁ , ...a _o-1 ) and multiple elements B
(b ₀ , b ₁ , ...b _o-1 ) on the corresponding elements, and the first operand of the result C (c ⁰ ,
c ¹ , . . . c _o-1 ) is called a vector processing device. On the other hand, a conventional general-purpose processing device in which the number of elements is limited to one (n=1) is called a scalar processing device. FIG. 1 shows an overview of a vector processing device, in which 1 is a main memory, 2 is a main memory control device,
3 is a vector processing device, 4 is a store processing section, 5 is a load processing section, 6 is a vector register, 7 is a multiplier, 8 is an adder, and 9 is an instruction control section. Note that solid line arrows indicate the flow of data, and dotted line arrows indicate the flow of control signals.
The store control unit 4 is for storing data in the vector register in the main memory 1, and the load processing unit 5 is for reading data from the main memory 1 and storing it in the vector register 6. It is. The vector register 6 has a plurality of vector registers that hold vector data consisting of a plurality of elements. The store processing section 4, the load processing section 5, the multiplier 7, and the adder 8 have a pipeline structure. Command control unit 9
controls the vector register 6, store processing unit 4, load processing unit 5, multiplier 7, adder 8, etc. The present invention relates to this instruction control section. In the present invention, the store processing section 4, load processing section 5, multiplier 7, and adder 8 are collectively referred to as an arithmetic processing section. A vector instruction has an instruction code, a first operand designation, a second operand designation, and a third operand designation part. Vector multiplication instructions are represented by VM1,2,3. This multiplies the contents of vector register 2 and vector register 3 and places the result in vector register 1. A vector addition instruction is represented by VA4,5,1, for example. This adds the contents of vector register 5 and vector register 1 and places the result in vector register 1. When processing a vector instruction, the multiplier 7, adder 8, etc. are arranged in a pipeline structure, and the subsequent element is input before the arithmetic processing of the preceding element is completed. Figure 2 shows the processing status of the vector addition instruction in the adder 8. (1) Read data (READ) (2) Compare the exponents of both operands (COMPARE) (3) Shift for exponent matching (PRE−
SHIFT) (4) Addition (ADD) (5) Shift for normalization after operation (POST
SHIFT) (6) Data writing (WRITE) 6-stage pipeline. Instruction processing is represented by a parallelogram as shown in FIG. Next, problems with the conventional command control method will be explained. Now, suppose we have a vector instruction sequence: VM1, 2, 3 VA 4, 5, 1 VA 7, 8, 9. The conventional processing at this time is shown in FIG. However, the vector multiplication instruction is an 11-stage pipeline,
It is assumed that the number of elements is eight. In Figure 3, VA
The reason why 4, 5, 1 starts from time = 11 is because
This is because VA4, 5, and 1 use the result data of VA1, 2, and 3. By the way, VA7, 8, 9 do not interfere with the preceding instruction and the vector register, so VA4, 5,
By executing VA7, 8, and 9 before VA1, the instruction processing time can be shortened. Fourth
The figure shows the state at this time. As is clear from FIGS. 3 and 4, the instruction processing time in FIG. 4 is nine cycles shorter than that in FIG. 3. In this way, there has never been a vector processing device that changes the order of vector instructions instructed by a program. In a scalar processing unit, each arithmetic processing unit has an operand register that holds the operands of multiple instructions. Flags for identification
There is a method of providing an operand reservation section having registers and a common bus for sending result data of each arithmetic processing section to the operand reservation section. Applying this method to a vector processing device would make the operand reservation section huge and unnecessarily increase the amount of hardware, which is not a good idea. The present invention is based on the above considerations, and includes:
The objective is to realize an instruction control method that executes later instructions before earlier instructions and reduces instruction processing time with a small amount of hardware. And for that reason,
The instruction control method of the present invention uses vector registers,
In a vector processing device having a plurality of pipeline-structured arithmetic processing units that process vector data of the vector register as operand data, an instruction register in which a vector instruction is set, a plurality of waiting registers, an input control circuit that stores vector instruction information in the instruction register in the waiting register; an execution information holding register that holds vector instruction information of a vector instruction that is currently being executed; and an input control circuit that stores the vector instruction information in the waiting register. an instruction transmission control circuit that stores the transmitted vector instruction information in a corresponding executing instruction information holding register at the same time as executing the instruction; and a comparison means that compares the vector instruction information of the waiting register with the vector instruction information of the executing instruction information holding register. and the instruction transmission control unit transmits vector instruction information for which the comparison means has determined that there is no factor preventing the start of instruction execution from among the vector instruction information in the plurality of waiting registers. This is a characteristic feature. Hereinafter, the present invention will be explained with reference to the drawings. FIG. 5 is a block diagram of the first embodiment of the instruction control unit of the present invention, FIG. 6 is a time chart when an instruction is overtaken, and FIGS. 7 and 8 are one embodiment of a register interference check circuit. FIG. In FIG. 5, 10 is a fetch register;
11 is a waiting register input control circuit, 12-1 and 1
2-2 is a waiting register, 13-1 and 13-2 are register interference check circuits, 14 is a selector, 15
is an instruction transmission control circuit, 16 is a multiplication register, 17
18 shows an addition register, 18-1 and 18-2 a register interference check circuit, and 19 a selection control circuit, respectively. Fetch register 10 is set with instruction information fetched from main memory 1. The waiting register input control circuit 11 transfers the instruction information of the fetch register 10 to the waiting register 12-1 or 12-2 on the condition that the register interference check circuits 13-1 and 13-2 indicate that there is no register interference. Move to. Register interference check circuit 1
Details of 3-1 and 13-2 will be described later. The selector 14 selects the waiting register 12-1 or 12-2 according to a control signal from the selection control circuit 19. The selection control circuit 19 inverts the value of the control signal every cycle. When the output of the selector 14 is a vector addition instruction, the instruction transmission control circuit 15 transfers it to the addition register 17, provided that both register interference check circuits 18-1 and 18-2 indicate no register interference. , selector 1
If the output of step 4 is a vector multiplication instruction, it is transferred to the multiplication register 16, and at the same time, arithmetic processing unit activation information is sent out. Details of the register interference check circuits 18-1 and 18-2 will be described later. FIG. 6 is a time chart when instructions are overtaken. The instruction information VM1, 2, 3 is set in the fetch register 10 at time T=0, transferred to the waiting register 12-1 at T=1, transferred to the multiplication register 16 at T=2, and then multiplied. Begins. The pre-WRITE flag is turned on at the same time as multiplication starts. This flag is a vector
When writing of the operation result to the register starts,
It will be turned off. The command information VA4,5,1 is T
= 1, it is set in fetch register 10, and T
=2, it is set in the waiting register 12-2. VM1, 2, 3 held in multiplication register 16
1st operand register and waiting register 12
Since there is register interference with the first vector registers of VA4, 5, and 1 held at VA-2, the transmission of the command from the waiting register 12-2 is delayed. At T=2, VA7, 8, and 9 are set in fetch register 10. Waiting register 12-2
Since there is no register interference between VA4, 5, 1 held in the fetch register 10 and VA7, 8, 9 held in the fetch register 10, VA
7, 8, and 9 are moved to the waiting register 12-1, and since there is no factor that prevents the command from being issued, VA is set at T=4.
7, 8, and 9 are transferred to the addition register 17, and the adder 8 is started to process. FIG. 7 shows one embodiment of the register interference check circuit 18-1. Note that the register interference check circuits 18-1 and 18-2 have the same configuration. In FIG. 7, 20 and 21 are matching circuits, 2
2 and 23 are AND circuits, and 24 is an OR circuit, respectively. The matching circuit 20 receives the first operand register number of the instruction being processed and the second operand register number of the processing instruction, and the matching circuit 21 receives the first operand register number of the instruction currently processing and the processing instruction. The third operand register number is input. The AND circuit 22 includes a pre-start flag for the instruction WRITE during arithmetic processing and a match circuit 20.
The AND circuit 23 receives the arithmetic processing instruction WRITE pre-start flag and the output of the coincidence circuit 21 . The output of AND circuits 22 and 23 is
It is input to the OR circuit 24. When the output of the OR circuit 24 is logic "1", it indicates that there is register interference. FIG. 8 shows one embodiment of the register interference check circuit 13-1. In Figure 8, 2
5 to 27 indicate matching circuits, and 28 indicates an OR circuit, respectively. The first operand register number of the instruction register 10 is input to one input terminal of the matching circuits 25, 26, and 27, and the first operand register number of the waiting register is input to the other input terminal of the matching circuit 25. , the second operand register number of the waiting register is input to the other input terminal of the matching circuit 26, and the third operand register number of the waiting register is input to the other input terminal of the matching circuit 27. Matching circuit 2
The outputs of 5, 26, and 27 are input to an OR circuit 28. When the output of the OR circuit 28 is logic "1", it indicates that there is register interference. FIG. 9 is a block diagram of a second embodiment of the present invention, FIG. 10 is a flowchart showing the logic of the priority setting circuit, and FIG. 11 is a block diagram of one embodiment of the register interference check circuit. In FIG. 9, 110 is an instruction fetch register, 111 is a waiting register input control circuit, and 11
2-1 and 112-2 are waiting registers, 113 is a register interference check circuit, 114 is a selector, 1
15 is an instruction transmission control circuit, 116 is a multiplication register, 117 is an addition register, 118-1 and 118
-2 represents a register interference check circuit, 120 represents a priority setting circuit, and 121 represents a priority flip-flop. In addition, 110, 112-1,
112-2, 114, 116, 117, 118-
Those indicated by 1,118-2 are respectively 10, 12-1, 12-2, 14, 16, 17,
It is the same as that shown by 18-1 and 18-2. The second embodiment of FIG. 9 has a waiting register 112-
A priority is given to the instruction information stored in 1 and 112-2, and if there is register interference between these instruction information, the instruction with a higher priority is executed first. be. In this second embodiment, the waiting register input control circuit 111
If there is an empty waiting register 112-1 or 112, the instruction information in the fetch register 110 is moved to the empty waiting register without checking for register interference. FIG. 10 is a flowchart showing the logic of the priority setting circuit 120. Note that Q ₁ indicates the waiting register 112-1, and Q ₂ indicates the waiting register 112-1.
2 is shown. The priority order is set as follows. (b) Check whether the instruction information is set to _Q1 . If Yes, process (b); if No, process
Perform the processing in (e). (b) Check whether Q ₂ is paritud or not. No
If yes, perform process (d); if Yes, perform process (g). (c) Find out whether Q ₁ will be released or not. Release means that the Q ₁ command is sent to the command transmission control circuit 1.
15 means setting in the acquisition multiplication register 116 or addition register 117.
If No, process (d) will be performed, if Yes, process (ch) will be performed.
processing is performed. (d) Set the priority of Q ₁ higher than Q ₂ . (e) Check whether the instruction information is set to _Q2 . If No, perform the process in (i), and if Yes, perform the process in (f). (f) Check whether Q ₁ is valid or not. No
If so, perform the process in (H), and if Yes, perform the process in (C). (g) Find out whether Q ₂ will be released. If No, perform process (H); if Yes, perform process (D). (H) Set the priority of Q ₂ higher than Q ₁ . (li) Check whether the priority of Q ₁ is higher than Q ₂ . If Yes, process (d); if No, process
Perform the processing in (h). FIG. 11 is a block diagram of one embodiment of register interference check circuit 113. In FIG. 11, 122 to 126 are matching circuits, and 127 is a matching circuit.
OR circuit, 128 and 129 are AND circuit, 130 is
Each shows an OR circuit. The first operand register number of the waiting register 112-2 is input to one input terminal of the matching circuits 122, 123, 124, and the second operand register number of the waiting register 112-1 is input to the other input terminal of the matching circuit 122.
The operand register number is input, and the waiting register 112 is input to the other input terminal of the matching circuit 123.
The third operand register number -1 is input, and the first operand register number of the waiting register 112-1 is input to the other input terminal of the matching circuit 124. The first operand register number of the waiting register 112-1 is input to one input terminal of the matching circuits 125 and 126, and the matching circuit 1
25 has a waiting register 112-
The second operand register number of 2 is input;
The third operand register number of the waiting register 112-2 is input to the other input terminal of the matching circuit 126. Matching circuits 122, 123, 124,
The outputs of 125 and 126 are input to an OR circuit 127. When the negative output of the OR circuit 127 is logic "1", it indicates that there is no register interference, and when the positive output of the OR circuit 127 is logic "1", it indicates that there is register interference. AND circuit 128 detects that there is register interference, waiting register 112-1
is selected and the waiting register 112-
Logical “1” with the condition that 1 has higher priority
Output. The AND circuit 129 outputs logic "1" under the conditions that there is register interference, that the waiting register 112-2 is selected, and that the priority of the waiting register 112-2 is high. The OR circuit 130 includes the negative output of the OR circuit 127, the output of the AND circuit 128, and the output of the AND circuit 12.
The output of 9 is input. The output of the OR circuit 130 becomes a command executable state signal, and this signal is sent to the command generation control circuit 115. When the instruction generation control circuit 115 receives the instruction executable state signal of logic "1", it takes in the instruction information output from the selector 114 and performs a register interference check and the like. In the above explanation, the priority order is determined by the priority setting circuit 120 having the logic as shown in FIG.
From fetish register 110 to waiting register 11
When inputting a command to 2-1 or 112-2,
It is also possible to assign an instruction number and determine the priority order based on the number. FIG. 12 is a block diagram showing a third embodiment of the present invention, and FIG. 13 is a time chart showing its operation. In FIG. 12, 210 is a fetch register, 211 is a waiting register input control circuit, and 2
12 is a waiting register, 213-1 and 213-2 are also waiting registers, 224 is a selector, 225 is an instruction transmission control circuit, 226 is a multiplication register, 227 is an addition register, 228-1 and 228-2 are register interference check circuits. are shown respectively. Code 210, 224, 225, 226, 227, 22
8-1, 228-2 are numbered 10, 14, 15, 16, 17, 18-1, respectively.
It is almost the same as that shown by 18-2. A multiplication instruction is stored in the waiting register 212,
Addition instructions are stored in waiting registers 213-1 and 213-2. The addition instruction input to the waiting register 213-1 is transferred to the waiting register 213-2.
When the addition instruction becomes empty, the waiting register 213
-2. Waiting register input control circuit 21
1 performs a register interference check as described above and inputs instruction information to the waiting register 212 or 213-1. FIG. 13 is a time chart showing the operation of the embodiment of FIG. 12. In addition, F is the fetch register 210, AQB is the waiting register 213-1, AQ
stands for the waiting register 213-2, AR stands for the multiplication register 227, MQ stands for the waiting register 212, and MR stands for the multiplication register 226. FIG. 13 shows the case where the instruction sequence VA1, 2, 3 VA 4, 5, 1 VA 7, 8, 4 VMA, B, C VMD, E, A is executed. First, the instruction is set in fetch register F, and in the next cycle, this instruction is set in fetch register F.
It is moved to AQB, and in the next cycle it is moved to register AQ, and at T=0 it is moved to addition register AR.
The instruction in fetch register F is delayed by one cycle.
In the next cycle, it is moved to the waiting register AQB, and at T=0, it is moved to the waiting register AQ.
Then, when the instruction of is finished, the addition register is
Moved to AR. The instruction is set in the fetch register F one cycle later than the instruction in , and is set in the fetch register F in the next cycle (T=0).
It is moved to AQB, when the waiting register AQ becomes free, it is moved there, and when the instruction in is completed, it is moved to the addition register AR. The command of is 1 more than the command of
After a cycle delay, it is set in fetch register F at T=0, moved to waiting register MQ in the next cycle, and moved to multiplication register MR in the next cycle. The instruction is set in the fetch register F at T=1, and is set in the waiting register F in the next cycle.
It is moved to MQ, and when the instruction in is completed, it is moved to multiplication register MR. FIG. 14 shows the operation for executing the same instruction sequence when the waiting register AQB does not exist. In the case of FIG. 14, 55 cycles are required to execute the instruction sequence, but in the case of FIG. 13, only 39 cycles are required. In addition, in the embodiment shown in FIG. 12, the waiting register 2
If there is no instruction in both registers 13-1 and 213-2, the instruction is sent directly to the waiting register 213-2.
It is also possible to control the amount to be input at 2. As is clear from the above description, according to the present invention, it is possible to significantly shorten the instruction processing time with a small amount of hardware.

[Brief explanation of the drawing]

Figure 1 is a diagram showing an overview of a vector processing device, Figure 2 is a diagram showing the processing status of vector addition instructions in an adder, Figure 3 is a diagram showing conventional processing of vector instruction sequences, and Figure 4 is a diagram showing later development. FIG. 5 is a block diagram of the first embodiment of the present invention, and FIG. 6 is a diagram illustrating the reduction in instruction processing time when a vector instruction is executed before the preceding vector instruction. 7 and 8 are block diagrams of one embodiment of the register interference check circuit, FIG. 9 is a block diagram of the second embodiment of the present invention, and FIG. 10 shows the logic of the priority setting circuit. 11 is a block diagram of one embodiment of the register interference check circuit in the second embodiment,
FIG. 12 is a block diagram of the third embodiment of the present invention, FIG. 13 is a time chart showing its operation, and FIG.
The figure is a time chart for comparison. 10...Fetch register, 11...Waiting register input control circuit, 12-1 and 12-2...Waiting register, 13-1 and 13-2...Register interference check circuit, 14...Selector, 15...Instruction transmission control circuit, 16 ...Multiplication register, 17...Addition register,
18-1 and 18-2...Register interference check circuit, 19...Selection control circuit, 110...Fetch register, 111...Waiting register input control circuit, 1
12-1 and 112-2...waiting register, 113...
Register interference check circuit, 120...Priority setting circuit, 121...Priority flip-flop, 212...
Waiting registers, 213-1 and 213-2...Waiting registers.

Claims (1)

[Claims] 1. In a vector processing device that includes a vector register and a plurality of pipeline-structured arithmetic processing units that process vector data in the vector register as operand data, a vector instruction is an instruction register to be set, a plurality of waiting registers, an input control circuit that stores the vector instruction information of the instruction register in the waiting register, and an execution information holding register that holds the vector instruction information of the vector instruction that is currently being executed. an instruction transmission control circuit that transmits vector instruction information in the waiting register and stores the transmitted vector instruction information in a corresponding executing instruction information holding register; and a comparison means for comparing the vector instruction information in the information holding register, and the instruction transmission control section determines, by the comparison means, a factor that prevents the start of instruction execution from among the vector instruction information in the plurality of waiting registers. An instruction control method characterized by transmitting vector instruction information that is determined not to exist. 2. Comparing means for comparing vector instruction information in the instruction register and vector instruction information in the waiting register, and by the comparing means, the order of vector instructions is determined between the vector instruction information in the instruction register and the vector instruction information in the waiting register. 2. The instruction control method according to claim 1, wherein the vector instruction information in the instruction register is transferred to the waiting register by the input control circuit when it is determined that there is no need to distinguish between the instructions. 3. A selection circuit for selecting one of a plurality of waiting registers is provided, and a comparison means compares the vector instruction information of the waiting register selected by the selection circuit with the vector instruction information of the executing instruction information holding register. An instruction control system according to claim 1 or 2, characterized in that: 4. It has an order identification means for identifying the order among the waiting registers, and a comparison means for comparing vector instruction information between the waiting registers, and the comparison means prevents register interference between the waiting registers. When it is determined that there is no vector instruction, all vector instructions in the waiting register are considered to be in the instruction execution start state, and when it is determined that there is register interference between the waiting registers, the ordering identification means determines that the vector instructions have a high priority. 2. The instruction control method according to claim 1, wherein the vector instruction that has been executed is considered to be in a state where instruction execution can be started. 5 A plurality of waiting registers are divided into a plurality of groups, one vector instruction information is selected in a first-in, first-out manner within a group, and the vector instruction information before execution of the operation selected for each group and the executing instruction information holding register are combined. 2. The instruction control method according to claim 1, wherein the vector information is compared with the vector information by a comparing means.