JPS61224636A - Multiplex transmitter - Google Patents

Abstract

PURPOSE:To allow the titled transmitter to use two wires only without complicating the terminal constitution while keeping the transmission efficiency and quality of a 3-wire type transmitter by providing a power supply/code superimposing circuit superimposing an inverted voltage of an address clock code onto a power supply voltage to form a power supply/code superimposition signal, a power/code superimposing line and a data line. CONSTITUTION:The multiplex transmitter has the power supply/code line 15, the data lien 17 and the power supply/code superimposing circuit 19. The circuit 19 has an address clock generator 25 and a superimposition signal output circuit 27, superimpose an address clock signal and a power supply signal shown in figure (a) and outputs a serial signal shown in figure (b) to the line 15. Thus, a charging circuit 43 of a transmitter 21 and a receiver 23 obtains a voltage V shown in figure (c) via the lien 15. The voltage V activates a transmission circuit 45 and a reception circuit 73. On the other hand, data transmission sections 45, 73 between the transmitter and receiver receive the said voltage, use the address clock signal superimposed on the line 15 so as to attain data transmission with the equal efficiency and quality to those of a conventional 3-wire multiplex transmitter.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a multiplex transmission device that can efficiently perform high-quality multiplex transmission with a small number of transmission lines.

[Prior Art] An example of a conventional multiplex transmission device is, for example, the
There is something like the one shown in No. 13367.

This is an example of the so-called time-sharing method, and its outline is explained in Section 6.
Shown in the figure.

In the figure, 1 indicates a power supply line, 3 an address clock signal line, and 5 a data line. Reference numeral 7 denotes an address clock generator that repeatedly generates a code string called, for example, an M sequence, synchronizes it with a clock signal, and sends it out as an address clock signal 113. 9.11 indicates a transmitter and a receiver connected to the power supply line 1, address clock signal line 3, and data line 5, respectively, and transmit! 19
An input line 9a for inputting transmission information is connected to the receiver 11, and an output line 11a for operating a connected external device (not shown) according to received data is connected to the receiver 11, respectively. Note that herein, these transmitters and receivers are collectively referred to as a terminal.

In the multiplex transmission device with the above configuration, all three-bit code string patterns except L, L, and L are sequentially cycled once each on the address clock signal line 3 during one cycle.
The transmitter 9 and the corresponding receiver 11 connected to the address clock signal line 3 constantly monitor the above code string to see if a 3-bit code string pattern corresponding to the address assigned to their own device appears. Waiting for.

Then, when the code string pattern assigned to itself appears, the transmitter 9 and the corresponding receiver 11 transmit the input data from the input line 5a to the data line 5, and at the same time, the receiver 11 transmits the input data from the input line 5a to the data line 5. This data is taken in from the data line 5 and a control signal is output to external equipment via the output line 7a. Note that these transmitters and receivers are collectively referred to as a terminal.

The above-mentioned time-division multiplex transmission device has high transmission efficiency and high transmission quality, and the configuration of each terminal can be simplified, so it is widely used in the transmission of switch information in vehicles, etc., and in other fields. This is where it is used.

However, the conventional multiplex transmission device as described above requires a power supply line, an address clock signal line, and a data line, and requires at least three electric wires.

For example, if we consider the case where a multiplex transmission device is used in a vehicle, it is clear that the purpose of the multiplex transmission device is to transmit a large amount of information using the minimum amount of equipment, which may result in loss of transmission efficiency and quality. In order to further simplify the configuration of the multiplex transmission equipment, it is possible to reduce the number of three wires mentioned above to two, for example, without complicating the terminal configuration. is important.

[Object of the Invention] In view of the above-mentioned points, the present invention has been made to achieve the following without impairing the high transmission efficiency and high transmission quality of the conventional multiplex transmission device, and
Reduce the minimum number of wires to 2 without complicating the terminal configuration.
The object of the present invention is to provide a multiplex transmission device that can be used as a main unit.

[Summary of the Invention] To achieve the above object, the present invention provides a multiplex transmission device with a power supply/code that superimposes an inverted voltage of a predetermined address clock code on a power supply voltage to form a pulsed power/code superimposed signal. a superimposition circuit; a power/code superimposition line connected to the circuit and outputting the power/code superimposed signal in time series; a data line attached in parallel with the superimposition line; a charging unit connected to a data line and charged with the power source portion of the power supply/code superimposed signal; a demodulation unit demodulating the address clock signal superimposed on the power supply/code signal using the voltage charged in the charging unit; and a terminal having a data transmission unit that performs data transmission with the data line, and the minimum number of wires to be manufactured is two, the power/code superimposition line and the data line.

[Examples] Examples of the present invention will be described in detail below based on the drawings.

FIG. 1 shows a schematic diagram of a multiplex transmission apparatus according to an embodiment of the present invention. Figures 2 to 4 are detailed circuit diagrams of the constituent members;
FIG. 5 is an explanatory diagram of the operation.

As shown in FIG. 1, the multiplex transmission device 13 includes a power/code line 15 and a data line 17.

A power source/code superimposing circuit 19 is connected to one end of the power source/code line, and a transmitter 121 and a receiving WA 23 are connected to the power source/code line and the data line, respectively. Reference numeral B indicates a battery power source of voltage VB, 21a indicates an information input line to the transmitter 21, and 23a indicates an output line for control signals to external equipment of the receiver.

FIG. 2 shows a detailed circuit diagram of the power supply/code superimposition circuit 19.

As shown in FIG. 2, the power supply/code superimposition circuit 19 consists of an address clock generator 25 and a superimposition signal output circuit 27.

First, address clock generation Ia25 will be briefly explained as follows.

Address clock generator ta25 is reference clock generator 2
9, a shift register 31, an exclusive OR gate 35, and a width modulation circuit 37.

The shift register 31 consists of 3 bits, each bit (
ft.! A reference clock (for example, 1024H2) from the reference clock generator 29 is given at 12.03,
bit +13.020g1, bit g
The output of 1 and bit g2 is exclusive OR gate 35
It is designed to be input to bit g3 via. Although the details are omitted, at the beginning, bit Q+, (
J2. If signal 010 is input to g3,
The output signal of bit g1 changes to 010 every time the reference clock arrives.
1110, and this is repeated at the end of the cycle when the so-called M
Form a series of signals.

Then, the output of bit g1 is output to the width modulation circuit 907, where it is pulse width modulated and output as a serial signal of the tertiary M-sequence code. The form of this output signal is shown in Figure 5 (a
)It was shown to.

The high level is the battery voltage VB, and the low level is the ground voltage O. If the part with a wide pulse width is represented by 1 and the part with a narrow pulse width is represented by O, the signal output from the width modulation circuit 37 will be 01 in the same way as the output signal of bit g1.
01110... Howl.

The superimposed signal output circuit 27 is composed of a P channel and an N channel power MO8F and ET39.41. Both gates G of these two power MO8FETs 39°41,
Connect the output line of the address clock generator 25 to G, and also connect the source S of the P-channel power MO8FET 39 to the power supply B, and
The drain D of 41 is grounded. Then, connect the drain D of the P-channel power MO8FET 39 and the source S of the N-channel power MO8FET 41,
This connection point and the power supply/code line 15 are connected.

This superimposed signal output circuit 27 inverts the output signal from the address clock generator 25 shown in FIG. 5(a),
It acts to superimpose this on the power supply voltage. That is, the superimposed signal output circuit 27 outputs the P and N channel power MO.
The power supply voltage V3 is set to 0 by the 8FET39.41 at the high level of the address clock signal shown in Fig. 5(a).
level, and outputs a signal as shown in FIG. 5(b). , in addition, Fig. 5 (b
), To indicates the period of the synchronization signal of the address clock, T1 indicates the off time of the 0 signal, T2 indicates the off time of the 1 signal, and the duty ratio of the 0 signal (To −T+ )/
To, duty ratio of one signal (T.

T2)/To are both relatively large values.

FIG. 3 shows a detailed circuit diagram of the transmitter 21.

The transmitter 121 includes a charging circuit 43 and a transmitter circuit 45 serving as a transmitter.

The charging circuit 43 consists of a series circuit of a diode 47 and a capacitor 49, and the power supply/code line 15 and the diode 47 are connected so that the diode 47 is in the forward direction T when viewed from the line 15, and one end of the capacitor 49 is connected to the diode 47. It is grounded. The capacitance of the capacitor 49 is 10 μF to 500 μF. and,
A power supply circuit 5 is connected to the midpoint between the diode 47 and the capacitor 49.
1 is connected.

As shown in FIG. As described above, since the voltage sent from the power supply/code line is a signal with a sufficiently high duty ratio, this voltage (2) is lower than the battery voltage VB, but is sufficiently higher than the required voltage VOO.

The transmission circuit 45 is driven by receiving the voltage VDD from the power supply circuit 51, and includes an input buffer 53, an address demodulation circuit 55. Shift register 57° At/res determination circuit 59. In addition, an address control section 63 including a transmission control circuit 61 and an input data buffer 65 . It consists of a data shift register 67 and a transmitter 71 equipped with a data modulation circuit 69.

The input buffer 53 is connected to the voltage level VB of the power supply/code line 15.
is converted to the logic level VDD of this circuit.

The address demodulation circuit 55 demodulates the input width modulation pulse and extracts the tertiary M-sequence code and the clock signal. The 3-bit shift register 57 sequentially shifts the third-order M-sequence code inputted from the address demodulation circuit 55 to the right in the figure based on the clock signal obtained by the address demodulation circuit, and converts the 3-bit code inputted sequentially. It stores columns in sequence. The address judgment circuit 59 is a shift register 57
Input a 3-bit code string held in parallel, and compare this input code string with a 3-bit address assigned in advance, e.g. L, H, and as long as the two match. An address match signal is output to the transmission control circuit 61.

The transmission control circuit 61 controls the operation of the transmission section 71, that is, the data shift register 67 and the data modulation circuit 69 while the address match signal is input.

The data input buffer 65 has a register of predetermined bits according to the data to be transmitted, and converts the signal input via the input line 21a to a logic level within the circuit. The data shift register 67 is operated as a data manual buffer by a command from the transmission control circuit 61. Transmission data from the transmission control circuit 65 is input in parallel, and is sequentially output serially in accordance with a timing signal from the transmission control circuit 61.

The data modulation circuit 69 mixes serially input data with a timing signal from the transmission control circuit 61 to convert it into, for example, a width modulation pulse, and sequentially sends the serial data to the data line 17.

FIG. 4 shows a detailed circuit diagram of the receiver 23.

The receiver 23 includes a charging section 43 and a receiving circuit 73.

The configuration of the power receiving circuit 43 is the same as that of the power receiving circuit 43 of the transmitter described above, so the same reference numerals are given to its constituent members.

The receiving circuit 73 includes an address control section 75 and a receiving section 77. Since the address control section is similar to the address control section 63 of the transmitter 21 described above, its constituent members are designated with the same reference numerals as those of the control section 63. The receiving section 77 includes a data demodulation circuit 79, a shift register 81, and an output data buffer 83.

Received! The charging unit 43 of 1123 is the charging circuit 4 of the transmitter 21
Although it has the same configuration as No. 3, its operation is also similar.

Further, the operation of the address control section 75 excluding the reception control circuit 79 is also similar to the operation of the address control section 63 of the transmitter, so a description thereof will be omitted.

The data 1ili circuit 79 is connected to the data line 17,
In response to a demodulation command from the reception control circuit 79, the width modulated pulse sent from the transmitter 21 is input from the data line 17 and demodulated. The shift register 81 is the data demodulation circuit 7
Data is sequentially input serially from 9 and sequentially shifted to the adjacent register according to a timing signal. The data output buffer 83 inputs and latches the data in parallel according to a command from the reception control circuit 79 when the data is stored in all the registers of the shift register 81, and outputs it to the outside via the output line 23a. It is.

The operation of the multiplex transmission device having the above configuration will be explained.

First, in the power supply/code superimposition circuit shown in Fig. 2, the address clock signal shown in Fig. 5(a) and the power supply signal are superimposed to obtain the serial signal shown in Fig. 5(b). .

Therefore, the charging circuit 43 shown in FIGS. 3 and 4.
43 can obtain the voltage V shown in FIG. 5(C) via the power supply/code line 15. This voltage V is converted into vDD via the power supply circuit 51 and is supplied to the transmitting circuit 45 of the transmitter 21 and the receiving circuit 73 of the receiver 23, respectively, so that the transmitting circuit 45 and the receiving circuit 73 can operate. That is to say.

On the other hand, the data transmission section 45.73 between the transmitter and the receiver 1m receives the required voltage vDD via the power supply circuit 51, and uses the address clock signal superimposed on the power supply/code line to transmit data using the conventional three-way transmission circuit shown in FIG. Data transmission can be performed with the same efficiency and quality as a line multiplex transmission device.

In the above embodiment, data transmission is also performed by width modulation, but the data modulation method is not limited to this, and it goes without saying that an NRZ method without a synchronizing signal or a so-called bi-phase method may also be used.

Further, although the third-order M-sequence code was taken as an example in the above embodiment, it goes without saying that the same explanation can be applied to other sequence codes such as the fifth-order M-sequence code.

[Effects of the Invention] As explained in detail above, according to the present invention, the number of transmission lines can be reduced to at least two, the power/code line and the data line, and the transmission and It is an object of the present invention to provide a multiplex transmission device with high efficiency and high transmission quality, which can reduce the number of man-hours required for connection to a receiver, and minimize the installation cost, which increases depending on the length of the installation and the number of connection points. can.

[Brief explanation of drawings]

Fig. 1 is a schematic explanatory diagram of a multiplex transmission device according to an embodiment of the present invention, Fig. 2 is a circuit diagram of a superimposed signal output circuit, Fig. 3 is a circuit diagram of a transmitter, and Fig. 4 is a circuit diagram of a receiver. Figure 5 (a>, (b), and (c) are time charts of signals generated from the address clock generator, signals generated from the superimposed signal generation circuit, and signals input to the power supply circuit; Figure 6 is 13 is an explanatory diagram of a conventional multiplex transmission device. 13... Multiplex transmission device 15... Power supply/code superimposition line 17... Data line 19... Power supply/code superimposition circuit 21... Transmitter 23. ...Receiver 43...Charging section 45...Transmission section (transmission circuit) 73...Transmission section (reception circuit) B...Battery power supply Patent applicant Nissan Motor Co., Ltd. Fig. 2 Fig. 4

Claims (1)

[Claims] a power supply/code superimposition circuit that superimposes an inverted voltage of a predetermined address clock code on the power supply voltage to form a pulsed power/code superimposed signal; and a power supply/code superimposition circuit connected to the circuit to output the power/code superimposed signal in time series. a power source/code superimposing line, a data line attached in parallel with the superimposing line, a charging unit connected to the superimposing line and the data line, and charged by a power source portion of the power source/code superimposing signal; A terminal having a demodulation section that demodulates the address clock signal superimposed on the power supply/code signal using a voltage charged in the charging section, and a data transmission section that transmits data to and from the data line. A multiplex transmission device consisting of