JPS6097436A - Rounding control circuit - Google Patents

Abstract

PURPOSE:To speed up rounding processing by detecting whether mantissa data is increased to output a carry before a mantissa is increased. CONSTITUTION:Mantissa part data, exponent part data, and a sign before rounding processing are stored in registers 101 and 105 and a sign bit 104 in a period phi2 of a period T1. A specific rounding mode is stored in a rounding mode register 103 until the period phi2 of the period T1. A round-up/round-off decision circuit 105 and a carry look-ahead circuit 107 operate in a period phi1 of the period T1. Further, the mantissa part data in the register 101 is passed through a mantissa data bus 108 and latched by a mantissa part adder 109 in the period phi1 of the period T1, and the exponent part data in the register 115 is latched by an exponent part adder 117 through an exponent data bus 116. The mantissa part adder 109 and exponent part adder 117 operate in the period phi2 of the period T2. At this time, the mantissa part adder 109 uses the decision signal 106 of the round-up/round-off decision circuit 105 as the least significant digit bit.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a rounding circuit in floating point arithmetic.

Generally, the format of floating point data is expressed by separating fields into a sign part, an exponent part, and a mantissa part, as shown in FIG. In arithmetic operations on floating point data, the data length of the mantissa often exceeds the predetermined data length during the operation process. For example, in the case of floating-point multiplication, the mantissa part is multiplied by arithmetic, and the result of computation of the true mantissa has a data length twice the mantissa data length that can be represented. At this time, rounding is an attempt to fit the true calculation result within the mantissa data length that can represent it, and the final calculation result is obtained through this rounding process.

Normally, computers that handle floating-point data have some form of means to store data that overflows from the least significant bit of the mantissa during the calculation process, and depending on the content of the overflowing data and the rounding mode, The final operation result is obtained by rounding up or discarding the intermediate result of the mantissa. That is, in the rounding process, depending on the rounding mode and the contents of the overflowing data, it is decided whether to add 1 to the intermediate result of the mantissa part or leave it as is.

However, as shown in Figure 2, when rounding data where the intermediate result of the mantissa is all "]", by adding l, a carry occurs and the mantissa becomes all "0". . This is due to an overflow from the topmost pit of the mantissa, and the mantissa data is
...0" and corrected it.

and the exponent must be incremented by (.1).Therefore, it is necessary to perform rounding taking into account the above special case.

Conventionally, rounding processing followed the steps in the flowchart shown in Figure 3. When handling data, it does not often happen that the carry of the result of incrementing the mantissa by 1 due to rounding processing becomes "1", but it is necessary to take this into consideration and check the carry after incrementing the mantissa by 1. Don't check Carrie,
The rounding time also included the time required to complete the rounding process.

Furthermore, if the carry becomes "1" as a result of incrementing the mantissa by 1, the mantissa and exponent are corrected, so the entire rounding process takes about twice as much time, significantly reducing processing speed. There were drawbacks that made it worse.

The present invention solves the above-mentioned drawbacks by detecting whether the mantissa data is incremented and outputs a carry before incrementing the mantissa, and provides a rounding control circuit that can speed up the rounding process. It is.

In order to achieve the above object, the rounding control circuit of the present invention includes a determination circuit that determines whether to round up or truncate when the lower digits overflow in floating point data, and a judgment circuit that determines whether to round up or truncate the lower digits of floating point data.
1, an adder for the mantissa part, and an adder for the exponent part. When it is detected that all bits are logic rlJ, the exponent data is incremented by 1 in the adder of the exponent part, and the most significant bit of the mantissa data is added.

It is characterized by forcibly setting the output to logic "1".

An embodiment of the present invention will be described below based on the drawings. Fourth
The figure is a block diagram of one embodiment of the present invention. Referring to FIG. 4, the first embodiment of the present invention includes a 24-bit long register 101 that stores mantissa data before rounding, a 3-bit rounding register 102 that stores the lower part of the mantissa data, and a rounding register 101 that stores the mantissa data before rounding. a 2-bit long rounding mode register 103 that stores the mode of the rounding, a code pit 104 that stores the sign of the mantissa, the lowest pit of the 24-bit long register 101, the rounding register 10203 bit data, the rounding mode register 103 2-bit data and the code pit 10401-bit data are input, and the rounding/up/down process determines whether to round up or discard the mantissa data.
The 24-bit data of the 24-bit length register 101 and the judgment signal 106 which is the output of the round-up/round-down judgment circuit 105 are input to the round-down judgment circuit 105, and it is detected whether there is a carry when the mantissa data is rounded. carry lookahead circuit] 07 and the 24-bit long register 10
24-bit data of 1 is input via the mantissa data bus 108, and a 24-bit length mantissa adder 109 is incremented by the judgment signal 106, and a 24-bit length constant "100...0" is input. A game in which the contents of the constant generation circuit 110 are output to the mantissa data bus 108 by the constant generation circuit 110 generated and the carry signal 111 which is the output of the carry look ahead circuit 107.
2, a game) 113 for outputting the calculation result of the mantissa part adder 109 to the mantissa data bus 108 by a carry signal 111 which is the output of the carry look ahead circuit 107, and a game) 113 for storing the mantissa data of the rounding unit Wl. 24 bit length V
7 to store raster 114 and exponent data before rounding
The 7-bit data of the bit length register 115 and the 7-bit length register 115 are inputted via the exponent data bus 116, and incremented by the carry signal 111. , and a 7-bit register 118 for storing rounded exponent data. Next, the operation of the first embodiment will be explained in detail with reference to FIGS. 4 and 5. FIGS. 1 and 5 are simple timing charts showing the rounding process in the first embodiment.

First, during the period of T1, the mantissa data, the exponent data, and the sign before rounding are stored in the V dimeta 1011 register 115*n bit 104, respectively.

Also, by the second period of T1, the rounding mode is stored in the rounding mode register 103.Next, in the second period of T1, the rounding up/down judgment circuit 105 and the carry look ahead circuit 107 are activated. In other words, the rounding up/down determination circuit 105 uses the data in the rounding mode register 103, the data in the rounding register 102, and the sign bit 104.
When rounding the floating point data, it is determined whether to round up or down according to the logic shown in Table 1, and if it is rounded up, a determination signal 106 is sent.
is output as "1", and if it is truncated, the determination signal 106 is output as "0". Further, the carry look ahead circuit 107 uses the 24-bit long plate number data in the register 101 and the judgment 16.
Enter number 106.

To detect in advance whether a digit shift in a mantissa occurs in rounding processing. In other words, the 24-bit long plate number data is all "1" and is MR'+M-f-! t106 is “
MTh is detected. When an overflow occurs, the above-mentioned carry outputs the signal 111 as "1", and the overflow does not occur. During the period of (・
Also, for the mantissa part, the register l1024 bit data is passed through the mantissa data bus 108f (and is latched by the mantissa adder 109), and for the exponent part, the 7-bit data in register l15 is passed through the exponent data bus 116, and the exponent part data is sent to 117. Then, the mantissa is 1j between 1; 2jlJj of T2.
IX7Il# a l O9 (!: exponent base n unit 117
and works. At this time, the mantissa adder 109 uses the judgment signal 106 output from the round-up/truncation 'C judgment + Pl path 105 as the carry value of the least significant bit. In other words, the judgment signal 106 is ”, the mantissa adder 109 increments by 1 the mantissa data that was doubled at the previous timing. Conversely, the determination signal 106 is "0".
”, the mantissa adder 109 leaves the mantissa data latched at the previous timing as is without incrementing the mantissa data. Further, the exponent part adder 117 uses the carry signal 111 outputted from the carry look-ahead circuit 107 as a carry signal for the least significant bit. That is, digit J
If the signal 11 is "1", the exponent part adder 117 increments the exponent data latched at the previous timing by 1. Conversely, if the carry signal 111 is "0", the exponent part adder 117 increments the exponent data latched at the previous timing. Leave the latched index data as is without incrementing it. Finally, T2
In the da1 period, the mantissa data after rounding is transferred to the register 114 for the mantissa part, and the exponent data after rounding is transferred to the register 118 for the exponent part. At this time, in the mantissa part, if the carry signal 111 output at the previous timing is "0", the gate 113 is turned on, and the operation result in the mantissa part adder 109 is sent to the register 114 via the mantissa data bus 108. be transferred. Conversely, if the carry signal 111 is "1", the gate 112 is turned on and the 24-pit length constant "100...0" stored in the constant generation circuit 110 is transferred to the mantissa data bus 108. The data is transferred to the register 114 via the register 114. In addition, in the exponent part, the calculation result in the exponent part adder 117 is sent to the register 118 via the exponent data bus 116.
will be forwarded to.

Therefore, it only takes two clocks to round floating-point data and store it in a predetermined register (--rounding processing can be realized at extremely high speed.

FIG. 6 shows the round-up/round-down determination circuit 105 in FIG.
1 is an example of a circuit diagram of a specific configuration. Table 1 logically represents the function of the rounding up/down judgment circuit 118105.

Rounding up/rounding down determination circuit 105 selects RM indicating rounding mode.
I, RMO, rounding bits G, R', S, and the least significant bit of the rounding front board data. and Big indicating the sign of the mantissa data, and outputs a 1 determination signal 106 according to the logic diagram shown in FIG. Regarding the rounding mode (the closest approximation is determined by the values of RMI, R, MO,
Four types of rounding are defined: -〇〇 major direction, +00 major direction, and 0 direction rounding. Also, the 3 bits for rounding are weighted, and the percentage of the least significant bit D0 of the mantissa data is G and K.
is the logical sum of the mantissa data and the data bits with digits shifted below G and R.

FIG. 8 is an example of a circuit diagram of a concrete configuration of the carry look-ahead circuit 107 in FIG. 4.

The carry look-ahead circuit 107 inputs the 24-bit length mantissa data D, , D, . . . It outputs a signal 111. First, the configuration of the carry look ahead circuit 107 will be shown with reference to FIG.

Mantissa data D, , D, 2...DI.

Do respectively pass through inverter elements to the 23rd transistors 223. 22nd transistor 222°...first transistor 201. Connected to the gate of the first transistor 201. The drain sides of the 23rd transistor 223 to the 0th transistor 200 have mantissa data all "l".
They are connected by a detection line 230, and their sources are connected to ground via transistors each using Da1 as a gate signal. The precharge transistor 240 has its drain side connected to the power supply, its source side connected to the mantissa data all "1" detection line 230, and its gate connected to 02. In addition, the mantissa data all “1” detection line 23
0 is connected to the power side of the inverter element 2600A through the transfer transistor 250 whose gate signal is 01. The output of the inverter element 260 is the output of a two-person NOR element 270. Another input line of the two-way NOR element 270 is an inverted version of the determination signal 106.

Next, the operation of the carry look ahead circuit 107 will be explained in detail. First, when 02 is "1", the mantissa data all "1" detection line 230 is precharged and becomes "1". Next, when G1 becomes "l", the mantissa data D, , , D,...
- If at least one bit among Dl and Do is "0", the transistor corresponding to that bit is turned on and the mantissa data all "1" detection line 230 is discharged to become "0", and the inverter element 260 The output becomes "l".

Conversely, mantissa data I) ts t I) tt...Dl,
If all pits of Do are rxJ, the 23rd transistor 2
The 23rd to 0th transistors 200 are all turned off, and the mantissa data all "1" detection line 230 remains charged.
1", the output of the inverter element 260 becomes "0". Furthermore, the output of the inverter element 260 is "0"
Two-man power N0R only when the judgment signal 106 is “1”
The carry signal 111, which is the output of the I-child 270, becomes "1".In this way, according to this embodiment, any kind of floating point data is not checked by software, but is simply Depending on the circuit configuration, it is possible to realize extremely high-speed rounding processing.

Although this embodiment deals with floating point data having a mantissa data length of 24 bits and an exponent data length of 7 bits, it is clear that the same structure may be applied to extended formats.

In this embodiment, a constant generating circuit 110 storing a 24-bit long constant "100...0", a gate 112, and a gate 1 are used.
13, when the carry signal 111 is "1", the gate 113 is closed and the gate 112 is opened, and the constant "100.
. . 0" was output to the mantissa data bus 108, but the most significant bit of the data from the adder 109 is set to logic "1" only when the carry signal 111 is "1". 24-bit data to mantissa data bus lo8
If the constant generating circuit 110 and the gate circuit 112 are configured to be outputted, the constant generating circuit 110 and the gate circuit 112 are unnecessary, and the same effect as the first embodiment can be obtained.

FIG. 9 shows a circuit in which the functions of the constant generating circuit 110, gates 112, and gates 113 in the first embodiment are considered in another way. Mantissa adder 109024-bit output result its e ■22 t...■. When outputting the signal to the mantissa data bus 108, the data output control circuit 113' sets the most significant line Du of the mantissa data bus 108 to the drain side, as shown in FIG. 9, and gates the inverted signal of the carry signal 111. Transistor 330 and mantissa adder 10
A transistor 323 whose gate is the inverted signal of XtS, which is the most significant bit of the 9024-bit output result, and whose drain side is the source of the transistor 330;
The inverted sign is gated and the drain side is connected to the mantissa data bus 10.
8 glue 8. Similarly, the transistor 322 and Io
The gate is the inverted signal of , and the drain side is the mantissa data bus 108 . The transistor 300 is configured to be integrated with the transistor 300 . Here, the mantissa adder 109024 bit output result 123sI12...■.

In the example just before outputting the data to the mantissa data bus 108, the mantissa data bus 108 is recharged and all data lines are set to "1".
1, at this time the carry signal 111 becomes "
1'', transistor 330 is turned off and D
2. remains charged and becomes "]", and furthermore, the 24-bit output result of the mantissa adder 109 is 11m, 2t...
・Eng. is expected to be all "0", transistors 322 to 300 are turned on, and 1D2. ~1
]. is discharged and becomes "0". Conversely, when the carry signal 111 is "0", the transistor 330 is turned on and the output voltage is ttstItt....

It is clear that is output to the mantissa data bus 108 as is.

Therefore, the same effect can be obtained by using the data output control circuit 113'.

[Brief explanation of drawings]

FIG. 1 is a format diagram of floating point data. Figure 2 is a flowchart showing the rounding process for special mantissa data, Figure 3 is a flowchart showing the procedure of conventional rounding process, and Figure 4 is the first embodiment of the present invention. FIG. 5 is a timing diagram in the first embodiment of the present invention. FIG.
7 is a circuit diagram showing an example of the round-up/round-down determination circuit shown in FIG. , FIG. 8 &;IjJ
FIG. 4 is a circuit diagram showing an example of the carry look ahead circuit in FIG. 4; FIG. 9 shows the constant generation circuit 110 in FIG.
12 is a circuit diagram in which the functions of gate 12 and gate 113 are realized by another method. 101...Register, 102...Rounding bit. 103...Rounding mode register, 104...
. . . Sign bit, 105 . . . Round up/down judgment circuit, 106 . . . Judgment signal, 107 .
... Carry look ahead circuit, 108... Mantissa data bus, 109... Adder, 110...
Register, 111...Carry signal, 112...
...Gate, 1] 3...Gate, 1
14...Register, ]15...Register, 116
...Exponent data bus, 117...Adder, 118...Register, 200-223 Old...Transistor, 230...Mantissa data all "1" ”Detection line, 240・Old...transistor, 250
...Transistor, 260...Inverter element, 270...2 human power NO Keiko, 30
0~323...Transistor, 33o...Transistor, 113'...Data output control circuit\, '5+'/' Fig.4 Fig.1T11T21 Fig.S Fig.6' Fig./66 Glans 8 Fig. Gun 9 Fig.

Claims (1)

[Claims] In a rounding control circuit for floating point arithmetic, there is a determination circuit that determines whether to round up or truncate when the lower digits of mantissa data overflow, a detection circuit that detects that all bits of mantissa data are logic "1", and a mantissa part. and an exponent part adder, and when the floating point data is determined to be rounded up by the determination circuit, and the detection circuit detects that the mantissa data is all bits logical "1". A rounding control circuit characterized in that the exponent data is incremented by the adder of the exponent part, and the most significant bit of the mantissa data is forcibly set to logic "l".