JPS5959088A - Filter circuit for control circuit - Google Patents
Filter circuit for control circuitInfo
- Publication number
- JPS5959088A JPS5959088A JP57168328A JP16832882A JPS5959088A JP S5959088 A JPS5959088 A JP S5959088A JP 57168328 A JP57168328 A JP 57168328A JP 16832882 A JP16832882 A JP 16832882A JP S5959088 A JPS5959088 A JP S5959088A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- digital
- output
- control circuit
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P5/00—Arrangements specially adapted for regulating or controlling the speed or torque of two or more electric motors
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02K—DYNAMO-ELECTRIC MACHINES
- H02K11/00—Structural association of dynamo-electric machines with electric components or with devices for shielding, monitoring or protection
- H02K11/30—Structural association with control circuits or drive circuits
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、モータサーボ位相制御装置に係り、特に、定
常状態位相誤差の補正機能と位相遅れ補償とをディジタ
ル沖波回路により施すに好適な自動制御装置に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a motor servo phase control device, and in particular to automatic control suitable for performing a steady state phase error correction function and phase lag compensation using a digital Okinawa circuit. Regarding equipment.
本発明の利用分野の一例を第１図のブロック図により説
明する。An example of the field of application of the present invention will be explained with reference to the block diagram of FIG.
第１図において１はモータの回転位相信号を発生するタ
ンクパルス発生器、２はモータ、３はモータの周波数信
号を発生する周波数発生器、４はモータ駆動回路、５は
ディジタル速度制御回路、６はディジクル位相ｆＵ１４
１１１１回路、７は加算器、８，１０はディジタル−ア
ナ［−１り変換器、９はアナロクーデイジタル変換器、
１１は位相補償回路、１２は低域通過型沖波回路（以下
、ＬＰＦと略す。このり、１）Ｆ１２の機能については
、本出願人の昭和５７年８月３０日付出願１一定常状態
位相誤差補正方法およびその装置」に詳述されている。In FIG. 1, 1 is a tank pulse generator that generates a rotational phase signal for the motor, 2 is a motor, 3 is a frequency generator that generates a frequency signal for the motor, 4 is a motor drive circuit, 5 is a digital speed control circuit, 6 is digital phase fU14
1111 circuit, 7 is an adder, 8 and 10 are digital-to-analog converters, 9 is an analog-to-digital converter,
11 is a phase compensation circuit, and 12 is a low-pass Oki wave circuit (hereinafter abbreviated as LPF). Regarding the function of F12, the function of F12 is described in Application No. 1 Constant Steady State Phase Error filed by the present applicant on August 30, 1982. "Correction Method and Apparatus".
）である。ここで示されている位相制御、速度制御機構
そのものは周仄）１のものであり、説明は控える。本件
出願において特に注目しているのは位相補償回路１１と
ＬＰＦ１２でありこれらの具体例を第２図に示す。第２
図において、１３１４．１６は抵抗、１５．１７は容量
である。抵抗をＨａ容量をＣで示すとｌＬ＋ ３ 、Ｒ
１４、Ｃ１５より成る位相補償回路１１の伝達関数■■
１（３）は
となり、ここでＴａ＝Ｃ１ｓ（Ｒｔ３＋）も＋４ ）
、 Ｔｂ＝Ｃ１ｓＲ１３（Ｔａ）Ｔｂ ）である。). The phase control and speed control mechanisms themselves shown here are those of Part 1, and will not be explained here. Particular attention is paid to the phase compensation circuit 11 and the LPF 12 in this application, and a specific example thereof is shown in FIG. Second
In the figure, 1314.16 is a resistance, and 15.17 is a capacitance. If the resistance and Ha capacity are expressed as C, then lL+ 3 , R
14, Transfer function of phase compensation circuit 11 consisting of C15■■
1(3) becomes, where Ta=C1s(Rt3+) is also +4)
, Tb=C1sR13(Ta)Tb).
この位相補償回路のゲイン、位相特性は第３図に示すよ
うなものとなる。一般的に自動制御系では、系の開ルー
プゲインを極端に増加すると系が不安定になる。これに
対し、上記のような位相補償回路を付加すると、未補償
の系に比べ、系の安定を確保したまま、低減のケインの
み増加させることが可能である。外乱の系への影響はゲ
イン分の−に減少ぜらるので、上記補償回路を加えれば
直流外乱に対して強く、かつ安定な自動制御系となる。The gain and phase characteristics of this phase compensation circuit are as shown in FIG. Generally, in an automatic control system, if the open loop gain of the system is increased excessively, the system becomes unstable. On the other hand, if a phase compensation circuit as described above is added, it is possible to increase only the reduction cane while ensuring stability of the system compared to an uncompensated system. Since the influence of disturbance on the system is reduced by the gain, adding the above-mentioned compensation circuit will result in an automatic control system that is strong and stable against DC disturbances.
一方、第２図において、抵抗１６、容量１７より成るＬ
ＰＦ１２の伝達関数Ｈ２（８１はＲ２（ｓ） ＝−ニー
・・・（２）
１＋ＳＴｃ
となり、ＴＣ＝Ｒ１り Ｃ１？である。On the other hand, in FIG. 2, L consisting of a resistor 16 and a capacitor 17
The transfer function H2 of PF12 (81 is R2(s) = -knee...(2) 1+STc, and TC=R1 ri C1?).
この回路のゲイン、位相特性は第４図に示すものである
。この回路は位相制御回路６の出力の直流変動分、即ち
、ドリフト成分（定常誤差信号）のみを抽出するための
ものである。The gain and phase characteristics of this circuit are shown in FIG. This circuit is for extracting only the DC fluctuation component of the output of the phase control circuit 6, that is, the drift component (steady error signal).
前述した位相補償回路１１とＬＰＩ”１２とを第２図に
示したような−ｒナログ回路で実現すると、Ｉ（”集積
化した場合外付部品が増す上、４つの入出力ビンを要す
る。If the phase compensation circuit 11 and the LPI 12 described above are implemented using a -r analog circuit as shown in FIG. 2, the number of external components increases and four input/output bins are required when integrated.
以−Ｈのように第１図の構成によれは、抵抗、容量等の
外付部品数や入力、出力ビンの増加をまねくという欠点
があった。これに対し、近年ではフィルタ類をディジタ
ル処理する傾向が強く、これらをディジタルフィルタに
置換するこ吉が一般的に考えられる。そこで次に第５図
１こ示すディジタルフィルタへの置換を考える。第５図
において、２０，２１，２３，２４．３２は乗算器、２
２゜２５は遅延保持器、２６ 、２７ 、２８ 、２９
は加算器、３０はサンプラ、３１はデイシタルアナロク
変換器、３３は位相補償部ディジタルフィルタ、３４は
ロウバスディジタルフィルタである。第５１′ｙ、］の
ディジクルフィルタへの置換は、メー次変換によるｐ波
回路設計法を用いたちので、これは次の手続きによる。The configuration shown in FIG. 1, as shown in FIG. On the other hand, in recent years there has been a strong tendency to digitally process filters, and it is generally considered possible to replace these with digital filters. Next, let us consider replacing the filter with the digital filter shown in FIG. In FIG. 5, 20, 21, 23, 24.32 are multipliers, 2
2゜25 is a delay holder, 26, 27, 28, 29
30 is an adder, 30 is a sampler, 31 is a digital-to-analog converter, 33 is a phase compensator digital filter, and 34 is a low-pass digital filter. The replacement of the 51'th y, ] with a dicicle filter uses the p-wave circuit design method using Mae-order transformation, so this is done according to the following procedure.
即ち、連続時間系から紐散時間系への変換は、（３）式
の関係を用いでＳ平面からＺ平面に写像することにより
行われる。That is, the conversion from the continuous time system to the string discrete time system is performed by mapping from the S plane to the Z plane using the relationship of equation (3).
（３）により（す、’（２）は次のように変換される。According to (3), (su,'(2) is converted as follows.
ここで である。here It is.
上記のようにディジタルフィルタを用いた技術は、フィ
ルタ類のＩＣ内蔵化により、入出力ビン数、内部素子数
の低減がはかれるかわりに、ＩＣ内蔵素子数の増大とい
う欠点を有していた。As described above, the technology using digital filters has the disadvantage that, although the number of input/output bins and the number of internal elements can be reduced by incorporating the filters into an IC, the number of elements built into the IC increases.
本発明の目的は、上述したｐ波回路の構成要素である容
量や抵抗を除き、この機能をＩＣ内に内蔵し、さらにＩ
Ｃ内の構成素子数を低減させて、ナツブサイスの小型化
によるＪＣのコストタウンをはかることにある。It is an object of the present invention to eliminate the capacitance and resistance that are the constituent elements of the p-wave circuit described above, incorporate this function into an IC, and furthermore
The purpose is to reduce the cost of JC by reducing the number of components in C and downsizing the nut size.
本発明の主眼は、異なつンこ特性の沢阪回路出力として
、単一のディジタル戸波回路から複数の出力をとり出す
ことにある。これは、先に述べたアナロウ回路による実
ＪＪｌ法が市するデメリットを克服するため、これりを
ディジタルフィルタに置換し、なおかつ、少ない素子数
で実現することを可能にする。The main purpose of the present invention is to extract a plurality of outputs from a single digital Toba circuit as Sawazaka circuit outputs having different characteristics. This makes it possible to replace the actual JJl method with a digital filter and realize it with a small number of elements in order to overcome the disadvantages of the real JJl method using the analog circuit described above.
以下、本発明の一実施例を渠に図シごより説明する。先
に説明した第３図、第４図の特性を有する位相補償回路
、およびＬ ｐ ＦＣＤカットオフ周波数（第３図ｊ’
ｃｌ、第４図ｆＣ２）は通常ｆｃｔ ＝０、０１ Ｈｚ
〜０．１１−Ｉｚ程度、ｆｃ２＝ ｌ Ｈｚ以下に選
ばれる。Hereinafter, one embodiment of the present invention will be explained with reference to the drawings. The phase compensation circuit having the characteristics shown in FIGS. 3 and 4 described above, and the L p FCD cutoff frequency (j'
cl, Fig. 4 fC2) is usually fct = 0, 01 Hz
It is selected to be about ~0.11-Iz, fc2=l Hz or less.
従って、Ｃ１５（１−Ｌｘａ−４−ＬＬｕ）＝＝Ｒ１６
Ｃ１７＝τとし、カットオ通に選べは
Ｈ２（Ｚ） ＝−ニーに２ ・・・（９）１＋ＤＺ−
１
Ｔ−２τ
となる。ここで””Ｔ＋２ｒ である。従って、これ
らを実現才ろブロック図が第６図のように得られる。構
成する各要素はＩ訂５１閑のものと等しい。第５図と第
６図を比較すれば明らかなように、来貢・、器、加痒器
、遅延保持要素力新ｉＪ減されている。このように本発
明を用いれば、素子数増加をおさえつつ、ディジタルフ
ィルタ化できる効果がある。Therefore, C15(1-Lxa-4-LLu)==R16
Assuming that C17=τ, the choice for cuto experts is H2 (Z) = - 2 for knee ... (9) 1 + DZ -
1 T-2τ. Here, ""T+2r. Therefore, a block diagram for realizing these is obtained as shown in FIG. The constituent elements are the same as those in I-edition 51. As is clear from a comparison between Figures 5 and 6, the amount of force used by the tributary, vessel, pruritus, and delayed retention element has been reduced. As described above, by using the present invention, it is possible to use a digital filter while suppressing an increase in the number of elements.
最後に本発明の他の実施例を、！ｇ７図に示しておく。Finally, another example of the present invention! This is shown in Figure g7.
こｆｌ、はディジタルフィルタの構成をわずかに変えた
（乗算器２１．２３の後段に遅延保持回路２２’、２２
“を設Ｗ）のみで、第６図のものと基本的差異は７′１
′い。このように、乗偉器、遅延保持素子の順番を入れ
替えて（８） 、 （ｆｌ）の伝達関数を有しブこディ
ジタルフィルタを構成することが可能なことは明らかで
ある。In this fl, the configuration of the digital filter is slightly changed (delay holding circuits 22' and 22 are installed after the multipliers 21 and 23).
The basic difference from the one in Figure 6 is 7'1
'stomach. In this way, it is clear that it is possible to configure a digital filter having the transfer function (8) and (fl) by changing the order of the multiplier and the delay holding element.
なお、本例では位相制御系における定常誤差を補正する
回路；Ｉｌｌ成とし、ここにディジタルのＬＰＦを設け
たが、速度制御系における定常誤差を・演出、補正する
回路ぞ４成とし、同様に本発明を実飽することｂ可能で
ある。In this example, the circuit for correcting the steady error in the phase control system is configured as Ill, and a digital LPF is provided here, but the circuit for correcting and directing the steady error in the speed control system is configured as 4 circuits. It is possible to implement the present invention.
し発明の効果〕
本発明によれば、従来フィルタ類をアナログ回路で３（
現していたため、制御回路をＩＣ化した場合生ずる入出
力ビン数、外部部品の増加という問題を回避でき、さら
にディジタル化に伴う素子数増大８軽減できるので、小
型化、コストダウンがはかれる。[Effects of the Invention] According to the present invention, conventional filters can be replaced with three (3) analog circuits.
Therefore, it is possible to avoid the problem of an increase in the number of input/output bins and external components that would occur when the control circuit is integrated into an IC, and furthermore, the increase in the number of elements due to digitalization can be reduced, resulting in miniaturization and cost reduction.
ＩＳＩ、２，３，４．５図は本発明の詳細な説明するた
めの図、ｇＩＧ ６図は本’ｔ？ｆ＝明の一実施例を説
明するための図、第７図は本発明の他の実施例を説明す
るための図である。
５・・・速度制御回路 ６・・・位相比較回路２２
．２２’ 、２２“・・・遅延保持回路２０．２１，２
３．３２・・・乗算器
２６ 、２７ 、２８・・・加算器
茅 ｌ 圀
’ｊ’Ｃｙ 第３１
ｉ立鞘ず産量
りｍ−−−−−ＪISI, Figures 2, 3, and 4.5 are diagrams for detailed explanation of the present invention, and Figure 6 is from the book't? FIG. 7 is a diagram for explaining one embodiment of f=light, and FIG. 7 is a diagram for explaining another embodiment of the present invention. 5... Speed control circuit 6... Phase comparison circuit 22
．． 22', 22"...delay holding circuit 20, 21, 2
3.32... Multipliers 26, 27, 28... Adder 茀l 圀'j'Cy 31st i Tachiyazu production m-----J
Claims (1)
補償回路をディジタルＪ−１波回路で構成し、該ディジ
タル沖波回路の出力により制御を施すと共に、該ディジ
タル′Ｏ１波回路の他の出力より定常誤差信号を取り出
１−ことを特徴とする制御回路の沖波回路。1. In a control circuit having a phase compensation circuit, the phase compensation circuit is constituted by a digital J-1 wave circuit, and control is performed by the output of the digital Oki wave circuit, and the steady state is controlled by the output of the digital Oki wave circuit. An Okinami circuit of a control circuit characterized by extracting an error signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57168328A JPS5959088A (en) | 1982-09-29 | 1982-09-29 | Filter circuit for control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57168328A JPS5959088A (en) | 1982-09-29 | 1982-09-29 | Filter circuit for control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5959088A true JPS5959088A (en) | 1984-04-04 |
Family
ID=15866000
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57168328A Pending JPS5959088A (en) | 1982-09-29 | 1982-09-29 | Filter circuit for control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5959088A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6142015A (en) * | 1984-08-02 | 1986-02-28 | Matsushita Electric Ind Co Ltd | Digital phase controller |
| JPS61143822A (en) * | 1984-12-18 | 1986-07-01 | Hitachi Ltd | Digital control device |
| JPS63143098U (en) * | 1987-03-10 | 1988-09-20 |
-
1982
- 1982-09-29 JP JP57168328A patent/JPS5959088A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6142015A (en) * | 1984-08-02 | 1986-02-28 | Matsushita Electric Ind Co Ltd | Digital phase controller |
| JPS61143822A (en) * | 1984-12-18 | 1986-07-01 | Hitachi Ltd | Digital control device |
| JPS63143098U (en) * | 1987-03-10 | 1988-09-20 |
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