JPS58218169A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS58218169A JPS58218169A JP10153482A JP10153482A JPS58218169A JP S58218169 A JPS58218169 A JP S58218169A JP 10153482 A JP10153482 A JP 10153482A JP 10153482 A JP10153482 A JP 10153482A JP S58218169 A JPS58218169 A JP S58218169A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- integrated circuit
- substrate
- semiconductor integrated
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 230000005669 field effect Effects 0.000 claims description 7
- 239000010408 film Substances 0.000 claims description 7
- 239000010409 thin film Substances 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 4
- 239000012808 vapor phase Substances 0.000 abstract description 4
- 238000000137 annealing Methods 0.000 abstract description 2
- 239000007772 electrode material Substances 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 abstract 1
- 239000005368 silicate glass Substances 0.000 abstract 1
- 239000000463 material Substances 0.000 description 5
- 238000001947 vapour-phase growth Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000002195 synergetic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は薄膜中導体を基板として用いたＭＯ８型電界効
果トランジスタを構成要素とする半導体集積回路に関し
、ゲートに用いた電極構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit comprising an MO8 type field effect transistor using a thin film medium conductor as a substrate, and relates to an electrode structure used for a gate.
アモルファスや多結晶薄膜中導体を基板として用いたＭ
Ｏ８電界効果トランジスタの研究開発力さかんにおこな
われている。それは薄膜ＭＯ８電界効果トランジスタを
構成要素とする半導体集積回路装置が実用可能となると
、種々の大きなメリットが出てくるからである。たとえ
ば、大幅なコストダウンが期待できるのと、大型のＩＣ
及び多層構造のＩＣ等が実現して、ＩＣの大きな応用範
囲が出現する。M using an amorphous or polycrystalline thin film medium conductor as a substrate
Research and development efforts for O8 field effect transistors are being actively carried out. This is because if a semiconductor integrated circuit device having thin film MO8 field effect transistors as a component becomes practical, various great advantages will emerge. For example, we can expect significant cost reductions and large ICs.
With the realization of multi-layered ICs and the like, a wide range of applications for ICs will emerge.
現在、至るところで研究開発されつつあるこの薄膜１ｊ
ＯＥＩ電界効果トランジスタ及び集積回路装置にも大き
な問題点がいくつか存在す石。This thin film 1j is currently being researched and developed everywhere.
There are some major problems with OEI field effect transistors and integrated circuit devices.
その大きな問題の中Ｋ、ソース・ドレイン間のリークが
あり、又、トランジスタのドライブ能力、すなわち移動
度が小さいという問題がある。Among the major problems are leakage between the source and drain, and the problem of low transistor drive ability, ie, low mobility.
シリコン単結晶基板を用い次トランジスタのドレインリ
ークは、トランジスタ１個あたシに換算すると１０−Ｂ
〜１０−”Ａ程度となる。それに比較してアモルハスシ
リコン及び多結晶シリコンを基板として用いた薄膜ＭＯ
Ｂ電界効果型のソース汲びドレイン間のリークは、トラ
ンジスタ１個ア次シに換算するとＩ Ｌｌ−’〜１Ｑ−
１０Ａであり、２桁〜５桁多い。その定めスタティック
タイプの駆動でもリークが多くて問題はめるし、ダイナ
ぐツクタイプの駆動ではリークのため動作ができなくな
ってしまう。The drain leakage of the next transistor using a silicon single crystal substrate is 10-B when converted to one transistor.
~10-”A. In comparison, thin film MOs using amorphous silicon and polycrystalline silicon as substrates
The leakage between the source and drain of the B field effect type is I Ll-' ~ 1Q- when converted to one transistor.
10A, which is 2 to 5 digits more. Even with a static type drive, there is a lot of leakage, which causes problems, and a dynamic type drive cannot operate due to leakage.
又、薄膜Ｍ Ｑ Ｓ ’ｉｌ界効果トランジスタを構成
要素とする半導体集積回路装置の応用範囲の中には液晶
表示パネルの電極パネルとして使用されるなど光を直接
うける用途があり、この場合には前記したリーク電流値
がさらに大きくなる。Furthermore, among the applications of semiconductor integrated circuit devices that use thin-film MQS'IL field-effect transistors as constituent elements, there are applications in which they are directly exposed to light, such as being used as electrode panels for liquid crystal display panels. The leakage current value described above becomes even larger.
さらに、移動度が小さいためにスピードを要求する回路
には不向であシ応用範囲がかぎられてくる。ちなみに、
多結晶シリコンを用いた場合のＮチャンネルトランジス
タにおいて６０〜４０ ｃｍ／Ｖ”□ｅ
の移動度であり、Ｐチャンネルトランジスタでは、、：
１０〜２０備／ｖｌである６□
従来の構造について第１図１〜第３図に例を挙げて以下
に説明する。Furthermore, because of its low mobility, it is unsuitable for circuits that require speed, and its range of applications is limited. By the way,
The mobility in N-channel transistors using polycrystalline silicon is 60 to 40 cm/V"□e, and in the case of P-channel transistors, it is 10 to 20 cm/vl. An example will be described below with reference to FIGS. 1 to 3.
第１図に示すように石英ガラス基体１の上に、気相成長
５ｔｏｚ［２を形成し、その上にＰ型多結晶シリコン層
６を形成し選択的にエツチングする。As shown in FIG. 1, a layer 5TOZ[2 of vapor phase growth is formed on a quartz glass substrate 1, and a P-type polycrystalline silicon layer 6 is formed thereon and selectively etched.
その上に、熱酸化５ｉ０２ ｔ１ｇ４を形成して、ゲ
ート電極配ａＳを形成する。第２図に示すように、イ
′オン打込みに１９Ｎ＋拡散層６を形成し、その上にリ
ンシリケイトガラス７を形成する。又、第５図のように
選択エツチングにｘＤコンタクトホールをあけ、その上
にＭ配ｆｉｌ ８を形成する。Thereon, thermal oxidation 5i02 t1g4 is formed to form gate electrode arrangement aS. As shown in Figure 2,
'A 19N+ diffusion layer 6 is formed on the on-implant, and a phosphosilicate glass 7 is formed thereon. Further, as shown in FIG. 5, an xD contact hole is formed by selective etching, and an M film 8 is formed thereon.
以上のような構造をとると、前記したように気相成長５
ｉ０２ と多結晶シリコンの界面、及び多結晶中の粒
塊の界面を流れるリークが発生し、さらに光があたると
電荷が発生してリークする。特に液晶表示パネルの電極
基板に用いた場合には元が石英ガラス基体側から直接あ
たるのでリーク電流も非常に多く ｆＵｌ’る。さらに
前記したように移動度が小さく、内部１寥シフトレジス
タ等のスピードが要求される回Ｊ・を内蔵すｌができヶ
い。When the above structure is adopted, as mentioned above, vapor phase growth 5
Leakage occurs at the interface between i02 and polycrystalline silicon, and at the interface between grains in the polycrystalline silicon, and when exposed to light, charges are generated and leakage occurs. In particular, when used as an electrode substrate for a liquid crystal display panel, the leakage current is very large because the source is directly in contact with the quartz glass substrate side. Furthermore, as mentioned above, it is difficult to incorporate circuits J. which have low mobility and require high speed, such as an internal one-bit shift register.
本発明は以上のＬ５な欠点について改良を加え・
またものであり、本発明の目的はトランジスタの能力を
アップする事にあシ、本発明の他の目的は、光によるリ
ーク電流を少くする孕にある。又、さらに本発明の他の
目的については、以下の本発明の説明の中であきらかに
する。The present invention improves the above-mentioned L5 drawbacks.
Another object of the present invention is to improve the performance of a transistor, and another object of the present invention is to reduce leakage current due to light. Furthermore, other objects of the present invention will be made clear in the following description of the present invention.
第４図〜第６図に例を挙げて以下に本発明について説明
する。The present invention will be described below with examples shown in FIGS. 4 to 6.
第４図に示すように石英ガラス基体１１の上に、気相成
長５ｉＱ２１２を形成し、その上に下部ゲート電極１５
を形成する。その上に気相成長５１ｏ２１ＪｊＫ１４を
形成し、Ｎ２アニールをおこなう。そしてＰ製条結晶シ
リコンＩＨ１５を形成し、選択エツチングした後、熱酸
化５１０２膜１６を形成する。その上に上部電極１７を
形成する。As shown in FIG. 4, a vapor phase growth layer 5iQ212 is formed on the quartz glass substrate 11, and a lower gate electrode 15 is formed on it.
form. A vapor phase growth layer 51o21JjK14 is formed thereon, and N2 annealing is performed. Then, after forming a P strip crystal silicon IH 15 and selectively etching it, a thermally oxidized 5102 film 16 is formed. An upper electrode 17 is formed thereon.
第５図に示すように、イオン打込みに工りＮ＋拡散層１
８を形成した後、リンシリケイトガラス１９を形成する
。As shown in Figure 5, the N+ diffusion layer 1 is
After forming 8, phosphosilicate glass 19 is formed.
さらに、第６図に示すように選択エツチングにニジコン
タクトホールｔ６け、その上にＭ配線２０を形成する。Further, as shown in FIG. 6, a rainbow contact hole t6 is formed by selective etching, and an M wiring 20 is formed thereon.
なお必要であれば、下部ゲート電極と上部ゲート電極は
途中工程で接続し短絡する。If necessary, the lower gate electrode and the upper gate electrode are connected and short-circuited during the process.
以上のように本発明の方法によると、上部ゲート電極と
下部ゲート電極で電圧を同時に加え上部と下部から反転
層を形成して、上部、下部の反転層で電流を流す事ばで
き、父上部と下部から電圧を加える事によって相乗効果
も期待する事ができるＯ
さらに、上部ゲート電極と下部ゲート電極に不透明な電
極材料を用いる事によって、上下両方向からの光を遮断
する事ができリーク電流が少なくなる。なお、下部にも
ゲート電極がめシ、下部からも空乏層が発生している事
もあシ、下部絶縁膜と薄嘆牛導体層との界面でのリーク
も少なくなる。As described above, according to the method of the present invention, voltage can be simultaneously applied to the upper gate electrode and the lower gate electrode to form an inversion layer from the upper and lower parts, and a current can be passed through the upper and lower inversion layers. A synergistic effect can also be expected by applying voltage from below.Furthermore, by using opaque electrode materials for the upper and lower gate electrodes, it is possible to block light from both the upper and lower directions, reducing leakage current. It becomes less. In addition, a gate electrode is formed at the bottom, and a depletion layer is also generated from the bottom, and leakage at the interface between the bottom insulating film and the thin conductor layer is also reduced.
又、上部ゲート電極と上部ゲート電極とを短絡しないで
、別の電極として用いると２人力で１出力のトランジス
タを形成する事ができる。Furthermore, if the upper gate electrode and the upper gate electrode are not short-circuited but are used as separate electrodes, a single-output transistor can be formed by two people.
なお、本発明は上下とも金補ゲート電極でも、両者とも
多結晶又はアモル／・スの工うな半透明な電極、父、そ
の両者を用いた場合でもおのおの本・発明のそれぞれの
効果を発揮する事ができる。In addition, the present invention exhibits the respective effects of the present invention even when both the upper and lower gate electrodes are made of gold, both are semi-transparent electrodes such as polycrystalline or amorphous/silicon, or both are used. I can do things.
又、基体として石英ガラス板を用いた例を下したが、他
のガラス材料、グラスチック材料、セラミック材料及び
その他の材料を用いた場合でも同様である。Further, although the example has been given in which a quartz glass plate is used as the substrate, the same applies to cases where other glass materials, plastic materials, ceramic materials, and other materials are used.
又、ゲート材料としぞ気相成長のｓｉｏ、 ＰＩｉ＋と
熱酸化Ｓ ｉ Ｑ２ 膜について下したが他の材料を
用いた場合も同様である。又、本発明の例ではＮチャン
ネルについて示したがＰチャンネル、及び相補型でも同
様である。Further, although the above description has been made regarding the gate material, sio, PIi+, and thermally oxidized Si Q2 film grown in the groove vapor phase, the same applies to the case where other materials are used. Further, although the example of the present invention is shown for N channel, the same applies to P channel and complementary type.
第１図〜第３図は従来方法による製造工程順の断面略図
である。
第４図〜第６図は本発明の方法による製造工程順の断面
略図である。
以下、次の通りである。 ：
１、．１１・・・石英ガラス基体）、
２．１２．１４・・・気相成長のＳ ｉ ０２膜、６．
１５・・・Ｐ型多結晶シリコン層、４．１６・・・熱酸
化５１０２膜、
５・・・ゲート電極配線、
６．１８・・・Ｎ＋拡散層、
７．１？・・・リンシリケイトガラス、８．２０・・・
Ｍ配線。
１６・・・下部ゲート電極配線、
１７・・・上部ゲートＮ極配線、
以 上
出願人 株式会社 諏訪精工台
代理人 弁理士 最 上 務1 to 3 are schematic cross-sectional views of the manufacturing process according to the conventional method. 4 to 6 are schematic cross-sectional views of the manufacturing process according to the method of the present invention. The following is as follows. : 1,. 11... quartz glass substrate), 2.12.14... vapor phase grown S i 02 film, 6.
15... P-type polycrystalline silicon layer, 4.16... Thermal oxidation 5102 film, 5... Gate electrode wiring, 6.18... N+ diffusion layer, 7.1? ...phosphosilicate glass, 8.20...
M wiring. 16...Lower gate electrode wiring, 17...Upper gate N-electrode wiring, Applicant Suwa Seikodai Co., Ltd. Patent attorney Mogami Tsutomu
Claims (2)
を基板として用いたＭＯ８型電界効果トランジスタを構
成要素とする半導体集積回路装置において、該基板の上
下に、絶縁ゲート膜をかいして上部ゲート電極、下部ゲ
ート電極を形成した事を特徴とする半導体集積回路装置
。・(1) In a semiconductor integrated circuit device whose component is an MO8 field effect transistor using an amorphous semiconductor or a polycrystalline semiconductor thin film as a substrate, an insulating gate film is provided above and below the substrate to form an upper gate electrode and a lower gate electrode. A semiconductor integrated circuit device characterized by forming a gate electrode.・
同電位になっている事を特徴とする特許請求の範囲第１
項記載の半導体集積回路装置。(2) Claim 1, characterized in that the upper gate electrode and the lower gate electrode are short-circuited and have the same potential.
The semiconductor integrated circuit device described in .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10153482A JPS58218169A (en) | 1982-06-14 | 1982-06-14 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10153482A JPS58218169A (en) | 1982-06-14 | 1982-06-14 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58218169A true JPS58218169A (en) | 1983-12-19 |
Family
ID=14303106
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10153482A Pending JPS58218169A (en) | 1982-06-14 | 1982-06-14 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58218169A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63308386A (en) * | 1987-01-30 | 1988-12-15 | Sony Corp | Semiconductor device and manufacture thereof |
| JPS6459866A (en) * | 1987-08-31 | 1989-03-07 | Sony Corp | Manufacture of mos transistor |
| US4998152A (en) * | 1988-03-22 | 1991-03-05 | International Business Machines Corporation | Thin film transistor |
| JPH0354865A (en) * | 1989-07-24 | 1991-03-08 | Sharp Corp | Thin film field effect transistor and manufacture thereof |
| US5061648A (en) * | 1985-10-04 | 1991-10-29 | Hosiden Electronics Co., Ltd. | Method of fabricating a thin-film transistor |
| EP0481734A2 (en) * | 1990-10-16 | 1992-04-22 | Agency Of Industrial Science And Technology | Light valve device |
| US5550390A (en) * | 1991-08-08 | 1996-08-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
| US5859444A (en) * | 1991-08-08 | 1999-01-12 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| US7078321B2 (en) * | 2000-06-19 | 2006-07-18 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
| US7122409B2 (en) | 1999-12-10 | 2006-10-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and a method of manufacturing the same |
| US9799731B2 (en) | 2013-06-24 | 2017-10-24 | Ideal Power, Inc. | Multi-level inverters using sequenced drive of double-base bidirectional bipolar transistors |
-
1982
- 1982-06-14 JP JP10153482A patent/JPS58218169A/en active Pending
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5061648A (en) * | 1985-10-04 | 1991-10-29 | Hosiden Electronics Co., Ltd. | Method of fabricating a thin-film transistor |
| JPS63308386A (en) * | 1987-01-30 | 1988-12-15 | Sony Corp | Semiconductor device and manufacture thereof |
| JPS6459866A (en) * | 1987-08-31 | 1989-03-07 | Sony Corp | Manufacture of mos transistor |
| US4998152A (en) * | 1988-03-22 | 1991-03-05 | International Business Machines Corporation | Thin film transistor |
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