JPS58147247A - Pulse code transmission system - Google Patents

Pulse code transmission system

Info

Publication number
JPS58147247A
JPS58147247A JP2904182A JP2904182A JPS58147247A JP S58147247 A JPS58147247 A JP S58147247A JP 2904182 A JP2904182 A JP 2904182A JP 2904182 A JP2904182 A JP 2904182A JP S58147247 A JPS58147247 A JP S58147247A
Authority
JP
Japan
Prior art keywords
data
commercial
circuit
power line
frequency signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2904182A
Other languages
Japanese (ja)
Inventor
Yutaka Mizuno
豊 水野
Hanzo Tsuzuki
伴三 都築
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP2904182A priority Critical patent/JPS58147247A/en
Priority to GB08302771A priority patent/GB2116406B/en
Priority to DE19833305717 priority patent/DE3305717C2/en
Publication of JPS58147247A publication Critical patent/JPS58147247A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B3/00Line transmission systems
    • H04B3/54Systems for transmission via power distribution lines
    • H04B3/542Systems for transmission via power distribution lines the information being in digital form
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/02Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B2203/00Indexing scheme relating to line transmission systems
    • H04B2203/54Aspects of powerline communications not already covered by H04B3/54 and its subgroups
    • H04B2203/5404Methods of transmitting or receiving signals via power distribution lines
    • H04B2203/5416Methods of transmitting or receiving signals via power distribution lines by adding signals to the wave form of the power source
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B2203/00Indexing scheme relating to line transmission systems
    • H04B2203/54Aspects of powerline communications not already covered by H04B3/54 and its subgroups
    • H04B2203/5429Applications for powerline communications
    • H04B2203/5445Local network
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B2203/00Indexing scheme relating to line transmission systems
    • H04B2203/54Aspects of powerline communications not already covered by H04B3/54 and its subgroups
    • H04B2203/5462Systems for power line communications
    • H04B2203/5483Systems for power line communications using coupling circuits

Abstract

PURPOSE:To transmits binary-coded serial data through a commercial AC power line by turning on and off a switching circuit according to the binary-coded serial transmitted data, and superposing a high frequency signal which is outputted from an oscillating circuit during turn-on operation upon an AC voltage. CONSTITUTION:Respective electronic registers 1a-1c are connected electrically to the commercial AC power line L by connecting corresponding plugs 2a-2c to outlets 3a-3c. Similarly, a host computer is also connected electrically to the commercial AC power line L. Then, the electronic registers 1a-1c and the host computer interchange data through the commercial AC power line L.

Description

【発明の詳細な説明】 この発明は、データをパルス符号化して他の電子機器へ
伝送するパルス符号伝送方式に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse code transmission method for pulse-encoding data and transmitting it to other electronic equipment.

従来、イン、フィン方式でパルス符号化されたデータの
伝送を行うためには、電子機器相互を2!Iあるいは3
11式のケーブルで接続する必要があった。たとえば、
複数台の電子レジスタとホスシコンピユータ(図示せず
)との間では第21!3に示す配線が行なわ些る。すな
わち、各電子レジスタ1aslbslaは夫々対応して
接続されたプラグ2&、 2 bs 2 Gが商用交流
電力線りに接続されたコンセント31L13bs3cに
電気的に接続されて電力の供給を受ける。他方〜電子レ
ジスタ1m、1bxloはこれらが1&重された店の天
井内匈に設けられた分配器4にデータ伝送用のケーブル
lいl意、1mを介して接続され、さらにケーブル!。
Conventionally, in order to transmit pulse-encoded data using the in-fin method, two electronic devices must be connected to each other. I or 3
It was necessary to connect with Type 11 cable. for example,
The wiring shown in No. 21!3 is performed between the plurality of electronic registers and the host computer (not shown). That is, each electronic register 1aslbsla is electrically connected to an outlet 31L13bs3c connected to a commercial AC power line through the correspondingly connected plugs 2&, 2bs2G, and receives power supply. On the other hand, the electronic registers 1m and 1bxlo are connected to a distributor 4 installed in the ceiling of the store where they are stacked, via a 1m cable for data transmission, and further cables! .

を介して分配器4と前記ホストコンピュータとが接続さ
れる。そして、各電子レジX 貞1 a s 1bsl
oと本ストコン(ユータとの間で分配器4を介してデー
タの授受が行なわれる。
The distributor 4 and the host computer are connected via. And each electronic cash register
Data is exchanged between O and the main storage computer (user) via the distributor 4.

曹u述のように、電子レジスタのデータ伝送を行なうた
めには、伝送用に専用のケーブル!、〜l、の配線工◆
を行なう必要があり、工**、W料費など多くの出費を
必要とする欠点があった。また、配線工事は一定の工事
期間を必要とするから、その期間だけ電子レジスタのイ
ンラインシステムの稼動が遅れる欠点があった。
As mentioned by Cao Yu, in order to transmit data from electronic registers, a dedicated cable is required for transmission! ,~l, wiring worker◆
This has the drawback of requiring a lot of expense such as engineering** and W fees. Furthermore, since the wiring work requires a certain period of time, there is a drawback that the operation of the in-line electronic cash register system is delayed during that period.

この発明は前記◆惰に基づいてなされたもので1その目
的とするところは、商用交流電力叡を利用して2進化直
列のデータを伝送するようにしたパ羨ス符号伝送方式を
提供することである。
This invention has been made based on the above-mentioned ◆Information 1.The purpose of this invention is to provide a path-pass code transmission system that transmits binary coded serial data using commercial AC power. It is.

以下、この発明の一実施例につき第2Itないし第4I
tに基づいて説明する。第2図は前述した電子レジスタ
1&% t b% 1・とホストコンビ具−タ(v!J
示せず)との間でデータ伝送を行なう場合のインライン
システムを示し、各電子レジスタ1a N1・は夫々対
応するプラグ2&〜2cをコンセント31〜3・に接続
することにより商用交流電力@Lに電気的に接続される
。同様に、前記ホスFコンピュータも前記商用交流電力
@Lと電気的に接続される。そして、電子レジスタ11
〜10と前記ホストコンビエータは商用交流電力IIL
を介して電力の供給を受けると共に、商用交流電力@L
を介してデータの授受が行なわれる。
Hereinafter, 2nd It to 4th I for one embodiment of the present invention will be described.
The explanation will be based on t. Figure 2 shows the electronic register 1&%t b% 1.
(not shown), each electronic register 1a N1. connected. Similarly, the host F computer is also electrically connected to the commercial AC power @L. And electronic register 11
~10 and the host combinator is powered by commercial AC power IIL.
In addition to receiving power supply via commercial AC power @L
Data is exchanged via the .

第3図は前記電子レジスタ1&〜1cの概略システム構
成図を示し、前記商用交流電力!ILからの電圧は対応
するプラグ及び電源コード3gを介して変圧@11の1
次側コイルに印加され、2次個コイルからの減圧された
電圧は安定化電ma路れた電圧を一定の直施亀圧値に保
持し、点纏左備に示す電子レジスタ内の各回路に電力を
供給する・符号17はCPUで、このCPU17には入
力部18に備えられた各種キーの操作信号が人力され、
入力されたキーコードに従った処理を行なう。また、C
PU17は表示部19へ表示データを、印字部20へ印
字データを夫々出力し、表示部19、印字s20におい
て夫々表示、印字が行なわれる。
FIG. 3 shows a schematic system configuration diagram of the electronic registers 1&~1c, and shows the commercial AC power! The voltage from IL is transformed via the corresponding plug and power cord 3g @ 1 of 1
The reduced voltage from the secondary coil is applied to the secondary coil, and the voltage applied to the stabilizing current is maintained at a constant direct pressure value.・Reference numeral 17 is a CPU, to which operation signals from various keys provided in the input section 18 are inputted manually.
Performs processing according to the input key code. Also, C
The PU 17 outputs display data to the display section 19 and print data to the printing section 20, and display and printing are performed on the display section 19 and printing s20, respectively.

また、CPU17は記憶部21との間においてデータの
授受を行ない、所要のデータを記憶部21へ書き込む。
The CPU 17 also exchanges data with the storage section 21 and writes required data to the storage section 21 .

このはかCPU17はデータバッファ22ヘオベレーシ
璽ンデータおよび送信データを送出し、データバスバッ
ファ22内の受信データを読み出す。データバスバッフ
ァ22に薔き込まれたオペレージ曹ンデータはコントロ
ールレジスタ23へ、送信データは送信データレジスタ
24へ夫々転送され、さらに送信データレジスタ24内
の送信データは並−直変換回路25へ入力される。また
後述する波形整形111ifI33から出力された2進
化直列データは直−着変換回路26へ入力され、並列デ
ータに変換された後に餐養寺−七詐受信データレジスタ
34へ記憶される。この受信データレジスタ34内の受
信データはデータバスバッファ22を介してCPU17
へ読み込まれる。前記コントロールレジスタ23は書き
込まレタオベレーシ曹ンデータに従って1並−直変換回
路2sを指定する指定信号CJi l、あるいは直−並
毅換回路26を指定する指定信号C畠■を夫々出力する
。並−直変換回路25は指定信号cmIが入力されてい
る閾、入力された並列の送信デーVを直列データに変換
して2進化直列の送信データを出力する。
This CPU 17 sends out the transmission data and transmission data to the data buffer 22, and reads out the received data in the data bus buffer 22. The operating data stored in the data bus buffer 22 is transferred to the control register 23, the transmission data is transferred to the transmission data register 24, and the transmission data in the transmission data register 24 is input to the parallel-to-serial conversion circuit 25. Ru. Further, the binary coded serial data outputted from the waveform shaping 111ifI33, which will be described later, is input to the direct-to-end conversion circuit 26, converted to parallel data, and then stored in the Nanyoji-Nanaho reception data register 34. The received data in the received data register 34 is sent to the CPU 17 via the data bus buffer 22.
is loaded into. The control register 23 outputs a designation signal CJil for designating the parallel-to-direct conversion circuit 2s or a designation signal CHat for designating the direct-to-parallel conversion circuit 26 in accordance with the written retardation data. The parallel-to-serial conversion circuit 25 converts the input parallel transmission data V into serial data based on the threshold to which the designation signal cmI is input, and outputs binary coded serial transmission data.

また、符828は発振回路で、この発振回路2$かも出
力される高周波信号は増幅回路29へ出力され、ここで
増幅された高周波信号はスイッチング細路27へ出力さ
れる。スイッチング細路27はたとえばトランジスタに
よって構成され、このゲートに前記並−直変換回路2s
から2進化直列信号が入力される。したがって、このス
イッチング回路27は、前記2進化直列信号の“1“、
0′″に応じて“ON“、“OFF”″動作を行う。
Further, reference numeral 828 is an oscillation circuit, and the high frequency signal outputted from this oscillation circuit 2$ is also outputted to the amplifier circuit 29, and the high frequency signal amplified here is outputted to the switching path 27. The switching path 27 is constituted by a transistor, for example, and the parallel-to-direction conversion circuit 2s is connected to the gate of the transistor.
A binary coded serial signal is input from. Therefore, this switching circuit 27 can switch between "1" and "1" of the binary serial signal.
"ON" and "OFF" operations are performed depending on the signal 0'.

スイッチング細路27の出力備は切換回路16に接続さ
れる。この切換回路16は、たとえばトランジスタ、リ
レーなどのスイッチング手段で構成され、前記コントリ
ールレジスタ23からの切換信号C8Wに応じて、送受
信の切換を行なう。送信時には端子16a、16bが接
続状態となる。
The output of the switching path 27 is connected to the switching circuit 16. This switching circuit 16 is composed of switching means such as a transistor or a relay, and switches between transmission and reception in response to a switching signal C8W from the control register 23. During transmission, the terminals 16a and 16b are in a connected state.

端子16mは変圧1113$02次側巻線の一端へ接続
され、2次側巻線の他端は接地される。変圧器15の1
次側巻線にはコンデンサ13.14が直列に接続され、
更に前記電源コード35に接続される。
Terminal 16m is connected to one end of the transformer 1113$0 secondary winding, and the other end of the secondary winding is grounded. Transformer 15-1
Capacitors 13 and 14 are connected in series to the next winding,
Furthermore, it is connected to the power cord 35.

一方、変圧器1Bの2次側コイルを介して入力される受
信信号、すなわち、商用の低層波信号に高周波信号が重
畳された信号は切換回路16の端子16a、16・を夫
々介してフィルタ回路30に入力される。このフィルタ
回路30は廟用低周波信号を除去して前記高周波信号を
通過させて増幅回路31へ出力する。増幅回路31は入
力された高周波信号を増幅して整流回路32へ出力し、
ここで増−された高周波信号は一定電圧値の矩形信号と
して波形整形回路33に出力される。波形整形回路33
は入力された矩形信号を波形整形し、2進化直列の受信
データを前記直−並変換回路26へ出力する。
On the other hand, the received signal input through the secondary coil of the transformer 1B, that is, the signal in which a high frequency signal is superimposed on a commercial low layer wave signal, is passed through the filter circuit through the terminals 16a and 16 of the switching circuit 16, respectively. 30 is input. The filter circuit 30 removes the low frequency signal for the shrine, passes the high frequency signal, and outputs it to the amplifier circuit 31. The amplifier circuit 31 amplifies the input high frequency signal and outputs it to the rectifier circuit 32.
The high frequency signal increased here is outputted to the waveform shaping circuit 33 as a rectangular signal with a constant voltage value. Waveform shaping circuit 33
waveform-shapes the input rectangular signal and outputs the binary-coded serial received data to the serial-parallel conversion circuit 26.

次に、この発明の動作について説明する。まず、前記電
子レンジl&〜10のプラグ2&〜2Cを商用交流電力
IiLのコンセント3&〜3嗜へ接続すると、商用交流
電圧が変圧器11、安定化電源回路12を夫A介してレ
ジスタ内部の各回路に供給される。この状態で、商用交
流電力線りに接続された前記本スジコンビエータにデー
タを過信スるものとする。すなわち、CPU17かもデ
ータバスバッフ722ヘオペレーシ曹ンデータが出力サ
レ、このデータはコントルールレジスタ23へ書き込ま
れる。そして、コントレールレジスタ23からの切換信
号が切換剛結16に対して出力されて端子16&と端子
16’bとが電気的に接続されて送信麹に切り換えら、
q直1回路2Sを指定する指定信号C8Iが出力され、
この結果、電子レジスタlaが送信状態へ設定される。
Next, the operation of this invention will be explained. First, when the plugs 2&~2C of the microwave oven l&~10 are connected to the outlets 3&~3 of the commercial AC power IiL, the commercial AC voltage is applied to each of the registers inside the register via the transformer 11 and the stabilized power supply circuit 12. Supplied to the circuit. In this state, it is assumed that data is transmitted to the main line combinator connected to the commercial AC power line. That is, the CPU 17 also outputs the operation data to the data bus buffer 722, and this data is written to the control register 23. Then, the switching signal from the control register 23 is outputted to the switching rigid connection 16, and the terminals 16& and 16'b are electrically connected and switched to the transmitting koji.
A designation signal C8I designating the q direct 1 circuit 2S is output,
As a result, electronic register la is set to the transmitting state.

次に、CPU17から所定ビット分の並列の送信データ
が出力され、この送信データはデータバスバッファ22
、送信データレジスタ24を夫々介して並−直変換回路
25へ人力される・並−直変換回路25は人力された並
列の送信データを第4図(2)に示すように2進化直列
の送信データとして順次スイッチング−路27に対して
出力する。すると、スイッチング1路27は入力された
送信データが1“状態の期間だけでスイッチを導通する
から、この導通状態の間、発振回路28から出力された
高周波信号は増−回路29、スイッチング回路27を夫
庸介し、j14図俤)に示すように切換回路16へ送出
される・さらに、切換回路16の端子16klq16m
を夫々介した前記高周波信号は変圧器ISの2次個コイ
ルへ印加される。ところで、変圧器15には第4図C)
に示すように商用交流電圧が印加されているため、この
商用交流電圧に前記スイッチング−路27を通過した高
周波g!号がj14[))に示すようにコンデンf13
.14を介して順次重畳され、この重畳された高周波信
号が電源コード35、ブラダ、商用交流電力f7g L
を夫々介し、ホストコンビエータへ送出される。
Next, parallel transmission data for predetermined bits is output from the CPU 17, and this transmission data is transferred to the data bus buffer 22.
, and are manually input to the parallel-to-serial conversion circuit 25 via the transmission data register 24.The parallel-to-serial conversion circuit 25 converts the manually input parallel transmission data into a binary coded-serial transmission as shown in FIG. 4(2). The data is sequentially outputted to the switching path 27. Then, since the switching 1 path 27 conducts the switch only when the input transmission data is in the 1'' state, during this conductive state, the high frequency signal output from the oscillation circuit 28 is transmitted to the amplifier circuit 29 and the switching circuit 27. is sent to the switching circuit 16 via the terminal 16klq16m of the switching circuit 16 as shown in Fig.
The high frequency signals are applied to the secondary coils of the transformer IS. By the way, the transformer 15 is shown in Fig. 4C)
Since a commercial AC voltage is applied as shown in FIG. 2, the high frequency g! Condensation f13 as shown in j14 [))
.. 14, and this superimposed high frequency signal is sent to the power cord 35, the bladder, and the commercial AC power f7gL.
are sent to the host combiator via the respective host combinators.

次に、ホストコンビエータからtiM交流’IK力線り
を介して送られてくる第4WI(ロ)に示すような送信
信号を受信する場合について説明する。この場合、CP
U17かも出力されるオペレージ璽ンデータがデータバ
スバッファ22、コント胃−ルレジスタ23を夫庸介し
、切換回路l・の端子16島を端子16・側へ切り換え
ると共に1直−並変換ii路2藝を指定する。この結果
、商用交流電力11Lを介して入力する高周波信号が重
畳された商用交流電圧がコンデン?13.14、変圧器
1!。
Next, a case will be described in which a transmission signal as shown in the fourth WI (b) sent from the host combinator via the tiM AC'IK line of force is received. In this case, C.P.
The operation data outputted from U17 passes through the data bus buffer 22 and the control register 23, and switches the terminal 16 of the switching circuit l to the terminal 16 side, and also performs the 1 straight-to-parallel conversion path 2. specify. As a result, the commercial AC voltage on which the high frequency signal inputted via the commercial AC power 11L is superimposed is converted to a capacitor. 13.14, Transformer 1! .

切換−路16を夫々介してフィルタ3・へ入力する。フ
ィルタ30は商用交流電圧を遮断して第41韓に示すよ
うに高周波信号を増幅回路31へ出力する。増−回路3
1はil+gF)に示すように入力された高周波fr1
号を増幅し、整流−路32へ出力する。整流回路32は
、増−された高周波信号を第4面切に示すように整流し
て波形整形回路33へ出力し、ここで同図頓に示すよう
に波形整形された信号が2進化直列の受信データとして
直−並変換回路26へ出力される。そして、受信データ
が一定量記憶されると、この記憶データは受信データレ
ジスタ34に送出され、さらに同データはデータバスバ
ッファ22を経てCPU17に入力され、所定の処理が
行なわれる。
The input to the filter 3 is via the respective switching path 16. The filter 30 cuts off the commercial AC voltage and outputs a high frequency signal to the amplifier circuit 31 as shown in the 41st line. Increase circuit 3
1 is the input high frequency fr1 as shown in il+gF)
The signal is amplified and output to the rectifier path 32. The rectifier circuit 32 rectifies the amplified high-frequency signal as shown in the fourth section and outputs it to the waveform shaping circuit 33, where the waveform-shaped signal is converted into a binary series signal as shown in the diagram. It is output to the serial-parallel conversion circuit 26 as received data. When a certain amount of received data is stored, this stored data is sent to the received data register 34, and further inputted to the CPU 17 via the data bus buffer 22, where predetermined processing is performed.

なお、前記実施例においてはこの発明を電子レジスタに
適用したが、これに限らず、ディジタルデータの伝送に
使用する電子機器に適用可能である0 以上説明したようにこの発明によれば、2進化直列の送
信データに従ってスイッチング回路を導通・遮断し、導
通時に発振囲路から出力される高周波信号を商用電力線
の交流電圧に重畳するようにしたから、商用交流電力線
を利用して2進化直列のデータを伝送することができる
。したがって、他の電子機器へデータを送信する場合に
も、特に配線工事を施す必要はないから、工事費、材料
費などを節約することができる利点がある。また、電子
機器の設置と同時にデータの送信が可能となる利点があ
る。
In the above embodiments, the present invention is applied to an electronic register, but the present invention is not limited to this and can be applied to electronic equipment used for transmitting digital data. The switching circuit is turned on and off according to the serial transmission data, and the high-frequency signal output from the oscillation circuit when conduction is superimposed on the AC voltage of the commercial power line. Therefore, the binary series data can be transmitted using the commercial AC power line. can be transmitted. Therefore, even when transmitting data to other electronic devices, there is no need for special wiring work, so there is an advantage that construction costs, material costs, etc. can be saved. Another advantage is that data can be transmitted at the same time as electronic equipment is installed.

【図面の簡単な説明】[Brief explanation of the drawing]

亀1図は従来の電子レジスタのインラインシステムの配
線状態図、J112図はこの発明のインラインシステム
の配線状m図、#I3図はこの発明の概略シスデム構威
図、114図体)〜(ロ)は動作を説明するための出力
波形図である。 l&〜lo・・・・・・電子レジスタ、16・・・・・
・切換回路、27・・・・・・スイッチング回路、L・
・・・・・商用交流゛電力線。 特許出願人 カシオ計算機株式会社
Figure 1 is a wiring state diagram of the in-line system of a conventional electronic register, Figure J112 is a wiring diagram of the in-line system of this invention, and Figure #I3 is a schematic system configuration diagram of this invention. is an output waveform diagram for explaining the operation. l&~lo...Electronic register, 16...
・Switching circuit, 27...Switching circuit, L・
...Commercial AC power line. Patent applicant Casio Computer Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 高周波信号を出力する発振回路と、2進化直列の送信デ
ータに従って導通・遮断し、導通時に前記発振回路から
の高周波信号を送出するスイッチング回路と、このスイ
ッチング回路から出力される為周波信号を商−用交流電
力線の交流電圧に重畳する手段とを備えてなるパルス符
号伝送方式。
An oscillation circuit that outputs a high frequency signal, a switching circuit that conducts and cuts off according to binary series transmission data and sends out a high frequency signal from the oscillation circuit when conductive, and a switching circuit that converts the frequency signal to be output from this switching circuit. A pulse code transmission method comprising means for superimposing the AC voltage on an AC power line for use.
JP2904182A 1982-02-26 1982-02-26 Pulse code transmission system Pending JPS58147247A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2904182A JPS58147247A (en) 1982-02-26 1982-02-26 Pulse code transmission system
GB08302771A GB2116406B (en) 1982-02-26 1983-02-01 Pulse code-transmitting apparatus
DE19833305717 DE3305717C2 (en) 1982-02-26 1983-02-18 Pulse code transmission device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2904182A JPS58147247A (en) 1982-02-26 1982-02-26 Pulse code transmission system

Publications (1)

Publication Number Publication Date
JPS58147247A true JPS58147247A (en) 1983-09-02

Family

ID=12265308

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2904182A Pending JPS58147247A (en) 1982-02-26 1982-02-26 Pulse code transmission system

Country Status (3)

Country Link
JP (1) JPS58147247A (en)
DE (1) DE3305717C2 (en)
GB (1) GB2116406B (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2151116A (en) * 1983-12-07 1985-07-10 Lamont David Gordon Signalling over power lines
US4583232A (en) * 1984-02-08 1986-04-15 General Electric Company Carrier current digital data transceiver
DE3581150D1 (en) * 1984-08-27 1991-02-07 Zellweger Uster Ag METHOD FOR SENDING DATA OVER THE LINE OF AN AC DISTRIBUTION NETWORK AND TRANSMITTER FOR IMPLEMENTING THE METHOD.
FR2570235B1 (en) * 1984-09-07 1989-07-28 Trt Telecom Radio Electr MONOLITHIC ANALOGUE INTERFACE CIRCUIT BETWEEN A SIGNAL PROCESSOR AND A TELECOMMUNICATION NETWORK
DE4436090A1 (en) * 1994-10-10 1996-04-18 Klaus Meeners Diagnostic, maintenance and identification unit for electronic devices
DE29700787U1 (en) * 1997-01-17 1998-02-19 Philipp Dieter Dr Order terminal for restaurant guests with bidirectional connection to a cash register terminal via the 230 V energy network
WO2000007304A2 (en) * 1998-07-27 2000-02-10 Siemens Aktiengesellschaft Electric power supply with a device for coupling data signals to a mains supply
KR100446931B1 (en) * 2002-04-30 2004-09-04 주식회사 두노시스템 Adapter for using Power Line Communication
US9065544B2 (en) * 2012-09-28 2015-06-23 Osram Sylvania Inc. Pulse-based binary communication

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2064923B (en) * 1979-10-31 1984-02-08 Matsushita Electric Works Ltd Data transmission system utilising power line

Also Published As

Publication number Publication date
GB8302771D0 (en) 1983-03-02
GB2116406A (en) 1983-09-21
DE3305717A1 (en) 1983-09-15
GB2116406B (en) 1985-11-27
DE3305717C2 (en) 1986-09-11

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