JPS58147209A - Amplifying circuit - Google Patents

Abstract

PURPOSE:To perform high-speed operation by connecting the input and output terminals of an inverter mutually through an MOS switch, and applying a bias voltage which has a value between a power voltage and a reference voltage to the back gate electrode in the MOSFET in the MOS switch. CONSTITUTION:A P channel MOSFET11 and an N channel MOSFET12 constitute a C-MOS inverter 13; the input and output terminals of the inverter 13 are connected mutually through an N channel MOSFET14 and a coupling capacitor 16 is provided on the input side of the inverter 13. An input signal IN is supplied to the gate of the FET14 and an output signal OUT is outputted from the inverter 13. To the gate of the FET14, a signal S is supplied to perform switch control. Further, a P channel MOSFET21 and an N channel MOSFET22 are connected in series between the power of voltage VDD and the ground of voltage VSS and the common connection point 23 of the drain is connected to the back gate electrode of the FET 14. Therefore, the bias voltage at the connection point 23 is made equal to the threshold voltage of the inverter 13 to obtain the amplifying circuit capable for high-speed operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement of an amplifier circuit used in a voltage comparator circuit called a so-called chillyd type or an autozero-sangert data type.

[Technical background of the invention and its problems] With the development of analog ICs such as integrated analog-to-digital conversion circuits, high performance voltage comparison circuits are required to be built into these ICs. There are three characteristics that are particularly required of this voltage comparison circuit: high-speed response, no offset, and high resolution, and these characteristics are interrelated.

FIG. 1 is a block diagram of a conventional amplifier circuit used in a transistor-type, para-type, or auto-zero sample r-type voltage comparator circuit configured with multiple MOS FETs. This amplifier circuit consists of a P channel MOS FET11 and an N f-w channel M.
An N-channel MOS FE is connected between the input end and the output end of the C-MOS inverter eco consisting of O8FET 1
MOS FET switch using TJ4.

Connected by child circuit L1, and further connected to C-MOS inverter 13.
A coupling capacitor @16 is provided on the input end side. An input signal IN is supplied to the input terminal of each of the above 1jjk16, and the C-MO
An output signal OUT is output from the "S inverter L". In addition, the N f -w 4 MO8FET 14 constituting the above MO8FET switch circuit L
(D'f-to1imKU, this MOS FIT 1
A signal 8 for switch control of MOS FIT J 4 is supplied, and furthermore, a signal 8 for controlling the switch of MOS FIT J 4 is supplied.
The power supply voltage v supplied to this amplifier circuit is applied to the r-) electrode.
DD (positive polarity voltage), ground voltage V1. One of the (reference voltages) Pg is supplied. In an amplifier circuit with such a configuration, first, MOS FE
The control signal S supplied to the dart electrode of T J 4 is V□
This MOS FIT by being set to the level
14 is turned on. When MOS FET 14 is turned on, the input/output terminal voltage of 9C-MO8 imperter is set to its circuit threshold voltage, thereby
- The operating point of the MOS inverter eco is set.

Next, by setting the signal S to the vsg level, the MOS FICT 14 is turned off, and in this state, the input signal IN is amplified by the c-MOS inverter 13. Such an amplifier circuit has a simple circuit configuration. Moreover, since it is suitable for integration, it has a wide range of applications as a basic amplifier circuit. In addition, as an example of applying a voltage comparison circuit based on this principle to an analog-to-digital conversion circuit, an example is "Monolithic".
Expandak+1*6 Bit 20 MI(z
CMO8/ SO8~ΦConvert@r' AND
REW G.

F, DINGWALL, IEEE J, 5ol
id-8tats C1rcuit, volSC-1
4, pp. 926-932, D@c, 1979j.

The analog-to-digital conversion circuit described in the above document requires high-speed conversion characteristics, and therefore the operating speed of the amplifier circuit shown in FIG. 1, which is one of the circuit parts with the slowest operating speed, becomes a problem. It's coming. In other words, if you want to give the above analog-to-digital conversion circuit high-speed conversion characteristics, turn on the MO8FET switch in the expansion circuit and the sub circuit L1 until the operating point of the C-MOS inverter eco stabilizes. We need to shorten the time. . However, in the prior art, since the MO8FET switch 14 and the sub-circuit L' simply use the MOS FET 14 as a transfer gate, the ground voltage v,1 is supplied to the gate electrodes thereof. For this reason,
When the voltage of the input signal IN increases, the MOS FIT 1
This has the drawback that the on-resistance of the C-MOS input/output 13 becomes high, and therefore it takes a long time until the C-MOS input/output 13 is set to the operating point. Furthermore, since the threshold voltage of the MOS FET fluctuates due to the manufacturing process, in the prior art, when the threshold voltage fluctuates toward a high absolute value, the on-resistance of the MO8FET 14 also increases, and thus In this case as well, there is a drawback that it takes a long time until the C-MO8/parter 13 is set to the operating point.

By the way, other conventional techniques for eliminating queen defects include:
MOS F constituting the MOS FET switch circuit 15
In order to lower the on-resistance of ET J 4, efforts are being made to increase its channel width.

However, in the MOB FICT J 4 that constitutes the MO8FET switch circuit, a feed-through phenomenon of the control signal S to the source and drain via the parasitic capacitance generated between the gate electrode and the source and drain electrodes occurs. leakage occurs, which causes C-
MOS FET
Increasing the channel width of l4 also increases the value of the parasitic capacitance, which results in an increase in the offset voltage. Therefore, the conventional technique of increasing the channel width of MOS FET J4 impairs the offset-less characteristic, which is one of the most important characteristics of a CH/9 type or auto-zero sampled data type voltage comparison circuit. . Therefore, it is preferable that the channel width, that is, the element dimensions, of the MO8FET J4 used for this type of application be made as small as possible.

On the other hand, when the MO8FET 14 is actually manufactured with the element size minimized, when the control signal S supplied to the gate electrode has a level of 5Vo, the -on resistance reaches 10Ω to 100Ω. is normal, especially the above C-M
When the operating point voltage of "OSI/Parter" is about 2.5V, the on-resistance is high, and it is not uncommon for it to reach around 100Ω. Therefore, the MO8FET 1
If the element size of No. 4 is minimized, the time required to set the operating point is long, and high-speed operation cannot be achieved.

Furthermore, as mentioned above, the threshold voltage of MOS FET varies by ±o, av@ degree due to manufacturing process, and especially in the case of N-channel MOS FICT, as the threshold voltage increases, the above-mentioned on-resistance further increases. FIG. 3 is a characteristic diagram of input voltage (voltage supplied to a source electrode or drain electrode) versus on-resistance when a 560 vo voltage is supplied to the gate electrode of an N-channel MOSFET with φ. In FIG. 2, when the threshold voltage V, h=1, Ov, the input voltage is 2.
The on-resistance at 5V is approximately 28Ω, and when the input voltage is 2
．． When the threshold voltage vth is 5V, if the threshold voltage vth shifts by 0.3V toward the lower side, the on-resistance becomes 19Ω, and when it shifts by 0.3V toward the higher side, the on-resistance becomes 65Ω. That is, when the threshold voltage fluctuates in the same direction, it can be seen that the rate of increase in on-resistance is greater when the threshold voltage fluctuates higher than when it fluctuates lower.

[Purpose of the invention]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an amplifier circuit that can quickly set the operating point of an inverting amplifying means and thus can operate at high speed.

[Summary of the invention]

In the amplifier circuit according to the present invention, the input end and the output end of the C-MOS inverter are connected by a MOS FET switch circuit using an N-channel MOSFET, and a power supply voltage is applied to each gate electrode of the N-channel MOSFET. By providing a bias generation circuit that supplies a voltage having a value between
By lowering the apparent threshold voltage of the FET, the on-resistance in the MOS FET switch and switch circuits is kept low, and the operating point of the C-MOS inverter can be quickly set to enable high-speed operation. This is what I did.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be explained with reference to the drawings.

3C is a configuration diagram of a circuit according to an embodiment of the present invention, and in FIG. 0, parts corresponding to those of the conventional circuit in FIG.
A C-MOS inverter (inverting amplification means) 13 is configured with channel MOS FIT J 2, and an N-channel MOS FET is connected between the input terminal and output terminal of this inverter 1.
Connect with CMOS switch y f)14, and then connect with C-
A coupling capacitor 16 is provided on the input end side of the MOS inverter 13. An input signal IN is supplied to the input terminal of the capacitor 160, and an output signal OUT is output from the C-MO and inverter JJ. Further, a signal S for controlling the switch of this MOS FET 14 is supplied to the gate electrode of the N-channel MO8FET 14.

Furthermore, the power supply voltage vDD and ground voltage v0 applied to the C-MOS inverter 13 are connected to the KP channel MO8FET, ? between the respective application points. 1 and N channel MOS F
Connect the source and drain of ETJJ in series, and connect both FITs.
The common drain connection point of the bias voltage output terminal 23 is connected to the bias voltage output terminal 23 of the P-channel MO8.
The gate electrodes of FET 21 and N-channel MOS FET 22 are connected to form a noise generating circuit L1. Further, the bias voltage output terminal 23 of the bias generating circuit 1 is connected to the pass and cross electrodes of the N-channel MO8FET 14.

That is, in the embodiment circuit shown in FIG.
A bias voltage higher than the ground voltage 111 is always supplied from the ET 14's bias voltage generating circuit 111.

In the embodiment circuit having the above configuration, the bias generation circuit L'' has a circuit configuration in which the input and output terminals of a C-MOS inverter are short-circuited, so that the voltage at the bias voltage output terminal 23 is as follows (1 ) C-MO which can be expressed by the formula
The circuit threshold voltage vtheVC as an S inverter is equal.

Here, v, , : Threshold voltage of p-channel MO8FET J J
22C) Threshold voltage, and further, , KN are P-channel MO8FETjl and N-channel MOS
The drain current of FET 2 J is a coefficient of , and where, W, , wN:P? + channel MO8FET 21 and N channel MOS FET 22 valley channel width “p −L
v ” Channel length of P-channel MO8FET 21 and N-channel MOS FET 22 '@X ''
Gate insulating film thickness 1°X! Electrical constant μ2 of dirt insulating film. μN: Effective mobility of holes and electrons.

As is clear from the above equations (1) to (3), as the universal threshold voltage vthc5 as the CMO8 imper, that is, the voltage at the bias voltage output terminal 23 of the bias generation circuit 1, the P-channel MO8FET 2J and By setting the channel width and channel length of the N-channel MOS FET 22, a voltage having a value between vDD and v,llIO can be obtained. That is, a bias voltage of 111 or more is supplied to the negative electrodes of the N-channel MOS FET 14 as a MOS switch, and as a result, the apparent threshold voltage of this MOS FET 14 is lower than that of the conventional one. becomes, therefore,
The on-resistance of this MOS FET 14 can be made sufficiently lower than that of the conventional one.

By the way, considering only the on-resistance, the voltage supplied to the P and Kgut electrodes of MO8FET 14 is preferably higher, and can be set to the value of vDD itself, but on the other hand, a problem arises in terms of the 1p3* current. . This is M.O.
N-channel MO8FET used as B switch and switch
A PN junction is structurally generated between the 14 pack gate electrodes and each of the source and drain electrodes, with the pack gate electrode side serving as a P conductive lid layer.
If the amount of T14 (vDl) itself is supplied to the Kugut electrode, a current will always flow from the pack gate electrode to the source or drain electrode, resulting in extremely large current consumption.
The bias voltage supplied to the pack gate electrode of the N-channel MO8FET 14 is set to v
It is necessary to set the voltage to a value between DD and vsg.

Furthermore, when integrating the circuit shown in FIG. 3, the N-channel MO8FIST 14, which is the MO8 switch, and the N-channel MO8FET 22 in the bias generation circuit 1 are manufactured with the same process, so their respective threshold voltages are set to a predetermined value. It fluctuates in the same direction with respect to the threshold voltage. So, for example, if you are reluctant to use a high threshold voltage for MOS FET I4, then the MOS FET I4
The threshold voltage of z x also varies toward the higher side, as described in (1) above.
The bias voltage from the bias generation circuit 24 expressed by the equation increases. When the actual value voltage of MOS FET 14 is lowered, this MOS FET
The on-resistance of J4 is reduced.

On the other hand, contrary to the above, if the threshold voltage of MOS FET J4 fluctuates toward the lower side and its on-resistance becomes lower than a predetermined value (lower on-resistance is not desirable for an amplifier circuit) ), MOS FET
The threshold voltage of 22 also fluctuates in the lower direction, and the threshold voltage of (1
) The bias voltage from the bias generation circuit 1 expressed by the equation becomes low.

Therefore, in this case, the effective threshold voltage of MOS FET 14 is increased, so that this MOSFET
The on-resistance of J4 can be increased. That is, the bias voltage from the bias generation circuit L1 is applied to the MOS FIT J
By supplying 4 pack gate electrodes, the MOS
The on-resistance of FET 14 can almost always be kept close to a constant value, especially when the threshold voltage becomes high.
An increase in the on-resistance of the S FET 140 can be prevented.

FIG. 4 shows the MOS FET 14 in the above embodiment circuit.
FIG. 3 is a cross-sectional view showing a specific element structure of a bias generation circuit 110 portion. In the figure, a semiconductor substrate 101 of Nll
Two P well regions 102 and 103 are formed in one of the P well regions 102, and a MOS FIT 14 is formed in one of the P well regions 102.
A pair of N+ type regions 1041 serving as the source and drain of
05 and this P well region 102, that is, MOS FI
A P”ffi region 106 is provided for making contact with the P well region 103 of the CT 14. Furthermore, within the other P well region 103, a bias generating circuit 74 is provided.
The source of one of the MOS FETs JJ.

A p''m@ region 109 is provided to make contact with the P well region 10B of a pair of N+ micro regions xov and 1os, which will serve as the drain, and the substrate 101 is provided with the MOS FICT J
A pair of p"li* regions 110 that become the source and drain of J
．． 111 is provided.

A gate electrode 112 of MOS FET J 4 is provided across the pair of N+ type regions 104105, and signal 8 is supplied to this gate electrode 112. Further, the gate electrode 113 of the MOS FET 22 is provided over the pair of N + type regions 101108, and the dirt electrode 114 of the MOS FET 2 J is provided over the pair of P + type regions 110 and IJJ, respectively. Both dart electrodes 113 and 114 are connected to the bias voltage output terminal 23tf. Further, this output end 23 includes the Nm region 107 and the P+ type region 11.
0 is connected, and the output end 23 is connected to the p mm region 106. The P11 region 111 is connected to the power supply voltage V, an application point, and the N+ type region 08 and the P+ area reduction region 09 are connected to a ground voltage vas application point.

As in the case of the characteristic diagram shown in the above m2 diagram, FIG.
The ratio W/1° of the channel width W to the channel length of the N-channel MO8FET 14, which becomes 8 switch and 1, is set to 1 on the i screen, and the s and ovoi IE pressures are supplied to the dirt electrode, and the bias generation circuit is P-channel MO8FE in Ll
T 21 W/L on mask 6/42KSN channel MO8FIT J J W/I on mask 35/7
The bias voltage supplied to the electrodes of MOS FET 14 is approximately 1.2V-1.5.
FIG. 3 is a characteristic diagram of input voltage versus on-resistance when the voltage is set to V. FIG. As is clear from Figure 5, the input voltage or L5
v"t" MO8FIET 14 (15kQ when D threshold voltage vtk is 0.7V, 1.OV, 1.3VC1, respectively.

The on-resistance value is 18Ω and 25Ω. These values are 19Ω, 28Ω, and 65Ω in the case of Fig. 2 above.
The fact that it is significantly reduced compared to Ω is a sign of wear. Further, even if the threshold voltage of the MOS FIT 14 varies due to the manufacturing process, the variation in on-resistance is significantly improved compared to the conventional method. Also, this fifth
The on-resistance value in the figure is 1.2 when the bias voltage is 1.2.
In the case of V -1,5V, both P and N in the bias generation circuit 741 are
1, j JC) By changing the settings of the element dimensions, it can be increased to, for example, 2.0v to 2.5v. By increasing this bias voltage, the on-resistance of the MO8FET 140 can be further reduced, and the influence of variations in threshold voltage can be further reduced; however, as described above, The value of this bias voltage should be determined in consideration of current consumption.

FIGS. 6 to 8 each show other embodiments of the present invention, and are configuration diagrams of other examples of the bias generating circuits. In the case shown in FIG. 6, a constant current source circuit 31 is connected between the application point and the bias voltage output terminal 2J,
In addition, between the bias voltage output terminal 2S and the V□ application point, there is a resistor 32 and a drain of the same channel as the M08 FET J4, that is, an N-channel MOS FET ss.
, between the sources are connected in series, and further this MOS FET
J J gate electrode bias voltage output 31112B
It was designed to connect to. In the bias generation circuit having such a configuration, vDD and V are determined depending on the output current 11 of the constant current source circuit s1, the resistance value R of the resistor 32, and the element dimensions of the MO8FICT, respectively.

A bias voltage having a value of the function is output. Also, assuming that the resistor 32 does not exist in this circuit, the MOS
The threshold voltage of FICT s 3 is vthN33, No4
When the bias voltage is V, the following proportional equation holds true between vthss e vo.

IocK(vo-■ii,,)2 Song... Song... (4) K: Constant of proportionality In the above equation (4), as the threshold voltage vth of MOS FIT J j increases, the bias voltage V. Too expensive 9.
On the other hand, when vthss becomes low, V. It also shows that it is getting low. Therefore, even if the bias voltage from this bias generation circuit is used, the ON of the MOS FIT 14 will be affected by variations in threshold voltage due to the manufacturing process, as in the case of alternating the bias generation circuits in the circuit shown in FIG. The resistance tl can be made close to a constant value. In addition,
The resistor 32 is a bias voltage (■) that adds a certain voltage to the drain-source voltage of MEJ8 FET SJ.

It is designed to obtain.

In the circuit shown in FIG. 7, a load resistor 41 is connected between the vDD application point and the bias voltage output terminal 23, and a load resistor 41 of the same channel as the MO8FET J4 is connected between the bias voltage output terminal 23 and the V application point. That is, the drain and source of an N-channel MOS FET 42 are connected, and the gate electrode of this MOS FET 42 is connected to the bias voltage output terminal 23. In the bias 1 raw circuit with such a configuration, a, the resistance value of the load resistor 41 and the MOS FIT 4 J
(A bias voltage having a value between vDD and v81I according to the D element size is output. Also, in this circuit, the output bias voltage is V.', MOS F
Letting the threshold voltage of ET 4 J be ■th4□, it is V.

The following proportional expression holds between ' and vth4□.

K'=proportionality constant Equation (5) above is based on the threshold voltage vth4□ of MOS FET JJ and the Iasumi pressure V. Therefore, even if this circuit is used, the on-resistance of the MOS FET 14 can be kept close to a constant value even if the threshold voltage varies due to the manufacturing process. I can get away with it.

Incidentally, in any case of the bias generation circuit shown in FIG. 6 and #I7, the bias voltage output changes depending on the threshold voltage of the N-channel MOS FET 3B or 42. However, MOS F
If the on-resistance of IT J 4 simply needs to be lowered without considering the fluctuation of the threshold voltage, the 8th
A bias generation circuit as shown in the figure can also be used. That is, the circuit shown in FIG. 8 has a voltage between the vDD application point and V. Two resistors 51 and 52 are connected in series between the application point and the bias voltage output terminal 23, which is the series connection point, is connected to the bias voltage output terminal 23.
A constant bias voltage divided according to the resistance ratio of the resistors 51.5 and 2 is obtained. Therefore, the bias voltage obtained by this circuit is
14, by supplying it to the Kugut electrode 5, MO
The on-resistance of the S FET 14 can be set to a sufficiently lower value than in the conventional case.

FIG. 9 is a configuration diagram of an applied example circuit of the present invention. This circuit consists of a C-MOS inverter 61. for signal inversion and amplification. cs
N-channel MOS for setting the operating point by short-circuiting the input and output terminals of each of the input and output terminals of 2 and 63, respectively.
Amplifier circuit 1 consisting of FETs 54, 65, 6 g and coupling capacitances @61, 611.69, respectively;
72 and 73 are connected in cascade to form an amplifier circuit with a high overall power. In addition, among the above amplifier circuits, the MO in the first stage amplifier circuit L''
C-MOS is used for the S FET 64 electrode
Bias voltage V from a bias generation circuit 74 configured by short-circuiting the input and output terminals of an inverter. , and the pack r-) electrode of the MOB FET 65 in the intermediate stage amplifier circuit 72 receives a bias voltage from a bias generation circuit 75 which is also configured by shorting the input and output terminals of a C-MOS inverter. V02 is supplied, and the bias voltage from the bias generation circuit 16 configured by shorting the input and output terminals of the C-MOS inverter is supplied to the terminal electrodes of rDMO8FIT e a in the final stage amplifier circuit LJ. V.3 is supplied, and each C-MOS inverter 61, 62.63 and each bias generation circuit ?4.75
．． Even if the power supply voltage v0 supplied to 76 is ij5.
In the case of OV, the above bias voltage ■01 # v021
2.0V to 2.5V as v03.

1.5 V ~2. OV, 1.2V ~ 1.5V
21)! Each bias generation circuit 7
The element size ratio within /4,715°26 is set. Note that the control signal 8 is commonly supplied to the gate electrodes of the MO8FICTs 64, 65, and 66. In a circuit configured like this, the amplifier circuit on the side closer to the input signal IN handles a signal with a much lower voltage, so the on-resistance value of the MOS FET for setting the operating point is reduced accordingly to increase the operating speed. There is a need. Therefore, by supplying the highest bias voltage to the 0MO8FIT 64 electrodes in the first stage amplifier circuit 71, which is close to the input signal IN, a voltage comparator circuit that is fast and has offset-less characteristics is constructed as a whole. This is a possible amplifier circuit.

Note that the present invention is not limited to the above embodiment; for example, in FIG. 3, the C-MOS inverter 13
The MOS switch that connects the input and output terminals of
Although the case where the OS FET 14 is used has been described, a P-channel MO8FET may also be used, and if a P-channel MO8FET is used, the voltage 1! A voltage ■.

It is necessary to reverse the relationship between and ground voltage Vjl.

Also, if you use the SO8CMO8f process,
As shown in FIG. 10, an N-channel MOS FIT 81 and a P-channel MO8FET 8 are used as MOS switches.
It is also possible to use an MOaX switch in which J is connected in parallel, and if a C-MOS inverter whose input and output terminals are short-circuited is used as the bias generation circuit in this case, the configuration as shown in the figure will be obtained. That is, N channel MOS F
A bias generation circuit 8S for applying a bias voltage to the gate electrode of ET&J connects the vDD application point and the vam
P channel k MOS FIT tt 4 between application point
and N-channel MO8FICT g 5 are connected in series, and both dart electrodes are connected to the common drain point. On the other hand, P Chasle MO8FIT
A bias generation circuit 86 for applying a bias voltage to the pack dart electrode 82 has a P channel MO8FICT 87 and an N channel M between the V□ application point and the vDD application point.
The configuration is such that the O8FETs 811 are connected in series and both dart electrodes are connected to the common drain connection point.

In each case, the above-mentioned embodiment or application fpIl applied the present invention to a voltage comparison circuit of an analog-to-digital conversion circuit, but next, the present invention was applied to a switched capacitor integration circuit. An example will be explained below.

FIG. 11 is a circuit diagram of a switched capacitor integration circuit according to the prior art. That is, this circuit has φ,
The MOS FET 20J is turned on at the timing φ2 to charge the capacitor 202 with the input voltage IN, and then the MOS FET 203 is turned on at the timing φ2 to discharge the capacitor 1202.

In other words, two MOS FETs 20 J, 20
J acts as a resistance element, and the 4M signal passing through this resistance element is integrated by a circuit consisting of a capacitor 204 and an operational amplifier 205, and its vp detailed operation is [J, T, C
&V@l at al: Sample@d Ana
log Filt@ring UsiqSwitch
ed Capacitor@aa R@5istor
Equivalents, IEEE Jof5
olid-8tate-C1rcuits, vo
l, 5C-12+ 46, Dec.

1977, p592-p599J.

Two MOSs act as resistance elements in this integration circuit.
The resistance of FETs 20J and 203 becomes a problem. That is, in general, when the on-resistance increases, it means that the weighing ratio of the integrating circuit decreases, and the characteristics deteriorate. Therefore, it is desirable that the element dimensions of the two MO8FETs 201 and 203 be large, but in the same way as in the case of the voltage comparator circuit, the dirt-source and gate-drain characteristics of the MOS FETs should be , due to the negative effect of signal feedthrough, M
The dimensions of the OS FETs 201 and 203 have to be reduced. Therefore, as shown in FIG. 12, the present invention is applied to the above-mentioned conventional switch-chip capacitor integration circuit.
Tsuktsuku gate electrode KP of MOS F'ET 20 J
Channel MO8FIT 206 and Nchasle MO8
/4 ias generation circuit 208 consisting of FIT z o y
Supply the bias voltage ■, 1 obtained by MOS
P chasle MO8 on the pack gate electrode of FET 206
FET? 051 and N chasle MO8FET
;l By supplying the bias voltage vg2 obtained by the bias generation circuit 211 consisting of
The on-resistance of FETs 201 and 205 is reduced, and the diameter of φ4. Charging and discharging of charges is completed within the switching period of φ2. Also, MOS FET 201
, 205 can be minimized, and as a result, the influence of feedthrough can be minimized and high integration can be achieved.

〔Effect of the invention〕

As explained above, this BAK bias allows the operating point of the inverting amplification means to be quickly set, thereby providing an amplifier circuit capable of high-speed operation.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a conventional amplifier circuit, Figure 2 is a MOS F
A characteristic diagram of ET when used as a MOS switch, FIG. 3 is a block diagram of an embodiment of the present invention, FIG. 4 is a simplified diagram specifically showing the element structure of a part of it, and FIG. Characteristic diagrams of MOS switches and switches in the above embodiment circuit, Figures 6 to 8
The figures are respectively block diagrams of bias generation circuits according to other embodiments of the present invention, Fig. 9 is a block diagram of an applied model of the present invention, Fig. 10 is a block diagram of a modified example of the present invention, and Figs. Sui, block diagram of chido-kiya 9-shita integral circuit, 12th
The figure is a block diagram of an application example in which the present invention is applied to a switched capacitor integration circuit. 11.21, 82, 114.87...P Chasle MO
8FET, 12, 14, 22, 33.42, 64°65
．． 66.81,85. Ell...N channel special FI
T, 13, 61.62.63... C-MOS inverter, 16.6'l, 68.69... Coupling capacitance, 24.
74. , '15.76.83.86...Bias generation circuit, 31...Constant current source circuit, 32.5c52...
Resistance, 4...Load resistance.

Claims (9)

[Claims] (1) A MOS consisting of an inverting amplifying means and at least one Mo8 FET that sets the operating point of the inverting amplifying means by short-circuiting the input and output of the inverting amplifying means.
An amplifier circuit comprising: a switch; and bias generation means for supplying a bias voltage having a value between a power supply voltage and a reference voltage to a pack gate electrode of an Mo8 FET in the MOB switch. (2) The bias generating means is the Mo8 switch. 2. The amplifier circuit according to claim 1, wherein the amplifier circuit is configured to generate a bias voltage having a value corresponding to the threshold voltage of the MOB FICT in the transistor. (3) The amplifier circuit according to claim 1, wherein the bias generating means includes an Mo8) ICT on the same channel as the MOB FiCT in the MoI switch. (4) The amplifier circuit according to claim 1, wherein the bias generating means is constructed by short-circuiting the input and output terminals of a complementary WMO8 in/quarter consisting of Mo8 FETs of different channels. (5) constant current generating means in which the bias generating means is inserted between the power supply voltage application point or the reference voltage application point and the bias voltage output terminal, and the gate electrode is connected to the bias voltage output terminal and the Claim 1, comprising an Mo8 FET in the MoI switch inserted between the bias voltage output terminal and the reference voltage application point or the power supply voltage application point and a Mo8 FET on the same channel. amplifier circuit. (6) The bias generating means includes a load resistor inserted between the power supply voltage application point or the reference voltage application point and the bias voltage output terminal, and a gate electrode connected to the bias voltage output terminal, and the bias voltage The chip according to claim 1, comprising a Mo8 FET in the Mo8 switch inserted between an output end and the reference voltage application point or the power supply voltage application point and a MOS FET of the same channel.・Matrix amplifier circuit. (7) The amplifier circuit according to claim 1, wherein the bias generating means is configured to generate a bias voltage of a constant value. (8) The amplifier circuit according to claim 1, wherein each of the MOS switches is composed of one single channel MOS FET. (9) The amplifier circuit according to claim 1, wherein the MO8 switch and the MO8 switch are configured by two MOS FITs with different channel types connected in parallel.