JPS5812540Y2 - Frequency converter commutation failure protection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a commutation failure protection device for a frequency converter that directly obtains an output of any frequency using a power commutation method.

For example, a square wave current type cycloconverter is shown in FIG. 1 as an example of a frequency converter of the above type for supplying a variable frequency alternating voltage to a variable speed alternating current motor.

In FIG. 1, reference numeral 2 denotes a square wave current type cycloconverter with a known connection, which receives AC power from an AC power supply 3 via a power circuit breaker 4 and a DC reactor 5, and receives AC power at a controlled frequency (output frequency). The output is supplied to an AC motor 6.

The cycloconverter 2 consists of 18-arm thyristors, and each thyristor is given a code made by arranging three alphabets according to its placement position.

The first alphabet of this Cyrisk code is determined depending on which phase it belongs to, R, S, or T when viewed from the input power supply side, and similarly, the second alphabet!・ is determined by whether it belongs to the U, V, or W phase when viewed from the output side or load side, and the third alphabet indicates a pair of series that belong to the same phase when viewed from the power supply side or the load side. It is defined as P or N depending on whether the thyristor of the connection is arranged on the current inflow side or on the current outflow side.

For example, a thyristor that is in the R phase when viewed from the input power supply side, is in the U phase when viewed from the load side, and is arranged on the current inflow side is given the symbol RUP.

The cycloconverter 2 operates to flow a square wave current of a desired frequency to the AC motor 6 by controlling the load side commutation timing and the power source side commutation timing of each thyristor.

However, in this type of cycloconverter, if the residual energy due to the leakage inductance of the load motor is large during commutation at the load side commutation timing, the commutation type turning angle becomes too large and the thyristor, which should be turned off, becomes conductive. If this condition continues, commutation failure will occur, eventually resulting in an arm short circuit, which will cause serious accidents due to destruction of the SIRISK element and short circuit of the main circuit power supply.

- As an example, FIG. 2 shows the relationship between the phase current and the load-side commutation timing in a cycloconverter that outputs the +frequency of the power supply frequency.

Figure b-d according to the load side commutation timing signal in Figure a.
The load side currents iU, iv, and iw shown in are passed,
This load side current is the power supply side current iR,is in e-g in the same figure.

This is obtained by making each thyristor in FIG. 1 conductive in the order shown in the figure under io.

In this type of converter, due to the overlap period that occurs during commutation, that is, the existence of the hatched portion A in the figure, for example,
In the commutation to UP, the current flows from the energization route shown by the dashed line L1 in Figure 1 to the energization route shown by the broken line L2, but if the overlap angle exceeds 60', a commutation failure occurs and the thyristor TWP turns off. Without doing so, the second attempt is made at time t2.
When the thyristor RWN is fired, an arm short circuit occurs from the energization route 1-L to the energization route L3 shown by the two-dot chain line in FIG.

Commutation failure in the frequency converter thus leads to an arm short circuit, which is extremely dangerous.

Conventionally, to protect against such a situation, an arm short circuit or the like occurs, and after an overcurrent flows, this is detected and the power circuit breaker is tripped.

An object of the present invention is to provide a commutation failure protection device for a frequency converter that can detect commutation failure in advance and prevent commutation failure.

In order to achieve this objective, the present invention detects the current flowing through the controllable electric valve to be turned off at the load side commutation timing using a pulse signal at 60° intervals synchronized with the power supply, and When the voltage exceeds 60', a gate a disconnection signal is issued to prevent a short circuit in the arm of the frequency converter and damage to the electric valve, as well as to protect the main power supply circuit from failure due to a short circuit in the arm. be.

Hereinafter, embodiments of the present invention will be described with reference to the aforementioned square wave current type cycloconverter.

In Figure 2, each thyristor is energized 120°, and 6
Although ignition is performed using double pulses at every 0°, the present invention is characterized in that the overlapping period in the load side commutation timing is detected using this 60' pulse interval.

In the main circuit shown in FIG. 1, current detection converters 10R and 10T are inserted into the R phase and S phase of the input conductor on the power supply side.

The currents of each phase on the power supply side detected by this converter are used as input signals of the device shown in FIG. 12 T through resistor 13 R
, 13S and 13T.

The voltages generated across these resistors are led to the AND circuit 15 via analog-to-digital converters 14 Rj4 S and 14 T, respectively.

As is clear from FIGS. 2e to 2e, normally, the power supply side currents iR, i5. i□
Since one of them is always at the 0 level, the output of the AND circuit 15 is at the O level.

During the overlap period, the AND circuit 15 outputs a level of output as shown in FIG. 2i.

On the other hand, as shown in FIG. 2j, a pulse oscillator 16 is provided which generates pulses at 60° intervals in synchronization with the power supply, and its output pulses are guided to the first input terminal of an AND circuit 17.

The output signal of the AND circuit 15 is introduced to the second input terminal of the AND circuit 17 .

When the output of the AND circuit 17 becomes 1, it indicates that the overlap period has started at the load side commutation timing.

This state is stored in the memory circuit 18.

That is, the AND circuit 1 is connected to the memory circuit 18 by the AND output of both signals shown in FIG.
It is reset by changing the output of 5 from 1 to 0.

A reset signal for this reset is obtained as an output signal of an OR circuit 20 which outputs the logical sum of the negative output of the AND circuit 15 obtained via the inverter 19 and the device operation start signal.

A determination circuit 21 is arranged on the output side of the memory circuit 18.

This determination circuit 21 uses the second pulse P of the pulse generator 16.
At the rising edge of 2, the memory content of the memory circuit 18 becomes 1.
Determine whether or not.

As shown in FIG. 4, if the output of the memory circuit 18 is already O at the rising edge of the second pulse P2,
This indicates normal commutation, but if the output of the memory circuit 18 is still at l at the same time as shown in FIG. 5, it is determined that this is abnormal commutation.
Cycloconverter 2 via gate cutoff transmission circuit 22
to perform gate blocking.

A gate cutoff reset circuit 23 is attached to the gate cutoff transmitting circuit 22.

The reset circuit 23 stops the gate cutoff signal from the gate cutoff transmission circuit 22 and restores the gate signal.

A counter 24 counts how many times the reset circuit 23 performs the reset, that is, how many times a commutation failure state that generates a gate cutoff signal appears.

The fact that the gate is shut off many times means that the cycloconverter 2 is abnormal, so the third AND circuit 25 is configured to trip the power supply side circuit breaker 4 when the number of gate shutdowns exceeds a predetermined number of times. It is set up.

The AND circuit 25 issues a trip command on the condition that not only the output of the counter 24 but also the output of the determination circuit 21 is 1.

The gate cutoff reset circuit 23 is the gate cutoff transmitter circuit 2
The gate signal is automatically restored after the gate is shut off for a certain period of time during which the gate is shut off according to No. 2.

In this way, by determining that the overlapping period during commutation at the load side commutation timing is 60° or more and shutting off the gate, serious accidents such as arm short circuits can be prevented.

FIG. 6 shows a second embodiment of the present invention.

Analog-to-digital converter 14 in this embodiment
R, 14S, and 14T are the same as the embodiment shown in FIG.

As shown by arrows in FIG. 7, in a cycloconverter that outputs the same frequency as the power supply, load-side commutation timing occurs at 60° intervals.

In this case, the signal from the AND circuit 17 shown in FIG. 3 and the signal from the determination circuit 21 overlap, so this problem can be avoided by using the circuit configuration shown in FIG. 6.

Power supply side phase currents iR and is digitized by AND circuits 15R, 15S, 15T, respectively,
The AND of i5 and 11 or 11 and iR is output.

AND circuits 17R and 1 calculate the logical product of this output signal and the output signal of the pulse oscillator 16 that generates pulses at 60° intervals.
7S and 17T, and the output is sent to the memory circuit 18.
Store in R, 18S, 18T.

Furthermore, a second 60° pulse (P2 in Figures 4 and 5)
), the determination circuits 21R, 221S, and 21T determine whether the duration time of one output from the AND circuits 15R, 15S, and 15T is longer than 60'.

Is the reset of the memory circuits 18R, 18S, and 18T an initial condition for starting operation, or is the AND circuit 15R, 15S, 1
5 Depends on whether the output of T is O.

That is, the outputs of the AND circuits 15R, 15S, 15T are guided to one input terminal of the OR circuit 20 via the NOR circuit 26, and the operation start signal is guided to the other input terminal of the OR circuit 20, and the output thereof is Each memory circuit 18R with a signal
Reset 18T.

The output of each judgment circuit is sent to a gate cutoff signal via an OR circuit 27 so that if any one of the judgment circuits 21R to 21T is in the state shown in FIG. 5, a gate cutoff signal is issued. lead to circuit 22;

The following configuration is the same as that in FIG.

As described above, the device shown in FIG. 6 has power supply side phase currents iR, i5
．． By detecting the overlapping period of two currents at the same time in each of the iTs, it is possible to detect a commutation failure in the cycloconverter 20, shut off the gate, and prevent serious accidents such as arm short circuits. can.

FIG. 8 shows a third embodiment of the present invention.

In this embodiment, the output signal of the AND circuit 15 is
It is led to the memory circuit 18 and one end of the NOR circuit 29 via the delay circuit 28.

The delay circuit 28, as shown in FIGS. 9 and 10,
It is used to apply an on-delay so that one output of the AND circuit 15 does not overlap the pulse of the pulse oscillator 16.

The memory circuit 18 is set at the rising edge when the output of the delay circuit 28 changes from 0 to 1, and preparations are made for overlapping period determination.

A NOR circuit 29 is provided to reset when the output of the delay circuit 28 becomes 0 within 60 degrees thereafter.

The other components are substantially the same as those of the embodiment of FIG.

The embodiment of FIG. 8 differs from the first and second embodiments in that it uses a memory circuit 18 that operates at the rising edge of the input signal.

The device of FIG. 8 also has a pulse oscillator 1 as shown in FIG.
If the output of the delay circuit 28 is O at the time when the second pulse P2 from 6 is output, it is determined that there is no commutation failure, and as shown in FIG. If the output of 28 is still 1, it is determined that commutation has failed, and the gate is shut off, and if this is repeated several times, the power circuit breaker is tripped.

FIG. 11 shows a fourth embodiment of the present invention.

Current detection AND circuits 15R, 15S of this embodiment,
Circuit part up to 15T and gate cutoff transmitter circuit 22
The following circuit parts are the same as the embodiment shown in FIG.

The output sides of the AND circuits 15R, 15S, 15T are connected to the set input terminals of the memory circuits 18R, 18S, 18T via delay circuits 28R, 28S, 28T.

These memory circuits include output pulses from the pulse oscillator 16 and delay circuits 28R and 28S.

The output signal of 28T is connected to the NOR circuit 29R, 29S,
The signal obtained through 29T and the operation start signal are led to OR circuits 20R, 20S and 20T, and are reset by their output signals.

The subsequent circuit configuration and signal processing are performed in accordance with those shown in FIG.

This embodiment makes it possible to distinguish between the overlap start signal of the overlap period at the load side commutation timing and the commutation failure detection signal even in a ÷frequency cycloconverter.

As described above, according to the present invention, in a frequency converter of the type mentioned at the beginning, such as a square wave output type cycloconverter, commutation of a controllable electric valve, such as a thyristor element, commutating depending on the load side commutation timing is achieved. The shape angle is 6
By detecting that the temperature exceeds 0°, the gate can be shut off to prevent arm short circuits between elements, thereby preventing destruction of the elements and serious accidents in the main circuit power supply.

In addition, the frequent occurrence of the gate shutdown as described above indicates that the controllable electric valve element is in a situation where failure is likely to occur, so if this occurs more than the number of times, the power circuit breaker is tripped. By doing so, the converter and power supply can be more completely protected.

[Brief explanation of the drawing]

Figure 1 is a connection diagram showing an example of the main circuit configuration of a frequency converter, and Figures 2 a-j are diagrams showing phase currents and load side rotation in a Shibetsu wave number output type converter to explain the signals to be detected in the present invention. FIG. 3 is a block diagram of an embodiment of the commutation failure protection device according to the present invention;
Fig. 4 a, l) and Fig. 5 a, l) are signal waveform diagrams of main parts showing different operating states of the device in Fig. 3, and Fig. 6 is a block diagram of a second embodiment of the device of the present invention. , FIG. 7 is an explanatory diagram showing the commutation order and load-side commutation timing of each electric valve in the soil wave number output type converter, FIG. 8 is a block diagram of the third embodiment of the device of the present invention, and FIG. 9 Figures a, l) and Figure 10a
, l) are signal waveform diagrams of the main parts of the device shown in FIG. 8 in different operating states, and FIG. 11 is a block diagram of a fourth embodiment of the device of the present invention. 2... Square wave current type cycloconverter, 3.
...AC power supply, 4...Power circuit breaker, 5.
...DC reactor, 6...AC motor, IOR, IOT...Current transformer, 11R, 11S
, 11 T... Auxiliary current transformer, 12 R, 12
S, 12 T...Full wave rectifier, 13 Rj3
S, 13T...Resistance, 14R, 14S,
14T・・・Analog-digital converter, 15
．． 15 R, 15S, 15 T, 17.17 R, 1
7S, 17T. 25...AND circuit, 16...60°
Interval pulse oscillator, 18.18 R, 18S, 18
T... Memory circuit, 19... NAND circuit, 20.2OR, 20S, 20 T, 27...
...OR circuit, 21.21 R, 21S, 21 T・
... Judgment circuit, 22 ... Gate cutoff transmission circuit, 23 ... Reset circuit, 24 ...
・Counter, 26, 29.29 R, 29S, 29
T,...Nor circuit, 28.28R, 28S
, 28 T...Telelay circuit.

Claims (1)

[Scope of utility model registration request] A frequency converter of a type that directly obtains an output of any frequency using a power commutation method, a current detector that detects a power supply side current of the frequency, a rectifier that rectifies the current detected by the current detector, an analog-to-digital converter that converts the rectified current rectified by the rectifier from analog to digital; a pulse generator that generates pulses every 60 degrees in synchronization with the power supply of the frequency converter;
an AND circuit that outputs a logical product of digitally converted values of the power supply side current taken out from the analog-to-digital converter in synchronization with the output pulse of the pulse generator;
a memory circuit that stores the operational output of this AND circuit;
The memory state of this memory circuit is 60 minutes from the memory start point.
A frequency converter comprising: a determination circuit that determines whether or not commutation has failed after a lapse of time; and a gate cutoff oscillation circuit that shuts off the gate of the frequency converter when the determination circuit determines that commutation has failed. Commutation failure protection device.