JPS5473542A - Pll circuit - Google Patents

Pll circuit

Info

Publication number
JPS5473542A
JPS5473542A JP14088677A JP14088677A JPS5473542A JP S5473542 A JPS5473542 A JP S5473542A JP 14088677 A JP14088677 A JP 14088677A JP 14088677 A JP14088677 A JP 14088677A JP S5473542 A JPS5473542 A JP S5473542A
Authority
JP
Japan
Prior art keywords
pulse
supplied
input
phase
vco32
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14088677A
Other languages
Japanese (ja)
Inventor
Ryusuke Moriya
Yasuhiro Fujimori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP14088677A priority Critical patent/JPS5473542A/en
Publication of JPS5473542A publication Critical patent/JPS5473542A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop

Abstract

PURPOSE:To obtain the VCO output which is synchronizing accurately with the input pulse by securing a synchronization between the clock pulse and the input pulse of the PLL circuit and also enabling the phase comparison with the divided low frequency and regardless of the dropout of the input pulse. CONSTITUTION:Pulse SJ obtained by dividing 30 input with clock pulse SI along pulse PC sent from VCO32 are supplied to DFF35 to obtain pulse PD. Then pulse SJ is supplied to trapezoid wave signal generator circuit 36 through phase comparator circuit 31 to obtain trapezoid wave signal SA; pulse PD is supplied to delay monostable multivibrator 37 to obtain pulse PM; and PM is supplied to sampling pulse generator circuit 38 to obtain sampling pulse PS. After this, signal SA is sample-held 39 by pulse PS. This sample-held voltage, i.e., phase comparison voltage EH is supplied to VCO32 through LPF34 to control the phase of pulse PC. Accordingly, pulse SJ and PC are in a fixed time relation, and pulse PC synchronizes with input pulse SI.
JP14088677A 1977-11-24 1977-11-24 Pll circuit Pending JPS5473542A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14088677A JPS5473542A (en) 1977-11-24 1977-11-24 Pll circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14088677A JPS5473542A (en) 1977-11-24 1977-11-24 Pll circuit

Publications (1)

Publication Number Publication Date
JPS5473542A true JPS5473542A (en) 1979-06-12

Family

ID=15279055

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14088677A Pending JPS5473542A (en) 1977-11-24 1977-11-24 Pll circuit

Country Status (1)

Country Link
JP (1) JPS5473542A (en)

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