JPH1146481A - Parallel multiple inverter device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent large currents accompanied by resonances from flowing through the smoothing capacitors of a parallel multiple inverter device and to suppress the temperature rises of the capacitors, by providing damping resistors in the plus- and minus-potential buses of the plus-, intermediate-, and minus-potential buses of a DC linkage portion for connecting a plurality of three-level inverters in parallel with each other. SOLUTION: Three-level PWM inverters 1, 2 are provided respectively between a system power supply and, e.g. a motor M to connect the inverters 1, 2 by a DC linkage portion 3. In the DC linkage portion 3, providing three plus- interthediate- and minus-potential buses P, C, N for connecting the three- level PWM inverters, thereby smoothing capacitors 4a, 4c and 4b, 4d are provided respectively in parallel with each other between the plus and intermediate- potential buses P, C and between the intermediate- and minus-potential buses C, N to mount intermediately damping resistors 6a, 6b in the respective plus- and minus-potential buses P, N. By this configuration, making any resonance suppressible, no large current flows through the smoothing capacitors 4a-4d to make preventable the temperature rises thereof.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a three-level PWM (PalseWidth M) for obtaining a large capacity inverter.
so-called parallel multiplex inverter device in which inverters are connected in parallel by a DC link unit,
In particular, the present invention relates to a parallel multiplex inverter device in which resonance is suppressed.

[0002]

2. Description of the Related Art FIG. 7 is a circuit diagram showing a configuration of a parallel multiplex inverter device composed of two three-level PWM inverters. In the drawing, reference numerals 1 and 2 denote a three-level PWM inverter, and 3 denotes a DC link unit. ing. The three-level PWM inverters 1 and 2 are provided between the system power supply and, for example, the electric motor M, and are connected to each other by the DC link unit 3. The DC link unit 3 includes three DC buses, that is, a positive potential bus P, an intermediate potential bus C, and a negative potential bus N, between the positive potential bus P and the intermediate potential bus C, and between the intermediate potential bus C and the negative potential bus. Smoothing capacitors 4a, 4c, 4b, and 4d are provided in parallel with the bus N, respectively. Smoothing capacitors 4a and 4b are 3 level PWM
Close to the inverter 1 and also to the smoothing capacitors 4c and 4c.
d is located immediately adjacent to the three-level PWM inverter 2. Reference numerals 5a, 5b and 5c denote inductances of the positive potential bus P, the intermediate potential bus C and the negative potential bus N, respectively.

Next, the operation will be described. 3 level PW
Each of the M inverters 1 and 2 has a function of temporarily converting a system power supply having a commercial frequency (50 Hz or 60 Hz) into DC, and further converting the DC into AC having a variable frequency.
The outputs of these two inverters 1 and 2 are added and supplied to the electric motor M. Smoothing capacitors 4a-4d
Keeps the DC voltage of each positive potential bus P, the intermediate potential bus C and the negative potential bus N constant, and electrically connects the three-level PWM inverters 1 and 2 with the DC potential between them being equal. ing.

[0004]

However, in such a conventional parallel multiplex inverter device, a three-level PW
Smoothing capacitors 4 a to 4 a accompanying pulsating current due to switching of M inverters 1 and 2 and resonance of DC link unit 3
d, a large current flows to the smoothing capacitors 4a to 4d
There is a problem that the temperature rise occurs.

FIG. 8 is an explanatory diagram showing two resonance loops generated in the DC link unit 3. A first resonance loop X is a loop that loops through a smoothing capacitor 4a, an inductance 5a, a smoothing capacitor 4c, and an inductance 5b. The second resonance loop Y includes a smoothing capacitor 4a, an inductance 5a, smoothing capacitors 4c and 4d, an inductance 5
This is a loop that loops around c and the smoothing capacitor 4b.

FIG. 9 shows a DC link unit 3 viewed from an inverter.
Is a graph showing the resonance characteristics of FIG. 5, where the horizontal axis represents the frequency f and the vertical axis represents | z |. In the graph, f ₁ is the resonance frequency of the resonance loop X, and f ₂ is the resonance frequency of the resonance loop Y. As is clear from FIG. 9, the peak value of | z | is large at each of the resonance frequencies f ₁ and f ₂ , that is, resonance is occurring.

[0007]

According to a first aspect of the present invention, there is provided a parallel multiplex inverter device comprising three direct-current (DC) link portions for connecting a plurality of three-level inverters in parallel, namely, a positive potential bus, an intermediate potential bus, and a negative potential bus. A damping resistor is provided on the positive potential bus and the negative potential bus among the buses. This reduces the damping resistance
A large current due to the resonance phenomenon is prevented from flowing through the smoothing capacitor, and its temperature rise is suppressed.

In the parallel multiple inverter device according to the second and third aspects of the present invention, a portion of the positive potential bus and the negative potential bus in the DC link portion is cut off, and a resistance material formed of a high resistance material as a damping resistor is provided here. Alternatively, it is characterized by being provided with a hole in it. In the second and third aspects of the invention, the resistance value can be finely adjusted, the cooling effect can be enhanced by promoting ventilation, and the fluctuation of the resistance value can be suppressed.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) Hereinafter, the present invention will be specifically described with reference to the drawings showing the embodiments. FIG. 1 is a circuit diagram showing a configuration of a parallel multiplex inverter device according to the present invention. In FIG. .

The three-level PWM inverters 1 and 2 are provided between a system power supply and, for example, an electric motor M, and are connected to each other by a DC link unit 3. The DC link unit 3 includes three DC buses connecting the three-level PWM inverters 1 and 2, namely, a positive potential bus (P busbar) P, an intermediate potential bus (C busbar) C, and a negative potential bus (N busbar) N, Smoothing capacitors 4a, 4c, 4b and 4 are connected in parallel between the positive potential bus P and the intermediate potential bus C and between the intermediate potential bus C and the negative potential bus N, respectively.
d is provided. The smoothing capacitors 4a and 4b are 3
The smoothing capacitors 4c and 4d are located immediately adjacent to the level PWM inverter 1, and the smoothing capacitors 4c and 4d are located immediately adjacent to the three-level PWM inverter 2, respectively. Reference numerals 5a, 5b, and 5c denote inductances of the positive potential bus P, the intermediate potential bus C, and the negative potential bus N, respectively. The positive potential bus P and the negative potential bus N are provided with damping resistors 6a and 6b, respectively.

FIG. 2 is an explanatory diagram showing two resonance loops X and Y in the DC link unit 3. The resonance loop X loops around a smoothing capacitor 4a, an inductance 5a, a damping resistor 6a, a smoothing capacitor 4c, and an inductance 5b. It is a loop. The resonance loop Y includes a smoothing capacitor 4a, an inductance 5a, a damping resistor 6
a, smoothing capacitors 4c and 4d, damping resistor 6
b, an inductance 5c and a smoothing capacitor 4b.

When the capacitance of each of the smoothing capacitors 4a to 4d is C (Farad) and the inductance of each of the DC buses 3a to 3c is L _P , L _C , L _N (Henry), the damping resistance of the damping resistors 6a, 6b is assumed. The damping resistance values R _P of the damping resistors 6a and 6b required to suppress the resonance of the resonance loop X are set as follows.
It is given by equation (1).

[0013]

(Equation 1)

Further, the damping resistance values R _P of the damping resistors 6a and 6b required to suppress the resonance of the resonance loop Y
Since the damping resistors 6a and 6b are in a state of being connected in series, the resistance value of the damping resistor 6a only needs to be half or more of the critical resistance value, and the following expression (2) should be satisfied.

[0015]

(Equation 2)

The temperature T of the smoothing capacitors 4a to 4d has a relationship (T 関係 I ² ) proportional to the square of the resonance current I, and the loss Loss generated in the damping resistors 6a and 6b is equal to the resonance current I squared (I ²⁾ and the damping resistor 6a, the damping resistance value R _P of 6b product of (Loss
= I ² R _P ), and the voltage V between the inverters 1 and 2 is the product of the resonance current I and the impedance L of the damping resistors 6a and 6b (V = I × L). The conditions for reducing the respective values within the respective allowable ranges are the optimum design conditions.

Accordingly, the damping resistance value R _P of the DC link unit 3 is set to a value slightly smaller than the value that completely suppresses the resonance, and the resonance current I is made to flow a little, so that the smoothing capacitors 4a to 4d In some cases, the loss Loss generated in the damping resistors 6a and 6b and the voltage V between the two inverters 1 and 2 can both be reduced within the allowable current range.

FIG. 3 shows a three-level PWM inverter 1 when the damping resistance value R _P is set so as to leave a little resonance.
6 is a graph showing the resonance characteristics of the DC link unit 3 as viewed from the second side. Figure 3 and Figure 9 and as is clear from the comparison, the damping resistor 6a, the interposed in 6b, the resonance frequency f ₁ of the resonant loop section X, the resonance loop portion Y resonance frequency f ₂
It can be seen that the peak value at is significantly suppressed.

FIG. 4 shows that the rated output current of the inverter is I, 2
The minimum resistance value (critical resistance value) that can completely suppress the resonance of the two resonance loops X and Y is R, and the damping resistor 6
a, Loss generated in 6b and two 3 level PW
9 is a table showing a calculation example in which a voltage V between M inverters 1 and 2 is obtained. As is clear from FIG. 4, the damping resistor 6a, when the damping resistance value R _P of 6b slide into smaller from the critical resistance value R, the resonance current is slide into increasing, 2
The voltage between the three three-level PWM inverters 1 and 2 becomes small, and in the case of 0.58R, the damping resistors 6a,
It can be seen that the loss Loss generated at 6b is the largest.

When the resonance current value increases, the temperature of the smoothing capacitors 4a to 4d rises.
To to decrease the damping resistance R _P in the range of allowable current ~4b to suppress the temperature rise of the smoothing capacitor 4a~4d can that desirable.

In the first embodiment, a plus
Damping resistors on the potential bus P and the negative potential bus N
Is provided, the resonance can be suppressed and the smoothing capacitor 4a
To prevent the temperature rise without flowing a large current through
And the damping resistance value R _PSet properly
To allow the resonance current flowing through the smoothing capacitors 4a to 4d.
3-level PWM inverters 1, 2 connected in parallel within the range
Between the damping resistors 6a and 6
This has the effect of reducing the loss occurring in b.

(Embodiment 2) In this embodiment 2, instead of ordinary resistors, damping resistors 6a and 6b are made of nichrome, stainless steel or another high-resistance material, for example, a plate material (bar material). May be used). FIG. 5 is a schematic diagram of the damping resistors 6a and 6b used in the second embodiment. The damping resistor 6a,
6b cuts a predetermined length of the positive potential bus P and the negative potential bus N, and has a width corresponding to the width dimension of the positive potential bus P and the negative potential bus N, and the thickness, length and material (resistance). Value), resistance materials 6c and 6d having an optimum resistance value are interposed, and are fixed integrally with the positive potential bus P or the negative potential bus N with set screws (or welding) 6e. . With such a configuration, the damping resistors 6a and 6
The inductance value of b can be reduced, and a decrease in the resonance frequency of the DC link unit 3 can be prevented.

(Embodiment 3) In Embodiment 3, as in Embodiment 2, the damping resistors 6a,
6b is a plate made of nichrome, stainless steel, or other high-resistance material (or a bar) instead of a normal resistor and having a hole. FIG.
Are the damping resistors 6a used in the third embodiment,
It is a schematic diagram of 6b. The damping resistors 6a and 6b cut off a part of the positive potential bus P and the negative potential bus N by a predetermined length, and have a width corresponding to the width dimension of the positive potential bus P and the negative potential bus N. The length is adjusted, the material (resistance value) is selected, the resistance members 6c and 6d set to the optimum resistance value are interposed, and the set screw (or welding) 6 is set.
At e, the positive potential bus P and the negative potential bus N are integrally fastened. A plurality of holes 6f are opened in the resistance members 6c and 6d, and ventilation is promoted in the holes 6f, heat is efficiently radiated, cooled, and a change in resistance value is prevented.

[0024]

According to the first aspect of the invention, by providing a damping resistor on the positive potential bus and the negative potential bus of the DC link portion, resonance can be suppressed, so that a large current does not flow through the smoothing capacitor. loss temperature rise can be prevented, and by choosing the damping resistance R _P properly, within a tolerance of the resonant current flowing through the smoothing capacitor, which reduces the potential difference between the inverter connected in parallel, and generates a damping resistor Can be reduced.

According to the second aspect of the invention, the damping resistor is configured by replacing a part of the bus with a resistance material of stainless steel, nichrome or other high-resistance material. There is an effect that the inductance value of the damping resistor can be reduced, and a decrease in the resonance frequency of the DC link unit can be prevented.

According to the third aspect of the present invention, since a part of the bus is replaced with a resistance material having holes, the flow of air for cooling the damping resistor can be promoted.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a parallel multiplex inverter device according to Embodiment 1 of the present invention.

FIG. 2 is an explanatory diagram showing a resonance loop of the DC link unit in FIG.

FIG. 3 is a graph showing resonance characteristics of the DC link unit of FIG.

FIG. 4 is a chart showing a calculation example.

FIG. 5 is a schematic diagram of a damping resistor of the parallel multiple inverter device according to the second embodiment of the present invention.

FIG. 6 is a schematic diagram of a damping resistor of a parallel multiple inverter device according to a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a conventional parallel multiplex inverter device.

FIG. 8 is an explanatory diagram illustrating a resonance loop of the DC link unit in FIG. 7;

FIG. 9 is a graph illustrating resonance characteristics of the DC link unit of FIG. 7;

[Explanation of symbols]

1, 3 level PWM inverter, 3 DC link section, 4a-4d smoothing capacitor, 6a, 6b damping resistor, 6c, 6d resistance material.

Claims (3)

[Claims] 1. A damping resistor is connected to a positive potential bus and a negative potential bus among three DC buses of a positive potential bus, an intermediate potential bus, and a negative potential bus of a DC link unit for connecting a plurality of three-level inverters in parallel. A parallel multiplex inverter device provided. 2. The parallel multiplex inverter device according to claim 1, wherein a part of the bus is cut off and a resistance material of a high resistance material is interposed here as the damping resistance. 3. The parallel multiplexing method according to claim 1, wherein the damping resistor is formed by cutting a part of the bus bar, forming a high-resistance material therein, and interposing a resistance material having a hole formed therein. Inverter device.