JPH11306015A - Operating processing method and microcomputer using the method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an operation processing method and a microcomputer which uses the operation processing method which can reduce utility capacity of an instruction memory and can improve compression efficiency and speed up operation. SOLUTION: A primary instruction code to be inputted to an instruction decoder 80 has an instruction length of an (m) bit ((m) is a natural number) sufficient to control an operator/controller/register group and a program expressed by a secondary instruction code which is used by the program having the instruction length of an (n) bit ((n) indicates a natural number and m>=n) sufficient to allocate all the primary instruction codes used by the program is stored in an instruction memory 60. Then, a predecoder 70 is structured in which reconstruction of logic is easy as is represented by a PLA, a gate array or the like, converts the secondary instruction code taken out of the instruction memory 60 into the primary instruction code, the primary instruction code is converted into plural control signals, and the operator/controller/register group 90 executes a specified processing on the basis of a control signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing method for a program created with an instruction code of m bits and a microcomputer using the same.

[0002]

2. Description of the Related Art Conventionally, microcomputers for embedding a device widely use a program created with an instruction code of m bits (m: natural number).

[0003] Such a conventional microcomputer will be described below. FIG. 11 is a block diagram showing a configuration example of a conventional microcomputer. The microcomputer 300 includes an instruction memory 310 for storing a program, and an instruction decoder 3 for converting an instruction code in the program in the instruction memory 310 into a plurality of control signals.
20 and an arithmetic / control device / register group 3 for executing a predetermined process based on a control signal from the instruction decoder 320
30.

In the microcomputer 300 configured as described above, the instruction code fetched from the instruction memory 310 is converted into a plurality of control signals by an instruction decoder 320, and based on the control signals, an arithmetic unit / controller / register The group 330 performs a predetermined process. The instruction code in the program in the instruction memory 310 is determined at the time of designing the instruction decoder 320. Since the program described using this instruction code is stored in the instruction memory 310, the word length of the instruction memory 310 is , The instruction length determined when the instruction decoder 320 is designed.

In the microcomputer as described above,
In particular, in recent years, high speed and high function have been required, but at the same time, cost reduction is required.

[0006]

However, in the microcomputer having the conventional configuration as described above, the operation unit / control unit / register is used to improve the performance in response to the demand for high speed and high function in the market. When the number of arithmetic units and registers in the group 330 is increased, the instruction length increases accordingly. As a result, the word length of the instruction memory 310 becomes longer, so that its area needs to be increased. This means
The built-in microcomputer having the instruction memory 310 built in the chip has a problem that the chip area is increased, that is, the cost is increased.

On the other hand, in an actual application, the instruction use efficiency is not so high. FIG. 12A shows an example of a 32-bit instruction set. In this case, 655 is used.
Although 36 types of instructions can be expressed, the capacity of the instruction memory of the built-in microcomputer is a small capacity of at most about 32 K words, and therefore, as shown in FIG. Another problem is that most of the instructions are not used.

As a method for suppressing an increase in the area of the instruction memory, as disclosed in Japanese Patent Application Laid-Open No. H7-13763, a variable length instruction is adopted to shorten the instruction length of an instruction having a statistically high frequency of appearance. And a method for reducing the memory capacity required to store the entire program.
As disclosed in Japanese Patent Publication No. 348490, a method of reducing the memory capacity by storing a program in a compressed form in a memory has already been devised.

However, in the former method, since the logic of the instruction decoder is fixed, it is necessary to assign all instructions including instruction not used in the program to the instruction code. There is. In the latter method, since a data decompression step is required at the time of program execution, program control becomes complicated,
As a result, there is a problem that there is a limit in increasing the operation speed.

An object of the present invention is to solve the above-mentioned conventional problems, and to provide an arithmetic processing method capable of reducing the used capacity of an instruction memory, improving compression efficiency and achieving higher speed operation. A microcomputer using the same is provided.

[0011]

In order to solve the above-mentioned problems, an arithmetic processing method according to the present invention and a microcomputer using the same employ a 15-bit secondary instruction code, so that the word length is 15 bits. It has an instruction memory, and by using a 32-bit instruction code as in the past, the word length is reduced to less than half compared to the case of having an instruction memory with a 32-bit word length only by the area of the instruction memory. It is characterized by the following.

As described above, by allocating only the instructions used in the program among the instructions usable in the microcomputer to the secondary instruction code finally stored in the instruction memory, the flexibility of the instructions is sacrificed. Without doing
It is characterized by minimizing the instruction length.

The conversion operation from the secondary instruction code to the primary instruction code does not require any special control and is realized by a simple conversion of decoding by a predecoder, so that high-speed operation is possible. It is characterized by doing.

The pre-decoder is a programmable logic whose logic can be easily reconfigured, and is characterized in that the pre-decoder can flexibly cope with a change in an instruction used due to a program change.

Furthermore, the present method is characterized in that it can be applied to an existing microcomputer by adding a predecoder, so that design resources can be effectively used.

As described above, the used capacity of the instruction memory can be reduced, and the compression efficiency can be improved and the operation can be performed at higher speed.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An arithmetic processing method according to a first aspect of the present invention is a method for extracting an instruction used in a program created by a primary instruction code consisting of m bits (m: natural number), and A primary instruction code program analyzing step for analyzing the frequency of occurrence, and according to the analysis result, only the primary instruction code used is replaced by a secondary instruction consisting of n bits (n: natural number and m ≧ n) Generating a secondary instruction code assigned to a code; generating a predecoder logic for generating a logical structure for converting the secondary instruction code into the primary instruction code using programmable logic; and generating the predecoder logic. The program based on the secondary instruction code is converted into a primary instruction code by a predecoder composed of programmable logic obtained by Converting to 1
Converting the next instruction code into a plurality of control signals;
Executing a predetermined process based on the control signal.

According to a second aspect of the present invention, there is provided a microcomputer for performing arithmetic processing using each step included in the arithmetic processing method according to the first aspect of the present invention.
An instruction memory for storing a program consisting of the next instruction code, a predecoder consisting of programmable logic programmed by the logic structure generated in the predecoder logic generation step, and a plurality of primary instruction codes output from the predecoder. It is configured to include an instruction decoder for converting into a control signal, and a computing unit / control device / register group for executing a predetermined process based on a plurality of control signals output from the instruction decoder.

According to a third aspect of the present invention, there is provided a microcomputer for performing arithmetic processing using each step included in the arithmetic processing method according to the first aspect of the present invention.
An instruction memory for storing a program consisting of the next instruction code, a predecoder consisting of a programmable logic programmed by the logic structure generated by the predecoder logic generation step, and instruction data consisting of a secondary instruction code retrieved from the instruction memory , An instruction code buffer for supplying a plurality of secondary instruction codes to the predecoder, an instruction decoder for converting a plurality of primary instruction codes output from the predecoder into a plurality of control signals, and the predecoder And a group of operation units / control devices / registers for executing a predetermined process based on a plurality of control signals output from the instruction decoder.

A microcomputer according to a fourth aspect is the microcomputer according to the second or third aspect, wherein the microcomputer is formed on one or a plurality of semiconductor substrates.

According to the above method or configuration, by using a 15-bit secondary instruction code, an instruction memory having a word length of 15 bits is provided.
By using a 32-bit instruction code, the word length is reduced to half or less when compared only with the area of the instruction memory as compared with the case where the instruction memory has a 32-bit word length.

As described above, by allocating only the instructions used in the program among the instructions usable in the microcomputer to the secondary instruction code finally stored in the instruction memory, the degree of freedom of the instructions is sacrificed. Without doing
Minimize instruction length.

The conversion operation from the secondary instruction code to the primary instruction code does not require special control and is realized by a simple conversion of decoding by a predecoder, so that high-speed operation is possible. I do.

The predecoder is a programmable logic whose logic can be easily reconfigured, and can flexibly cope with a case where an instruction used by a program change is changed.

Further, the present method can be applied to an existing microcomputer by adding a predecoder, so that design resources can be effectively used. Hereinafter, an arithmetic processing method according to an embodiment of the present invention and a microcomputer using the same will be specifically described with reference to the drawings. Here, a case where the present invention is embodied in a digital signal processor will be described as an example.

First, the arithmetic processing method of the present embodiment and the principle of a microcomputer using the same will be described. FIG. 1 is a diagram for explaining the principle of an arithmetic processing method according to the present embodiment and a microcomputer using the same. In FIG. 1, the primary instruction code input to the instruction decoder 80 has an instruction length of m bits (m: natural number) sufficient to control the operation unit / controller / register group 90. This one
The next instruction code is determined when the instruction decoder 80 is designed. Application programs are created using the primary instruction codes. When storing the application program in the instruction memory 60, the following steps are performed.

First, the primary instruction code program analyzing device 20 extracts the used instruction from the program and test vector created by the primary instruction code and analyzes the frequency of occurrence. Next, the secondary instruction code generation device 30 allocates a new secondary instruction code to the primary instruction code used in the program from the analysis result. This secondary instruction code is an instruction code stored in the instruction memory 60. The secondary instruction code has an instruction length of n bits (n: natural number and m ≧ n), which is sufficient to allocate only the code used in the program among the primary instruction codes. For example, as a result of omitting duplicated primary instruction codes in a 1500-step program, 1
When the next instruction code is used, the instruction length of the secondary instruction code is 10 bits (2 10 = 1024).

Simultaneously with the determination of the secondary instruction code, the pre-decoder logic generation device 40 determines the logic of the pre-decoder 70 that converts the secondary instruction code into the primary instruction code. Here, the predecoder 70 outputs a PLA (Progr)
The logic has a structure that can be easily reconfigured, as represented by an enable logic array, a gate array, a GAL, and an FPGA.

The secondary instruction code extracted from the instruction memory 60 is converted into a primary instruction code by the predecoder 70, and
The next instruction code is converted into a plurality of control signals by the instruction decoder 80, and the arithmetic / control device / register group 90 executes a predetermined process based on the control signals. The secondary instruction code is determined at the time of logic generation of the predecoder 70, and a program described using this secondary instruction code is stored in the instruction memory 60. It does not depend on the instruction length of the primary instruction code determined at the time.

The instruction length of the secondary instruction code is shorter than that of the primary instruction code. As a result, the word length of the instruction memory 60 can be shorter than that of the conventional instruction code. If the secondary instruction code has a fixed length of n bits, the predecoder 70
Is simple, but 1 to n depending on the frequency of the instruction.
By making the bit variable length, the capacity of the entire program can be further reduced.

FIG. 2 is a diagram for explaining the operation of the program optimizing device. The program created by the primary instruction code and the test vector which is the input / output pattern of the program are input to the primary instruction code program analysis device 20. In step 21, the primary instruction code used in the program is extracted. In step 22, the number of appearances of each instruction code when the test vector is given to the program is obtained. In step 23, classification is performed for each operation code of the primary instruction code, and in step 24, sorting is performed in the order of the number of appearances.
Based on this information, the secondary instruction code generator 30 allocates a secondary instruction code, and the predecoder logic generator 40 generates a predecoder logical structure. The reason why the classification is performed for each operation code in step 23 is that the logic of the predecoder becomes simpler when the same operation code is put together when the secondary instruction code is assigned. As a similar approach, a method of classifying operands by source / destination or an execution flag condition, or a method of employing a gray code as a secondary instruction code can be considered.

FIG. 3 shows a block diagram of a digital signal processor which is a specific example of the present embodiment. The digital signal processor 100 includes an instruction memory 110, an analog-digital converter (ADC) 120, a digital-analog converter (DAC) 130, an I / O port 1
40, predecoder 150, program control unit 1
60, interrupt control unit 170, I / O control unit 180, emulator interface (ICE) 19
0, clock control unit 200, timer 210, arithmetic unit 220, pointer arithmetic unit 230, register group 240, data memory 250, and data bus 26
0, 270, 280, etc.

The data bus 260 connects the arithmetic unit 220 and the register group 240 to each other. Data bus 2
70 is a pointer operation unit 230 and a register group 240
Are interconnected. The data bus 280 includes the register group 240, the data memory 250, and the I / O control unit 18.
0 are connected to each other.

As shown in FIG. 4, predecoder 150 has a PLA (P) having an AND plane 153 and an OR plane 154.
(Programmable Logic Array) structure. The structure of the predecoder 150 is PL
In addition to the A structure, it is possible to adopt a structure such as a gate array, a GAL, an FPGA, etc., in which logic can be easily reconfigured. The predecoder 150 fetches instruction data for each k bits from the instruction memory 110 and stores the instruction data in the instruction code buffer 151. The instruction code buffer 151 has a buffer length of 2 k bits. Four n-bit secondary instruction codes are stored in the latch 152 from the instruction code buffer 151, the contents of the latch 152 are decoded by the AND plane 153 and the OR plane 154, and the four m-bit primary instruction codes are stored in the program control unit. 160.

Each of the AND plane 153 and the OR plane 154 includes a pipeline register, and changes the number of pipeline stages according to a decoding time. The number of pipeline stages is stored in a pipeline setting register 165 described later, and implements branch control according to the number of pipeline stages.

As shown in FIG. 5, the instruction code buffer 1
51 connects (merges) the fetched k-bit instruction data to the remaining end of the buffer in the previous stage, supplies 4n bits of the secondary instruction code, discards the supplied data, and moves (rotates) the buffer contents. .

As shown in FIG. 6, the primary instruction code converted from four n-bit secondary instruction codes is divided into execution flag condition, operation code, and operand fields.

As shown in FIG. 7, the program control unit 160 stores the four primary instruction codes in the instruction register 16.
1, the contents of the instruction register 161 are decoded by the instruction decoder 162, and the operation unit 220, the pointer operation unit 230, the register group 240, the data memory 2
A control signal is supplied to 50. At the same time, the instruction address stored in the instruction pointer 163 is supplied to the instruction memory 110. Instruction pointer 1
The content of 63 is incremented by the branch control 164 or the branch destination instruction address is stored. The branch control 164 executes an interrupt process according to an interrupt control signal supplied from the interrupt control unit 170 in addition to the normal branch process.

The pipeline setting register 165 stores the number of pipeline stages in the predecoder 150.
The branch control 164 implements branch control according to the contents of the pipeline setting register 165.

The ADC 120 receives an analog signal from an external terminal, converts the signal into a digital signal, and supplies the digital signal to the I / O control unit 180. The DAC 130 inputs a digital signal from the I / O control unit 180, converts the digital signal into an analog signal, and outputs the analog signal to an external terminal. The I / O port 140 converts a digital signal from an external terminal into an I / O control unit 18.
0, and a digital signal from the I / O control unit 180 to an external terminal.

The I / O control unit 180 detects the occurrence of an interrupt from the input signal and supplies an interrupt request signal to the interrupt control unit 170. Also, the contents of the register group 240 and the data memory 250 are read / written via the data bus 280.

The ICE 190 supplies an interrupt request signal to the interrupt control unit 170 according to a control signal from the emulator. The clock control unit 200 supplies a clock to each block, and supplies an interrupt request signal to the interrupt control unit 170 according to an interrupt accompanying the clock control. The timer 210 executes the count of the timer, and the interrupt control unit 1 according to the timer interrupt.
An interrupt request signal is supplied to 70.

The interrupt control unit 170 supplies an interrupt control signal to the program control unit 160 according to an interrupt request signal from each unit. As shown in FIG. 8, the arithmetic unit 220 reads the contents of the register group 240 via the data bus 260 in accordance with the control signal, and outputs the data to the barrel shifter 221, the ALU 222, and the multiplier 22.
3. The operation result obtained by the shifter 224 and the accumulator 225 is written again via the data bus 260.

As shown in FIG. 9, the pointer operation unit 230 stores the contents of the register group 240 in the data bus 270.
Read via, incrementer / decrementer 2
31, the operation result obtained by the ALU 232 is again written via the data bus 270.

The register group 240 supplies the contents of the register as an address to the data memory 250, and reads and writes the content of the data memory 250 via the data bus 280.

FIG. 10 shows the operation timing in this embodiment. When the number of predecode stages is one, the total pipeline length of instruction fetch, predecode, decode, operation / memory read, and memory write is 5 clocks. When the number of predecode stages is three, the pipeline length of predecode is three clocks, and the total length of each pipeline is seven clocks. The number of pipeline stages for this predecoding is stored in the pipeline setting register 165 described above.

As described above, as shown in FIG.
In the case of using a secondary instruction code of n = 15 bits, a word length has an instruction memory of 15 bits, and by using a 32-bit instruction code as in the related art,
Compared with the case where the instruction memory has a word length of 32 bits, the area can be reduced to half or less when compared only with the area of the instruction memory.

Actually, in this method, the area of the pre-decoder is added. However, as will be described in an embodiment to be described later, the same operation code is combined when a secondary instruction code is created, a gray code is used, or the pre-decoder is used. By adopting a method that simplifies the logic of, the increase in area can be minimized.

Further, among instructions usable in the microcomputer, only instructions used in the program are assigned to secondary instruction codes finally stored in the instruction memory, thereby sacrificing the flexibility of instructions. And the instruction length can be minimized.

In addition, the operation of converting the secondary instruction code into the primary instruction code does not require any special control, and is performed by a simple conversion of decoding by the pre-decoder. Can be.

The pre-decoder is a programmable logic whose logic can be easily reconfigured, so that it is possible to flexibly cope with a case where an instruction used by a program change is changed.

Furthermore, the present method can be applied to an existing microcomputer by adding a predecoder, and the design resources can be effectively used. As a result, it is possible to efficiently use resources such as an arithmetic unit and a register while minimizing the increase in the capacity of the instruction memory, and to realize high speed and low cost.

In the present embodiment, the secondary instruction code is described as having a fixed length of n bits. However, by making the secondary instruction code a variable length of 1 to n bits according to the frequency of occurrence of instructions, the capacity of the entire program is further reduced. it can.

Further, the present invention may be embodied in a microcomputer other than the digital signal processor.

[0055]

As described above, according to the present invention, by using a 15-bit secondary instruction code, an instruction memory having a word length of 15 bits is provided.
By using a 32-bit instruction code, the word length can be reduced to half or less when compared only with the instruction memory area, compared to the case where the instruction memory has a 32-bit word length.

As described above, by allocating only the instructions used in the program among the instructions usable in the microcomputer to the secondary instruction codes finally stored in the instruction memory, the flexibility of the instructions is sacrificed. Without doing
Instruction length can be minimized.

The conversion operation from the secondary instruction code to the primary instruction code does not require special control and is realized by a simple conversion of decoding by a predecoder, so that high-speed operation is possible. can do.

Further, the predecoder is a programmable logic whose logic can be easily reconfigured, and can flexibly cope with a change in an instruction used by a program change.

Furthermore, the present method can be applied to an existing microcomputer by adding a predecoder, so that design resources can be effectively used. As described above, the used capacity of the instruction memory can be reduced, and the compression efficiency can be improved and the operation can be performed at higher speed.

As a result, it is possible to efficiently use resources such as an arithmetic unit and a register while minimizing the increase in the capacity of the instruction memory, thereby realizing high speed and low cost.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of an arithmetic processing method according to an embodiment of the present invention and a microcomputer using the same;

FIG. 2 is an operation explanatory diagram of the program optimizing device according to the embodiment;

FIG. 3 is a block diagram showing a configuration example in which the embodiment is embodied in a digital signal processor;

FIG. 4 is a block diagram showing a predecoder in FIG. 3;

FIG. 5 is a diagram for explaining the operation of the instruction code buffer in FIG. 3;

FIG. 6 is a diagram illustrating the operation of the predecoder in FIG. 3;

FIG. 7 is a block diagram showing a program control unit in FIG. 3;

FIG. 8 is a block diagram showing an arithmetic unit in FIG. 3;

FIG. 9 is a block diagram showing a pointer operation unit in FIG. 3;

FIG. 10 is a timing chart showing the operation in FIG. 3;

And FIG. 11 is a block diagram showing a configuration example of a conventional microcomputer.

FIG. 12 is a diagram illustrating the instruction use efficiency of the microcomputer of the conventional example.

FIG. 13 is a diagram illustrating an arithmetic processing method according to an embodiment of the present invention and an effect of reducing an instruction memory area of a microcomputer using the arithmetic processing method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Program optimization apparatus 20 Primary instruction code program analysis apparatus 30 Secondary instruction code generation apparatus 40 Predecoder logic generation apparatus 50,300 Microcomputer 60,110,310 Instruction memory 70,150 Predecoder 80,162,320 Instruction decoder 90,330 Arithmetic unit / controller / register group 100 Digital signal processor 120 Analog-digital converter (ADC) 130 Digital-analog converter (DAC) 140 I / O port 151 Instruction code buffer 152 Latch 153 Pre-decoder logic AND plane 154 OR plane as predecoder logic 160 Program control unit 161 Instruction register 163 Instruction pointer 165 Pipeline setting register 170% Read control unit 180 I / O control unit 190 Emulator interface (ICE) 200 Clock control unit 210 Timer 220 Arithmetic unit 221 Barrel shifter 222,232 ALU 223 Multiplier 224 Shifter 225 Accumulator 230 Pointer arithmetic unit 231 Incrementer / Decrementer 240 Register group 250 data memory 260, 270, 280 data bus

Claims (4)

[Claims] 1. A primary instruction code program analyzing step of extracting a used instruction and analyzing its appearance frequency in a program created by m-bit (m: natural number) primary instruction code, and analyzing the primary instruction code Depending on the result,
A secondary instruction code generating step of newly assigning only the used primary instruction code to a secondary instruction code consisting of n bits (n: natural number and m ≧ n), and using the secondary instruction code by a programmable logic A pre-decoder logic generating step of generating a logical structure for converting the secondary instruction code into the primary instruction code, and a pre-decoder consisting of programmable logic obtained by the pre-decoder logic generating step, the program based on the secondary instruction code is primarily processed. Converting to an instruction code;
Converting the next instruction code into a plurality of control signals;
Performing a predetermined process based on the control signal. 2. A microcomputer for performing arithmetic processing using each step included in the arithmetic processing method according to claim 1, wherein the microcomputer stores a program including a secondary instruction code generated in a secondary instruction code generating step. An instruction memory, a predecoder comprising programmable logic programmed by a logic structure generated by a predecoder logic generation step, and an instruction decoder for converting a primary instruction code output from the predecoder into a plurality of control signals. And a computing unit / control device / register group for executing a predetermined process based on a plurality of control signals output from the instruction decoder. 3. A microcomputer for performing arithmetic processing using each step included in the arithmetic processing method according to claim 1, wherein the microcomputer stores a program including a secondary instruction code generated in a secondary instruction code generating step. An instruction memory, a pre-decoder composed of a programmable logic programmed by a logic structure generated in a pre-decoder logic generation step, and instruction data composed of a secondary instruction code extracted from the instruction memory. An instruction code buffer for supplying an instruction code to the predecoder, an instruction decoder for converting a plurality of primary instruction codes output from the predecoder into a plurality of control signals, and a pipe for storing the number of pipeline stages of the predecoder A line setting register and output from the instruction decoder A microcomputer comprising: a computing unit / control device / register group for executing a predetermined process based on a plurality of control signals. 4. The microcomputer according to claim 2, wherein the microcomputer is formed on one or more semiconductor substrates.